When a MOS FET is used for high-speed switching, the
inductive load and wiring inductance may cause a counter
electromotive voltage at cutoff that the device cannot
withstand.
Avalanche energy capability is the non-clamped ability
to withstand damage expressed as energy. As long as the
energy applied to the device at cutoff is within the
guaranteed avalanche energy capability, the device will not
be damaged even if the Drain-Source voltage exceeds the
capability.
For example, a Drain-Source voltage that is within the
guaranteed capability when electrically stationary may
exceed the limit at startup or cutoff. Usually, a snubber
circuit or similar surge absorbing circuit is used to keep the
Drain-Source voltage within the guaranteed capability.
Sanken MOS FETs, however, do not require this kind of
protective circuit because the avalanche energy capability
is guaranteed. Sanken MOS FETs enable the number of
parts to be reduced, saving board area.
* Consult the engineering department of Sanken when
planning to use MOS FETs in avalanche mode.
The EAS Value in the specifications is guaranteed when
the channel temperature Tch is 25ºC. Since the EAS Value
drops as the channel temperature rises, derating
depending on the temperature is necessary.
Fig.B shows the derating curve for single avalanche
energy capability. This is the derating curve of EAS and the
channel temperature (Tch (start)) immediately before the
avalanche occurs in the product, with the EAS value
(maximum rating) at 25ºC as 100%.
For example, if the product temperature is 50ºC, the EAS
value is derated to 64% of the value at 25ºC.
1. What is avalanche energy capability ?
If the current in an inductive load L is ILP at the moment
when the MOS FET is cut off, EAS can be expressed as
follows:
If the value of L is not known in an actual circuit, EAS
can also be calculated from the actual voltage and current
waveforms as follows:
The following calculation is used to determine EAS
where the voltage and current shown in Fig.A are applied
to the MOS FET in a circuit.
Integrate the overlapping section of ID and VDS to calcu-
late ∫ID•VDS•dt. When the ID waveform is triangular, EAS
will be as follows:
2. EAS calculation method
3. Temperature derating for EAS
This section explains the derating method for continu-
ous avalanche.
Considering continuous avalanche as the repetition of a
single avalanche, the safe operating area (SOA) is deter-
mined using the derating curve shown in Fig. B.
Calculate the energy and Tch (start) of avalanche in the
worst condition and determine SOA using the calculated
data and the derating curve shown in Fig. B. The tempera-
ture rise due to avalanche should not cause the channel
temperature to exceed the maximum rating.
The following is an example of determining SOA judg-
ment by calculation when a MOS FET enters a transient
avalanche state at power-on then changes to a stationary
state.
Supposing that the waveform is as shown in Fig.C until
the MOS FET changes to the stationary state, calculate the
start loss and switching (turn-on/off) Ioss. To simplify the
calculation, the average loss Pa and the last two wave-
forms are used for approximation. (Fig. D)
First, calculate the channel temperature Tch ( ) at time
( ) where the temperature condition is severest.
If the Tch ( ) value is within the maximum rating, there
is no problem as far as the temperature is concerned.
4. Continuous avalanche energy capability
Fig. A
Fig. B
Avalanche energy capability of MOS FET
EAS = • L • ILp2 •VDSS
VDSS – VDD
1
2
EAS =
•10(A) • 550(V) • 10(µs) = 27.5(mJ)
* VDD: Supply voltage
EAS = Ps•t
* Ps: Surge power * t: Surge time
0
0
ID
VDS
10A
550V
(VDSS)
10µs
100
80
60
40
20
025 50 75 100 125 150
Tch (start) (ºC)
EAS (normalized) (%)
EAS — Tch (start)
4
Sanken MOS FETs feature guaranteed
avalanche energy capability.
1
2
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1
2
ILp = ID max