High Frequency Divider/PLL Synthesizer
Data Sheet
ADF4007
Rev. B
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FEATURES
7.5 GHz bandwidth
Maximum PFD frequency of 120 MHz
Divide ratios of 8, 16, 32, or 64
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
RSET control of charge pump current
Hardware power-down mode
APPLICATIONS
Satellite communications
Broadband wireless access
CATV
Instrumentation
Wireless LANs
GENERAL DESCRIPTION
The ADF4007 is a high frequency divider/PLL synthesizer that
can be used in a variety of communications applications. It can
operate to 7.5 GHz on the RF side and to 120 MHz at the PFD.
It consists of a low noise digital PFD (phase frequency detector), a
precision charge pump, and a divider/prescaler. The divider/
prescaler value can be set by two external control pins to one of
four values (8, 16, 32, or 64). The reference divider is permanently
set to 2, allowing an external REFIN frequency of up to 240 MHz.
A complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and a VCO (voltage
controlled oscillator). Its very high bandwidth means that
frequency doublers can be eliminated in many high frequency
systems, simplifying system architecture and reducing cost.
FUNCTIONAL BLOCK DIAGRAM
REF
IN
RF
IN
A
RF
IN
B
V
DD
N2 N1 GND
R COUNTER
÷ 2
MUX MUXOUT
CPGND R
SET
V
P
CP
PHASE
FREQUENCY
DETECTOR
REFERENCE
CHARGE
PUMP
ADF4007
N COUNTER
÷ 8, ÷ 16,
÷ 32, ÷ 64
M2 M1
04537-001
Figure 1.
ADF4007 Data Sheet
Rev. B | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Reference Input Section ............................................................... 9
RF Input Stage ................................................................................9
Prescaler P ......................................................................................9
R Counter .......................................................................................9
Phase Frequency Detector (PFD) and Charge Pump ...............9
MUXOUT ................................................................................... 10
Applications Information .............................................................. 11
Fixed High Frequency Local Oscillator ................................... 11
Using the ADF4007 as a Divider .............................................. 12
PCB Design Guidelines for Chip Scale Package......................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
7/12—Rev. A to Rev. B
Changes to Figure 2 .......................................................................... 5
Changed Applications Section to Applications Information
Section .............................................................................................. 11
Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) ...... 14
Changes to Ordering Guide .......................................................... 14
12/09—Rev. 0 to Rev. A
Added Exposed Pad Notation to Figure 2 and Table 3................. 5
Changes to Table 5 ............................................................................. 6
Changes to Ordering Guide .......................................................... 14
2/04—Revision 0: Initial Version
Data Sheet ADF4007
Rev. B | Page 3 of 16
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω,
TA = TMAX to TMIN, unless otherwise noted.
Table 1.
Parameter B Version
1
Unit Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RF
IN
) 1.0/7.0 GHz min/max RF input level: +5 dBm to −10 dBm
RF Input Frequency 0.5/7.5 GHz min/max RF input level: +5 dBm to −5 dBm, for lower frequencies,
ensure that slew rate (SR) > 560 V/µs
REF
IN
CHARACTERISTICS
REF
IN
Input Sensitivity 0.8/V
DD
V p-p min/max Biased at AV
/2
REF
IN
Input Frequency 20/240 MHz min/max For f < 20 MHz, use square wave (slew rate > 50 V/µs)
REF
IN
Input Capacitance 10 pF max
REFIN Input Current
±100
µA max
PHASE DETECTOR
Phase Detector Frequency3 120 MHz max
MUXOUT
MUXOUT Frequency3 200 MHz max C
= 15 pF
CHARGE PUMP
I
CP
Sink/Source 5.0 mA typ With R
= 5.1 kΩ
Absolute Accuracy 2.5 % typ With R
= 5.1 kΩ
R
SET
Range 3.0/11 kΩ typ
I
CP
Three-State Leakage 10 nA max T
= 85°C
Sink and Source Current Matching 2 % typ 0.5 V ≤ V
≤ V
− 0.5 V
I
CP
vs. V
CP
1.5 % typ 0.5 V ≤ V
≤ V
− 0.5 V
I
CP
vs. Temperature 2 % typ VCP = V
/2
LOGIC INPUTS
V
IH
, Input High Voltage 1.4 V min
V
IL
, Input Low Voltage 0.6 V max
I
INH
, I
INL
, Input Current ±1 µA max T
= 25°C
C
IN
, Input Capacitance 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage V
DD
− 0.4 V min I
= 100 µA
VOL, Output Low Voltage
0.4
V max
POWER SUPPLIES
AV
DD
2.7/3.3 V min/max
DV
DD
AV
DD
V
P
AV
DD
/5.5 V min/max AV
≤ V
≤
5.5 V
I
DD
4 (AI
DD
+ DI
DD
) 17 mA max 15 mA typ
I
P
2.0 mA max T
= 25°C
NOISE CHARACTERISTICS
Normalized Phase Noise Floor5 −219 dBc/Hz typ
1 Operating temperature range (B version) is −40°C to +85°C.
2 AC coupling ensures AVDD/2 bias. See Figure 13 for typical circuit.
3 Guaranteed by design. Characterized to ensure compliance.
4 TA = 25°C; AVDD = DVDD = 3 V; N = 64; RFIN = 7.5 GHz.
5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logFPFD. PNSYNTH = PNTOT − 10logFPFD − 20logN. The in-band phase noise (PNTOT) is measured using the HP8562E Spectrum Analyzer from Agilent.
ADF4007 Data Sheet
Rev. B | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
AV
DD
to GND1 −0.3 V to +3.6 V
AV
DD
to DV
DD
−0.3 V to +0.3 V
V
P
to GND −0.3 V to +5.8 V
V
P
to AV
DD
−0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND −0.3 V to V
P
+ 0.3 V
REFIN, RFINA, RFINB to GND
−0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
CSP θ
JA
Thermal Impedance 122°C/W
Lead Temperature, Soldering
Vapor Phase (60 s) 215°C
Infrared (15 s) 220°C
Transistor Count
CMOS 6425
Bipolar 303
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
1 GND = AGND = DGND = 0 V.
Data Sheet ADF4007
Rev. B | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
14
13
12
1
3
4
M1
15 MUXOUT
M2
N1
11 N2
CPGND
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT
MUST BE CO NNE CTED TO G ROUND.
AGND 2
AGND
RF
IN
B5
RF
IN
A
7
AV
DD
6
AV
DD
8
REF
IN
9
DGND 10
DGND
19 R
SET
20 CP
18 V
P
17 DV
DD
16 DV
DD
TOP
VIEW
ADF4007
04537-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 CPGND Charge Pump Ground. The ground return path of the charge pump.
2, 3 AGND Analog Ground. The ground return path of the prescaler.
4 RFINB Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
5 RF
IN
A Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
6, 7 AVDD Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD
.
8 REFIN Reference Input. A CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ.
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9, 10 DGND Digital Ground.
11, 12 N2, N1 These two bits set the N value. See Table 4.
13, 14 M2, M1 These two bits set the status of MUXOUT and PFD polarity. See Table 5.
15 MUXOUT This multiplexer output allows either the N divider output or the R divider output to be accessed externally.
16, 17 DVDD Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
18
V
P
Charge Pump Power Supply. This pin should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it can be
set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
19 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAXCP
R
I5.25
=
Therefore, if R
SET
= 5.1 kΩ, then I
CP
= 5 mA.
20
CP
Charge Pump Output. When enabled, this pin provides ±I
CP
to the external loop filter, which in turn drives the
external VCO.
21 EP Exposed Pad.
ADF4007 Data Sheet
Rev. B | Page 6 of 16
Table 4. N Truth Table
N2 N1 N Value
0 0 8
0 1 16
1 0 32
1 1 64
Table 5. M Truth Table
M2 M1 Operation Description
0 0 CP Active
MUXOUT V
DD
PFD polarity +ve
0 1 CP Three-state
MUXOUT R divider output/2
PFD polarity +ve
1 0 CP Active
MUXOUT N divider output
PFD polarity +ve
1 1 CP Active
MUXOUT GND
PFD polarity:
−ve
Data Sheet ADF4007
Rev. B | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
Table 6. S-Parameter Data for the RF Input
Frequency1 MagS11 AngS11
0.60000 0.87693 −19.9279
0.70000 0.85834 −23.5610
0.80000 0.85044 −26.9578
0.90000 0.83494 −30.8201
1.00000 0.81718 −34.9499
1.10000 0.80229 −39.0436
1.20000 0.78917 −42.3623
1.30000
0.77598
−46.3220
1.40000 0.75578 −50.3484
1.50000 0.74437 −54.3545
1.60000 0.73821 −57.3785
1.70000 0.72530 −60.6950
1.80000
0.71365
−63.9152
1.90000 0.70699 −66.4365
2.00000 0.70380 −68.4453
2.10000 0.69284 −70.7986
2.20000 0.67717 −73.7038
2.30000 0.67107 −75.8206
2.40000 0.66556 −77.6851
2.50000 0.65640 −80.3101
2.60000 0.63330 −82.5082
2.70000 0.61406 −85.5623
2.80000 0.59770 −87.3513
2.90000 0.56550 −89.7605
3.00000
0.54280
−93.0239
3.10000 0.51733 −95.9754
3.20000 0.49909 −99.1291
3.30000 0.47309 −102.208
3.40000 0.45694 −106.794
3.50000
0.44698
−111.659
3.60000 0.43589 −117.986
3.70000 0.42472 −125.620
3.80000 0.41175 −133.291
3.90000 0.41055 −140.585
4.00000 0.40983 −147.970
4.10000 0.40182 −155.978
4.20000 0.41036 −162.939
Frequency1 MagS11 AngS11
4.30000 0.41731 −168.232
4.40000 0.43126 −174.663
4.50000 0.42959 −179.797
4.60000 0.42687 174.379
4.70000 0.43450 171.537
4.80000 0.42275 167.201
4.90000 0.40662 163.534
5.00000
0.39103
159.829
5.10000 0.37761 157.633
5.20000 0.34263 152.815
5.30000 0.30124 147.632
5.40000 0.27073 144.304
5.50000
0.23590
138.324
5.60000 0.17550 131.087
5.70000 0.12739 124.568
5.80000 0.09058 119.823
5.90000 0.06824 114.960
6.00000 0.04465 84.4391
6.10000 0.04376 34.2210
6.20000 0.06621 4.70571
6.30000 0.08498 −12.6228
6.40000 0.10862 −26.6069
6.50000 0.12161 −38.5860
6.60000 0.12917 −47.1990
6.70000
0.12716
−55.8515
6.80000 0.11678 −63.0234
6.90000 0.10533 −66.9967
7.00000 0.09643 −75.4961
7.10000 0.08919 −89.2055
7.20000
0.08774
−103.786
7.30000 0.09289 −127.153
7.40000 0.10803 −150.582
7.50000 0.13956 −170.971
1Frequency unit: GHz; parameter type: s; data format: MA; keyword: R;
impedance: 50.
ADF4007 Data Sheet
Rev. B | Page 8 of 16
–40
–35
–30
–25
–20
–15
–10
–5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
V
DD
= 3V
V
P
= 3V
RF INPUT FREQUENCY ( GHz)
RF INPUT P OW E R ( dBm)
0
T
A
= +85°C
T
A
= +25°C T
A
= –40° C
04537-003
Figure 3. Input Sensitivity
0
–60
–2k
–10
–50
–70
–90
–30
–40
–80
–20
2k6780M–1k 1k
–100
VDD = 3V , VP = 5V
ICP = 5mA
PF D FREQ UE NCY = 106kHz
LOOP BANDWI DTH = 1M Hz
RES BANDWIDTH = 10Hz
VI DE O BANDWIDT H = 10Hz
SWEEP = 1.9s
AVERAGES = 10
–99dBc/Hz
FRE QUENCY ( Hz )
OUTPUT POWER (dB)
REF LEVE L = –14.3d Bm
04537-005
Figure 4. Phase Noise (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop
Bandwidth)
10k 100M
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
FRE QUENCY OF FSE T F ROM CARRI E R ( Hz )
PHASE NOISE (d Bc/Hz)
10dB/DIV
RL = –40dBc/Hz
RMS NOIS E = 4.2°
04537-006
100k 1M 10M
Figure 5. Integrated Phase Noise (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz
Loop Bandwidth)
0
–60
–10
–50
–70
–90
–30
–40
–80
–20
–100
OUTPUT POWER (dB)
REF LEVE L = –14.0d Bm
–212 212
6780–106 106
FREQUENCY (MHz)
VDD = 3V , VP = 5V
ICP = 5mA
PF D FREQ UE NCY = 106M Hz
LOOP BANDWI DTH = 1M Hz
RES BANDWIDTH = 1kHz
VI DE O BANDWIDT H = 1kHz
SWEEP = 2.5s
AVERAGES = 30
–91.0dBc/Hz
04537-007
Figure 6. Reference Spurs (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop
Bandwidth)
–120
–130
–18010k 120M
100k 1M 10M
–140
–150
–160
–170
PHASE DE TECT OR F RE QUENCY ( Hz )
PHASE NOISE (d Bc/Hz)
V
DD
= 3V
V
P
= 5V
04537-013
Figure 7. Phase Noise (Referred to CP Output) vs. PFD Frequency
–6
–5
602.00.5 1.0 1.5
–4
–3
–2
–1
V
CP
(V)
I
CP
(mA)
0
1
2
3
4
5
4.02.5 3.0 3.5 5.04.5
V
P
= 5V
I
CP
= 5mA
04537-014
Figure 8. Charge Pump Output Characteristics
Data Sheet ADF4007
Rev. B | Page 9 of 16
THEORY OF OPERATION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 9. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
100kΩ
NC
REFIN NC
NO
SW1
SW2
BUFFER
SW3
TO R COUNTER
POWER-DOWN
CONTROL
04537-015
Figure 9. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 10. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
500Ω
1.6V
500Ω
AGND
BIAS
GENERATOR
RFINA
RFINB
AVDD
04537-016
Figure 10. RF Input Stage
PRESCALER P
The prescaler, operating at CML levels, takes the clock from the
RF input stage and divides it down to a manageable frequency
for the PFD. The prescaler can be selected to be either 8, 16, 32,
or 64, and is effectively the N value in the PLL synthesizer. The
terms N and P are used interchangeably in this data sheet. N1
and N2 set the prescaler values. The prescaler value should be
chosen so that the prescaler output frequency is always less than
or equal to 120 MHz, the maximum specified PFD frequency.
Thus, with an RF frequency of 4 GHz, a prescaler value of 64 is
valid, but a value of 32 or less is not valid.
2
][
REFIN
VCO
f
Nf ×=
R COUNTER
The R counter is permanently set to 2. It allows the input reference
frequency to be divided down by 2 to produce the reference clock
to the phase frequency detector (PFD).
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and the N counter
(prescaler, P) and produces an output proportional to the phase
and frequency difference between them. Figure 11 is a simplified
schematic. The PFD includes a fixed, 3 ns delay element that
controls the width of the antibacklash pulse. This pulse ensures
that there is no dead zone in the PFD transfer function and
minimizes phase noise and reference spurs.
LOGIC HI D1
D2
Q1
Q2
CLR1
CLR2
CP
U1
U2
UP
DOWN
CPGND
U3
R DIV IDER
3ns
DELAY
N DIV IDER
V
P
CHARGE
PUMP
04537-017
LOGIC HI
Figure 11. PFD Simplified Schematic and Timing (In Lock)
ADF4007 Data Sheet
Rev. B | Page 10 of 16
MUXOUT
The output multiplexer on the ADF4007 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by the M2 and M1 pins. Figure 12
shows the MUXOUT section in block diagram form.
DGND
DVDD
CONTROL
MUX
DVDD
R COUNTER OUTPUT
N COUNTER OUTPUT
DGND
MUXOUT
04537-018
Figure 12. MUXOUT Circuit
PFD Polarity
The PFD polarity is set by the state of M2 and M1 pins as given
in the Table 5. The ability to set the polarity allows the use of VCOs
with either positive or negative tuning characteristics. For standard
VCOs with positive characteristics (output frequency increases
with increasing tuning voltage), the polarity should be set to
positive. This is accomplished by tying M2 and M1 to a logic
low state.
CP Output
The CP output state is also controlled by the state of M2 and M1. It
can be set either to active (so that the loop can be locked) or to
three-state (open the loop). The normal state is CP output active.
Data Sheet ADF4007
Rev. B | Page 11 of 16
APPLICATIONS INFORMATION
FIXED HIGH FREQUENCY LOCAL OSCILLATOR
Figure 13 shows the ADF4007 being used with the HMC358MS8G
VCO from Hittite Microwave Corporation to produce a fixed-
frequency LO (local oscillator), which could be used in satellite
or CATV applications. In this case, the desired LO is 6.7 GHz.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 Ω. Many systems would
have either a TCXO or an OCXO driving the reference input
without any 50 Ω termination. To bias the REFIN pin at AVDD/2,
ac coupling is used. The value of the coupling capacitor used
depends on the input frequency. The equivalent impedance at
the input frequency should be less than 10 Ω. Given that the dc
input impedance at the REFIN pin is 100 kΩ, less than 0.1% of
the signal is lost.
The charge pump output of the ADF4007 drives the loop filter.
In calculating the loop filter component values, a number of items
need to be considered. In this example, the loop filter was designed
so that the overall phase margin for the system is 45°.
Other PLL system specifications are as follows:
KD = 5 mA
KV = 100 MHz/V
Loop Bandwidth = 300 kHz
FPFD = 106 MHz
N = 64
All these specifications are needed and used with the ADIsimPLL
to derive the loop filter component values shown in Figure 13.
The circuit in Figure 13 gives a typical phase noise performance
of −100 dBc/Hz at 10 kHz offset from the carrier. Spurs are
heavily attenuated by the loop filter and are below −90 dBc.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the RFIN
terminal of the synthesizer.
ADF4007
N2
N1
M2
M1
100pF 100pF
100pF
CP
MUXOUT
GND
GND
GND
5.6nF
51Ω
18Ω
22Ω
NOTE
DECO UP LING CAPACITORS (0.1mF/10pF) ONAV
DD
, DV
DD
,AND V
P
OF THEADF4007 AND O N
V
CC
OF THEAD820 AND THE HM C358M S 8G HAV E BE E N OMITTED FRO M THE DIAG RAM
TO AID CLARIT Y.
R
SET
AV
DD
DV
DD
V
P
FREF
IN
VCO
100MHz/V
HMC358MS8G
R
SET
5.1kΩ
617 18
8
20
15
19
9
3
2
10
04537-019
RF
IN
A
RF
IN
B
5
4
11
12
13
14
GND
47nF
AV
DD
7
DV
DD
16
REF
IN
AV
DD
= 3.3V
1kΩ
18kΩ
V
CC
= 12V
V
CC
= 3.3V
1kΩ
AD820 10pF
18Ω
100pF 18Ω100pF RF
OUT
LOGIC HI
LOGIC HI
LOGIC LO
LOGIC LO
Figure 13. 6.78 GHz Local Oscillator Using the ADF4007
ADF4007 Data Sheet
Rev. B | Page 12 of 16
USING THE ADF4007 AS A DIVIDER
In addition to its use as a standard PLL synthesizer, the ADF4007
can also be used as a high frequency counter/divider with a value
of 8, 16, 32, or 64.This can prove useful in a wide variety of
applications where a higher frequency signal is readily available.
Figure 14 shows the ADF4007 used in this manner with the
ADF4360-7.
This part is an integrated synthesizer and VCO, in this case
operating over a range of 1200 MHz to 1500 MHz. With divide-
by-8 chosen in the ADF4007 (N2 = 0, N1 = 0), the output range
is 150 MHz to 187.50 MHz.
ADF4360-7
ADF4007
470pF6.8nF
6.2kΩ
13kΩ
220pF
CLK
DATA
LE
4.7kΩ
R
SET
CP
V
TUNE
17
18
RF
OUT
A
1nF
C
C
CPGND AGND DGND
AV
DD
DV
DD
V
VCO
C
N
10mF
V
VCO
CE
REF
IN
FREF
IN
1nF
MUXOUT
LOCK
DETECT
RF
IN
B
V
P
AV
DD
100pF
100pF
V
VCO
CMOS OUT P UT
51Ω
19
12
13
1310
811 22 15 5
4
7
24
20
23
2
21
6
14
16
9
L2
51Ω
2.2nH
MUXOUT
REF
IN
PHASE
FREQUENCY
DETECTOR MUX
CHARGE
PUMP
CP
R COUNT E R
÷ 2
R
SET
N COUNT E R
÷8, ÷16
÷32, ÷64
N1 N2
CPGND GND
M2 M1
4.7kΩ
V
DD
SPI COMP ATI BLE SE RIAL BUS
RF
OUT
B
2.2nH
L1
1nF
V
DD
RF
IN
A
51Ω
04537-020
DV
DD
Figure 14. Using the ADF4007 to Divide-Down the Output of the ADF4360-7
Data Sheet ADF4007
Rev. B | Page 13 of 16
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the chip scale package (CP-20-6) are rectangular.
The printed circuit board pad for these should be 0.1 mm longer
than the package land length and 0.05 mm wider than the package
land width. Center the land on the pad to ensure that the solder
joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. The printed circuit board should have
a clearance of at least 0.25 mm between the thermal pad and the
inner edges of the pad pattern to ensure that shorting is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.30 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
Connect the printed circuit board thermal pad to AGND.
ADF4007 Data Sheet
Rev. B | Page 14 of 16
OUTLINE DIMENSIONS
0.50
BSC
0.65
0.60
0.55
0.30
0.25
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-1.
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.30
2.10 SQ
2.00
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
1516
5
08-16-2010-B
Figure 15. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
ADF4007BCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADF4007BCPZ-RL −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADF4007BCPZ-RL7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
EVAL-ADF4007EBZ1 Evaluation Board
1 Z = RoHS compliant part.
Data Sheet ADF4007
Rev. B | Page 15 of 16
NOTES
ADF4007 Data Sheet
Rev. B | Page 16 of 16
NOTES
©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04537-0-7/12(B)