UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
BiCMOS ADVANCED PHASE-SHIFT
PWM CONTROLLER
1
www.ti.com
FEATURES
DProgrammable Output Turn-on Delay
DAdaptive Delay Set
DBidirectional Oscillator Synchronization
DVoltage-Mode, Peak Current-Mode, or
Average Current-Mode Control
DProgrammable Softstart/Softstop and Chip
Disable via a Single Pin
D0% to 100% Duty-Cycle Control
D7-MHz Error Amplifier
DOperation to 1 MHz
DTypical 5-mA Operating Current at 500 kHz
DVery Low 150-μA Current During UVLO
APPLICATIONS
DPhase-Shifted Full-Bridge Converters
DOff-Line, Telecom, Datacom and Servers
DDistributed Power Architecture
DHigh-Density Power Modules
DESCRIPTION
The UCC3895 is a phase-shift PWM controller
that implements control of a full-bridge power
stage by phase shifting the switching of one
half-bridge with respect to the other. It allows
constant frequency pulse-width modulation in
conjunction with resonant zero-voltage switching
to provide high efficiency at high frequencies. The
part can be used either as a voltage-mode or
current-mode controller.
While the UCC3895 maintains the functionality of
the UC3875/6/7/8 family and UC3879, it improves
on that controller family with additional features
such as enhanced control logic, adaptive delay
set, and shutdown capability. Since it is built using
the BCDMOS process, it operates with
dramatically less supply current than it’s bipolar
counterparts. The UCC3895 can operate with a
maximum clock frequency of 1 MHz.
UDG--03123
1
10 11
12
13
14
15
16
17
18
19
77777777720
2
3
4
5
6
7
8
9
UCC3895
EAN EAP
EAOUT
RAMP
REF
GND
SYNC
CT
RT
DELAB
DELCD ADS
CS
OUTD
OUTC
VCC
PGND
OUTB
OUTA
SS/DISB
Q1
DB
AC
VIN
VOUT
VBIAS
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright ©2008 -- 2010, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
2www.ti.com
ORDERING INFORMATION
PACKAGED DEVICES
TASOIC--20(DW)(1) PDIP--20(N) TSSOP--20(PW)
(1) PLCC--20(Q)(1) CLCC--20(L) CDIP--20(J)
-- 5 5 °C to 125°C UCC1895L UCC1895J
-- 4 0 °Cto85°CUCC2895DW UCC2895N UCC2895PW UCC2895Q
0°Cto70°CUCC3895DW UCC3895N UCC3895PW UCC3895Q
(1) The DW, PW and Q packages are available taped and reeled. Add TR suffix to device
type (e.g. UCC2895DWTR) to order quantities of 2000 devices per reel for DW.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EAN
EAOUT
RAMP
REF
GND
SYNC
CT
RT
DELAB
DELCD
EAP
SS/DISB
OUTA
OUTB
PGND
VDD
OUTC
OUTD
CS
ADS
N and J PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EAN
EAOUT
RAMP
REF
GND
SYNC
CT
RT
DELAB
DELCD
EAP
SS/DISB
OUTA
OUTB
PGND
VDD
OUTC
OUTD
CS
ADS
PW and DW PACKAGE
(TOP VIEW)
QandLP
A
C
K
A
GE
(TOP VIEW)
3
18
17
16
EAN
122019
15
14
4
5
6
7
8
91110 12 13
EAOUT
RAMP
EAP
SS/DISB
OUTA
OUTB
OUTC
OUTD
PGND
REF
GND
SYNC
CT
RT
VDD
CS
ADS
DELAB
DELCD
PART TJA TJC UNIT
UCC2895DW 90 25
UCC2895N 80 35
UCC2895PW 125 14 o
C
/
W
UCC2895Q 75 34
o
C
/
W
UCC1895J 85 28
UCC1895L 80 20
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
3
www.ti.com
ABSOLUTE MAXIMUM RATINGS
All voltage values are with respect to the network ground terminal unless otherwise noted. (2)
UCCx895N UNIT
Supply voltage (IDD <10mA) 17 V
Supply current 30
Reference current 15 mA
Output crrent 100
m
A
Analog inputs EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB --0.3 V to REF+0.3 V
Drive outputs OUTA, OUTB, OUTC, OUTD --0.3 V to VCC + 0.3 V
o
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i
s
s
i
p
a
t
i
o
n
a
t
T
2
5
°
C
DW--20 package 650 mW
Power dissipation at TA=25°CN--20 package 1 W
Storage temperature range, Tstg --65 to 150
Junction temperature range, TJ--55 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300
C
(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions” is
not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability
RECOMMENDED OPERATING CONDITIONS(3)
MIN TYP MAX UNIT
Supply voltage, VDD 10 16.5 V
Supply voltage bypass capacitor, VDD(1) 10 x CREF
Reference bypass capacitor, CREF(2) (UCC1895) 0.1 1.0 μF
Reference bypass capacitor, CREF(2) (UCC2895, UCC3895) 0.1 4.7
μ
F
Timing capacitor, CT(for 500 kHz switching frequency) 220 pF
Timing resistor, RT(for 500 kHz switching frequency) 82
k
Ω
Delay resistor RDEL_AB, RDEL_CD 2.5 40 kΩ
Operating junction temperature, TJ(4) -- 5 5 125 °C
(1) The VDD capacitor should be a low ESR, ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk capacitor should
belocated as physically close as possible to the VDD pins.
(2) The VREF capacitor should be a low ESR, ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is desired
for the VREF then it should be located near the VREF cap and connected to the VREF pinwitharesistorof51Ωor greater. The bulk capacitor on
VDD must be a factor of 10 greater than the total VREF capacitance.
(3) It is recommended that there be a single point grounded between GND and PGND directly under the device. There should be a seperate ground
plane associated with the GND pin and all components associated with pins 1 through 12 plus 19 and 20 be located over this ground plane. Any
connections associated with these pins to ground should be connected to this ground plane.
(4) It is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
4www.ti.com
ELECTRICAL CHARACTERISTICS VDD =12V,R
T=82kΩ,C
T= 220 pF, RDELAB =10kΩ,R
DELCD =10kΩ,C
REF =0.1μF,
CVDD =0.1 μF and no load on the outputs, TA=T
J.T
A=0°Cto70°C for UCC3895x, TA=--40°Cto85°C for UCC2895x and TA = --55°Cto125°C
for the UCC1895x. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
UVLO (UNDERVOLTAGE LOCKOUT)
UVLO(on) Start-up voltage threshold 10.2 11 11.8
UVLO(off)
Minimum operating voltage after
start-up 8.2 99.8 V
UVLO(hys) Hysteresis 1.0 2.0 3.0
SUPPLY
ISTART Start-up current VDD = 8 V 150 250 μA
IDD Operating current 5 6 mA
VDD_CLAMP VDD clamp voltage IDD = 10 mA 16.5 17.5 18.5 V
VOLTAGE REFERENCE
TJ=25°C4.94 5.00 5.06
VREF Output voltage 10 V < VDD < VDD_CLAMP
,
0mA<IREF<5mA,
temperature
4.85 55.15 V
ISC Short circuit current REF = 0 V, TJ=25°C10 20 mA
ERROR AMPLIFIER
Common-mode input voltage range -- 0 . 1 3.6 V
VIO Offset voltage -- 7 7mV
IBIAS Input bias current (EAP, EAN) -- 1 1μA
EAOUT_VOH High-level output voltage EAP--EAN = 500 mV, IEAOUT =--0.5mA 4.0 4.5 5.0
EAOUT_VOL Low-level output voltage EAP--EAN = --500 mV, IEAOUT =0.5mA 00.2 0.4
ISOURCE Error amplifier output source current EAP--EAN = 500 mV, EAOUT = 2.5 V 1.0 1.5
m
A
ISINK Error amplifier output sink current EAP--EAN = --500 mV, EAOUT = 2.5 V 2.5 4.5 m
A
AVOL Open-loop dc gain 75 85 dB
GBW Unity gain bandwidth(1) 5.0 7.0 MHz
Slew rate(1) 1 V < EAN < 0 V, EAP = 500 mV
0.5 V < EAOUT < 3.0 V 1.5 2.2 V/μs
No-load comparator turn-off
threshold 0.45 0.50 0.55
No-load comparator turn-on
threshold 0.55 0.60 0.69 V
No-load comparator hysteresis 0.035 0.10 0.165
OSCILLATOR
fOSC Frequency TJ=25°C473 500 527 kHz
Frequency total variation(1) Over line, temperature 2.5% 5%
VIH_SYNC SYNC input threshold, SYNC 2.05 2.10 2.40
VOH_SYNC High-level output voltage, SYNC ISYNC = --400 μA, VCT =2.6V 4.1 4.5 5.0 V
VOL_SYNC Low-level output voltage, SYNC ISYNC = 100 μA, VCT =0.0V 0.0 0.5 1.0
Sync output pulse width LOADSYNC =3.9kΩand 30 pF in parallel 85 135 ns
VRT Timing resistor voltage 2.9 33.1
VCT(peak) Timing capacitor peak voltage 2.25 2.35 2.55 V
VCT(valley) Timing capacitor valley voltage 0.0 0.2 0.4
(1) Ensured by design. Not production tested.
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
5
www.ti.com
ELECTRICAL CHARACTERISTICS VDD =12V,R
T=82kΩ,C
T= 220 pF, RDELAB =10kΩ,R
DELCD =10kΩ,C
REF =0.1μF,
CVDD =0.1 μF and no load on the outputs, TA=T
J.T
A=0°Cto70°C for UCC3895x, TA=--40°Cto85°C for UCC2895x and TA = --55°C to 125°C
for the UCC1895x. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
CURRENT SENSE
ICS(bias) Current sense bias current 0V<CS< 2.5V, 0VADS<2.5V -- 4 . 5 20 μA
Peak current threshold 1.90 2.00 2.10 V
Overcurrent threshold 2.4 2.5 2.6 V
Current sense to output delay 0V ≤CS ≤2.3 V, DELAB=DELCD=REF 75 110 ns
SOFT-START/SHUTDOWN
ISOURCE Softstart source current SS/DISB = 3.0 V, CS = 1.9 V -- 4 0 -- 3 5 -- 3 0 μA
ISINK Softstart sink current SS/DISB = 3.0 V, CS = 2.6 V 325 350 375 μA
Softstart/disable comparator threshold 0.44 0.50 0.56 V
ADAPTIVE DELAY SET (ADS)
D
L
A
/
D
L
C
D
o
u
t
p
u
t
v
o
l
t
a
g
e
ADS = CS = 0 V 0.45 0.50 0.55 V
DEL
A
B
/
DELCD output voltage ADS=0V, CS=2.0V 1.9 2.0 2.1 V
tDELAY Output delay(1)(3) ADS = CS = 0 V 450 560 620 ns
ADS bias current 0V<ADS<2.5V, 0V<CS<2.5V -- 2 0 20 μA
OUTPUT
VOH High--level output voltage (all outputs) IOUT = --10 mA, VDD to output 250 400 mV
VOL Low-level output voltage (all outputs) IOUT =10mA 150 250 mV
tRRise time(1) CLOAD = 100 pF 20 35 ns
tFFall time(1) CLOAD = 100 pF 20 35 ns
(1) Ensured by design. Not production tested.
(2) Minimum phase shift is defined as:
Φ=180 ×
tf(OUTC)−tf(OUTA)
tPERIOD
or Φ=180 ×
tf(OUTC)−tf(OUTB)
tPERIOD
where
tf(OUTA) = falling edge of OUTA signal, tf(OUTB) = falling edge of OUTB signal
tf(OUTC) = falling edge of OUTC signal, tf(OUTD) = falling edge of OUTD signal
tPERIOD = period of OUTA or OUTB signal
(3) Output delay is measured between OUTA/OUTB or OUTC/OUTD. Output delay is defined as shown below where:
tf(OUTA) = falling edge of OUTA signal, tr(OUTB) = rising edge of OUTB signal
tPERIOD
OUTA
OUTC
OUTA
OUTB
Same applies to OUTB and OUTD Same applies to OUTC and OUTD
tDELAY =t
f(OUTC) -- t f(OUTA) tDELAY =t
R(OUTB) -- t f(OUTA)
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
6www.ti.com
ELECTRICAL CHARACTERISTICS VDD =12V,R
T=82kΩ,C
T= 220 pF, RDELAB =10kΩ,R
DELCD =10kΩ,C
REF =0.1μF,
CVDD =0.1 μF and no load on the outputs, TA=T
J.T
A=0°Cto70°C for UCC3895x, TA=--40°Cto85°C for UCC2895x and TA = 55°Cto125°C
for the UCC1895x. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
PWM COMPARATOR
EAOUT to RAMP input offset voltage RAMP = 0 V, DELAB=DELCD=REF 0.72 0.85 1.05 V
Minimum phase shift(2)
(OUTA to OUTC, OUTB to OUTD) RAMP = 0 V EAOUT = 650 mV .0% .85% 1.4%
tDELAY
Delay(3)
(RAMP to OUTC, RAMP to OUTD)
0 V < RAMP < 2.5 V, EAOUT = 1.2 V,
DELAB=DELCD=REF 70 120 ns
IR(bias) RAMP bias current RAMP < 5 V, CT = 2.2 V -- 5 5μA
IR(sink) RAMP sink current RAMP = 5 V, CT = 2.6 V 12 19 mA
TERMINAL FUNCTIONS
TERMINAL
I
/
O
D
C
R
I
T
I
O
N
NAME NO. I
/
ODESCRIPTION
ADS 11 IAdaptive delay set. Sets the ratio between the maximum and minimum programmed output delay dead time.
CS 12 ICurrent sense input for cycle-by-cycle current limiting and for over-current comparator.
CT 7 I Oscillator timing capacitor for programming the switching frequency. The UCC3895’s oscillator charges CT
via a programmed current.
DELAB 9 I Delay programming between complementary outputs. DELAB programs the dead time between switching of
output A and output B.
DELCD 10 IDelay programming between complementary outputs. DELCD programs the dead time between switching of
output C and output D.
EAOUT 2I/O Error amplifier output.
EAP 20 INon-inverting input to the error amplifier. Keep below 3.6 volts for proper operation.
EAN 1 I Inverting input to the error amplifier. Keep below 3.6 volts for proper operation.
GND 5-- Chip ground for all circuits except the output stages.
OUTA 18 O
OUTB 17 OThe
f
our out
p
uts are 100-m
A
com
p
lementar
y
MOS drivers
,
and are o
p
timized to drive FET driver circuits
OUTC 14 O
T
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e
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s
such as UCC27424 or gate drive transformers.
OUTD 13 O
PGND 16 -- Output stage ground.
RAMP 3 I Inverting input of the PWM comparator.
REF 4 O 5V,±1.2%, 5 mA voltage reference. For best performance, bypass with a 0.1-μF low ESR, low ESL capacitor
to ground. Do not use more than 4.7 μF of total capacitance on this pin.
RT 8 I Oscillator timing resistor for programming the switching frequency.
SS/DISB 19 ISoft-start/disable. This pin combines the two independent functions.
SYNC 6I/O Oscillator synchronization. This pin is bidirectional.
VDD 15 IPower supply input pin. VDD must be bypassed with a minimum of a 1.0-μF low ESR, low ESL capacitor to
ground. The addition of a 10--μF low ESR, low ESL between VDD and PGND is recommended.
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
7
www.ti.com
BLOCK DIAGRAM
UDG--98140
OSC
Q
Q
Q
QD
Q
Q
S
R
0.5V
11 V / 9 V
Q
QD
Q
D
2V
2.5 V
REF
4V
0.5 V
REF
0.5 V / 0.6 V
19
8
7
6
2
20
1
12
5
4
11
16
13
10
14
17
9
18
15
+
3
SS
CS
EAN
EAP
EAOUT
RAMP
SYNC
CT
RT
GND
REF
ADS
OUTD
PGND
DELCD
OUTC
OUTB
DELAB
OUTA
VDD
DELAY C
DELAY D
DELAY A
DELAY B
Q
IRT
10(IRT)
DISABLE
COMPARATOR
OVER CURRENT
COMPARATOR
ERROR
AMP
CURRENT SENSE
COMPARATOR
PWM
COMPARATOR
S
R
S
R
IRT
8(IRT )
NO LOAD
COMPARATOR
S
R
0.8 V
ADAPTIVE DELAY
SET AMPLIFIER
UVLO COMPARATOR
REFERENCE OK
COMPARATOR
+
+
+
+
+
+
+
+
+
HI = ON
HI = ON
UDG--03135
SYNC
CT
VREF
CLOCK
CLOCK
0.2 V
2.5 V
REF
RT
IRT
CT
RT
8xI
RT
+
+
SQ
R
Figure 1. Oscillator Block Diagram
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
8www.ti.com
UDG--98141
0.5 V
ADS
CS
DELCD
DELAB
REF
TO DELAY A
AND DELAY B
BLOCKS
REF
TO DELAY C
AND DELAY D
BLOCKS
+
+
+
75 kΩ
75 kΩ
100 kΩ
100 kΩ
Figure 2. Adaptive Delay Set Block Diagram
REF
DELAYED
CLOCK
SIGNAL
3.5 V
DELAB/CD
FROM PAD
2.5 V
CLOCK
BUSSED CURRENT
FROM ADS CIRCUIT
UDG--03132
Figure 3. Delay Block Diagram (One Delay Block Per Outlet)
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
9
www.ti.com
DETAILED PIN DESCRIPTION
Adaptive Delay Set (ADS)
This function sets the ratio between the maximum and minimum programmed output-delay dead time. When
the ADS pin is directly connected to the CS pin, no delay modulation occurs. The maximum delay modulation
occurs when ADS is grounded. In this case, delay time is four times longer when CS = 0 than when CS = 2.0 V
(the peak-current threshold), ADS changes the output voltage on the delay pins DELAB and DELCD by the
following formula:
VDEL =0.75 ×VCS −VADS+0.5 V
where VCS and VADS are in volts. ADS must be limited to between 0 V and 2.5 V and must be less than or equal
to CS. DELAB and DELCD are clamped to a minimum of 0.5 V.
Current Sense (CS)
The inverting input of the current-sense comparator and the non-inverting input of the overcurrent comparator
and the ADS amplifier. The current sense signal is used for cycle-by-cycle current limiting in peak current mode
control, and for overcurrent protection in all cases with a secondary threshold for output shutdown. An output
disable initiated by an overcurrent fault also results in a restart cycle, called soft stop, with full soft start.
Oscillator Timing Capacitor (CT)
The UCC3895’s oscillator charges CT via a programmed current. The waveform on CTis a sawtooth, with a peak
voltage of 2.35 V. The approximate oscillator period is calculated by the following formula:
tOSC =5×RT×CT
48 +120 ns
where CTis in Farads, and RTis in Ohms and tOSC is in seconds. CTcan range from 100 pF to 880 pF.
NOTE: A large CTandasmallR
Tcombination results in extended fall times on the CTwaveform.
The increased fall time increases the SYNC pulse width, hence limiting the maximum phase shift
between OUTA, OUTB and OUTC, OUTD outputs, which limits the maximum duty cycle of the
converter. (Refer to Figure 1)
Delay Programming Between Complementary Outputs (DELAB, DELCD)
DELAB programs the dead time between switching of OUTA and OUTB, and DELCD programs the dead time
between OUTC and OUTD. This delay is introduced between complementary outputs in the same leg of the
external bridge. The UCC2895N allows the user to select the delay, in which the resonant switching of the external
power stages takes place. Separate delays are provided for the two half-bridges to accommodate differences in
resonant-capacitor charging currents. The delay in each stage is set according to the following formula:
tDELAY =(25 ×10−12)×RDEL
VDEL +25 ns
where VDEL (V), and RDEL is in (Ω) and tDELAY is in seconds. DELAB and DELCD can source about 1 mA
maximum. Choose the delay resistors so that this maximum is not exceeded. Programmable output delay is
defeated by tying DELAB and/or DELCD to REF. For an optimum performance keep stray capacitance on these
pins at less than 10 pF.
(1)
(2)
(3)
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
10 www.ti.com
DETAILED PIN DESCRIPTION (continued)
Error Amplifier (EAOUT), (EAP), (EAN)
EAOUT connected internally to the non-inverting input of the PWM comparator and the no-load comparator.
EAOUT is internally clamped to the soft-start voltage. The no-load comparator shuts down the output stages
when EAOUT falls below 500 mV, and allows the outputs to turn on again when EAOUT rises above 600 mV.
EAP is the non--inverting and the EAN is the inverting input to the error amplifier.
Output MOSFET Drivers (OUTA, OUTB, OUTC, OUTD)
The 4 outputs are 100-mA complementary MOS drivers, and are optimized to drive MOSFET driver circuits.
OUTA and OUTB are fully complementary, (assuming no programming delay). They operate near 50% duty
cycle and one-half the oscillator frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an
external power stage. OUTC and OUTD drive the other half-bridge and have the same characteristics as OUTA
and OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB.
NOTE: Changing the phase relationship of OUTC and OUTD with respect to OUTA and OUTB
requires other than the nominal 50% duty ratio on OUTC and OUTD during those transients.
Power Ground (PGND)
To keep output switching noise from critical analog circuits, the UCC3895 has two different ground connections.
PGND is the ground connection for the high-current output stages. Both GND and PGND must be electrically
tied together. Also, since PGND carries high current, board traces must be low impedance.
Inverting Input of the PWM Comparator (RAMP)
This pin receives either the CTwaveform in voltage and average current-mode controls, or the current signal
(plus slope compensation) in peak current-mode control.
Voltage Reference (REF)
The5V,±1.2% reference supplies power to internal circuitry, and can also supply up to 5 mA to external loads.
The reference is shut down during undervoltage lockout but is operational during all other disable modes. For
best performance, bypass with a 0.1-μF, low-ESR, low-ESL capacitor to GND. Do not use more than 1.0 μFof
total capacitance on this pin. To ensure the stability of the internal reference.
Oscillator Timing Resistor (RT)
The oscillator in the UCC3895 operates by charging an external timing capacitor, CT
,withafixedcurrent
programmed by RT
.R
Tcurrent is calculated as follows:
IRT (A) =3.0 V
RT(Ω)
RTcan range from 40 kΩto 120 kΩ. Soft-start charging and discharging currents are also programmed by IRT
(Refer to Figure 1).
Analog Ground (GND)
This pin is the chip ground for all internal circuits except the output stages.
(4)
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
11
www.ti.com
DETAILED PIN DESCRIPTION (continued)
Soft-Start/Disable (SS/DISB)
This pin combines two independent functions.
Disable Mode: A rapid shutdown of the chip is accomplished by externally forcing SS/DISB below 0.5 V,
externally forcing REF below 4 V, or if VDD drops below the undervoltage lockout threshold. In the case of REF
being pulled below 4 V or an undervoltage condition, SS/DISB is actively pulled to ground via an internal
MOSFET switch.
If an overcurrent fault is sensed (CS = 2.5 V), a soft-stop is initiated. In this mode, SS/DISB sinks a constant
current of (10 ×IRT). The soft-stop continues until SS/DISB falls below 0.5 V. When any of these faults are
detected, all outputs are forced to ground immediately.
NOTE:If SS/DISB is forced below 0.5 V, the pin starts to source current equal to IRT
. The only time
the part switches into low IDD current mode, though, is when the part is in undervoltage lockout.
Soft-start Mode: After a fault or disable condition has passed, VDD is above the start threshold, and/or
SS/DISB falls below 0.5 V during a soft-stop, SS/DISB switches to a soft-start mode. The pin then sources
current, equal to IRT
. A user-selected resistor/capacitor combination on SS/DISB determines the soft start time
constant.
NOTE: SS/DISB actively clamps the EAOUT pin voltage to approximately the SS/DISB pin voltage
during both soft-start, soft-stop, and disable conditions.
Oscillator Synchronization (SYNC)
This pin is bidirectional (refer to Figure 1). When used as an output, SYNC can be used as a clock, which is the
same as the device’s internal clock. When used as an input, SYNC overrides the chip’s internal oscillator and
act as it’s clock signal. This bidirectional feature allows synchronization of multiple power supplies. Also, the
SYNC signal internally discharge the CTcapacitor and any filter capacitors that are present on the RAMP pin.
The internal SYNC circuitry is level sensitive, with an input-low threshold of 1.9 V, and an input-high threshold
of 2.1 V. A resistor as small as 3.9 kΩmay be tied between SYNC and GND to reduce the sync pulse width.
Chip Supply (VDD)
This is the input pin to the chip. VDD must be bypassed with a minimum of 1.0 μF low ESR, low ESL capacitor
to ground. The addition of a 10--μF low ESR, low ESL between VDD and PGND is recommended.
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
12 www.ti.com
APPLICATION INFORMATION
Programming DELAB, DELCD and the Adaptive Delay Set
The UCC2895N allows the user to set the delay between switch commands within each leg of the full-bridge
power circuit according to equations:
tDELAY =(25 ×10−12)×RDEL
VDEL +25 ns
From this equation VDEL is determined in conjunction with the desire to use (or not) the adaptive delay set
feature from the following formula:
VDEL =0.75 ×VCS −VADS+0.5 V
The following diagram illustrates the resistors needed to program the delay periods and the adaptive delay set
function.
9
1110
12
DELCD
DELAB
ADS
CS
RDELAB
RDELCD
UCC3895
Figure 4. Programming Adaptive Delay Set
The adaptive delay set feature (ADS) allows the user to vary the delay times between switch commands
within each of the converter’s two legs. The delay-time modulation is implemented by connecting ADS
(pin 11) to CS, GND, or a resistive divider from CS through ADS to GND to set VADS as shown in Figure 4.
From equation (6) for VDEL, if ADS is tied to GND then VDEL rises in direct proportion to VCS, causing a
decrease in tDELAY as the load increases. In this condition, the maximum value of VDEL is 2 V.
If ADS is connected to a resistive divider between CS and GND, the term (VCS-- VADS) becomes smaller,
reducing the level of VDEL. This decreases the amount of delay modulation. In the limit of ADS tied to CS,
VDEL = 0.5 V and no delay modulation occurs. Figure 5 graphically shows the delay time vs. load for
varying adaptive delay set feature voltages (VADS).
In the case of maximum delay modulation (ADS=GND), when the circuit goes from light load to heavy
load, the variation of VDEL is from 0.5 V to 2 V. This causes the delay times to vary by a 4:1 ratio as the
load is changed.
The ability to program an adaptive delay is a desirable feature because the optimum delay time is a
function of the current flowing in the primary winding of the transformer, and can change by a factor of
10:1 or more as circuit loading changes. Reference[5] describes the many interrelated factors for choosing
the optimum delay times for the most efficient power conversion, and illustrates an external circuit to
enable adaptive delay set using the UC3879. Implementing this adaptive feature is simplified in the
UCC3895 controller, giving the user the ability to tailor the delay times to suit a particular application with a
minimum of external parts.
(5)
(6)
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
13
www.ti.com
APPLICATION INFORMATION
00.51.0
100
1.5 2.0 2.5
200
300
400
500
VCS -- Current Sense Voltage -- V
td -- Delay Time -- ns
DELAY TIME
vs
CURRENT SENSE VOLTAGE
A=V
ADS/VCS RDELAY =10kΩ
A=1.0
A=0.8
A=0.6
A=0.4
A=0.2
A=0.1
Figure 5. Delay Time Under Varying ADS Voltages
UDG--99138
CLOCK
RAMP
&
COMP
PWM
SIGNAL
OUTPUT A
OUTPUT B
OUTPUT C
OUTPUT D
Figure 6. UCC3895 Timing Diagram (No Output Delay Shown, COMP to RAMP offset not included)
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
14 www.ti.com
TYPICAL CHARACTERISTICS
0
200
0
10 20 30 40
400
800
600
1000
1200
1400
1800
1600
2000
Figure 7
VCS =0V
OUTPUT DELAY
vs
DELAY RESISTANCE
RDEL -- Delay Resistor -- kΩ
VCS =2V
tDELAY -- Output Delay -- ns
100 1000
200
0
600
400
800
1200
1000
1400
1600
OSCILLATOR FREQUENCY
vs
TIMING CAPACITANCE
RT= 100 kΩ
RT=82kΩ
RT=62kΩ
RT=47kΩ
Figure 8
CT-- Timing Capacitance -- pF
fSW -- Switching Frequency -- kHz
Figure 9
TA-- Temperature -- °C
E
A
OUTtoR
A
MP OFFSET
vs
TEMPERATURE
V
OFFSET -- E
A
OUTtoR
A
MP Offset --
V
-- 5 5
0.80
--15 125
0.85
0.90
0.95
1.00
-- 3 5 5 4 525 65 10585
Figure 10
1100 10 k 100 k
20
0
60
40
80
100
40
0
120
80
160
200
fOSC -- Oscillator Frequency -- kHz
A
MPLIFIER G
A
IN
A
ND PH
A
SE M
A
RGIN
vs
FREQUENCY
Gain -- dB
Phase Mar
g
in -- De
g
rees
GAIN
PHASE
MARGIN
10 1k 1MHz 10 MHz
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
15
www.ti.com
TYPICAL CHARACTERISTICS
Figure 11
0400 800 1200 1600
4
5
6
7
8
9
INPUT CURRENT
vs
OSCILLATOR FREQUENCY
IDD -- Operating Current -- mA
fOSC -- Oscillator Frequency -- kHz
NO OUTPUT LOADING
VDD =17V
VDD =15V
VDD =12V
VDD =10V
Figure 12
0400 800 1200 1600
4
5
6
7
8
9
10
11
12
13
IDD -- Operating Current -- mA
fOSC -- Oscillator Frequency -- kHz
INPUT CURRENT
vs
OSCILLATOR FREQUENCY
VDD =17V
VDD =15V
VDD =10V
VDD =12V
0.1-nF OUTPUT LOADS
REFERENCES
1. M. Dennis, A Comparison Between the BiCMOS UCC3895 Phase Shift Controller and the UC3875
Application Note (SLUA246).
2. L. Balogh, The Current--Doubler Rectifier: An Alternative Rectification Technique for Push--Pull and Bridge
Converters Application Note (SLUA121).
3. W. Andreycak, Phase Shifted, Zero Voltage Transition Design Considerations, Application Note
(SLUA107).
4. L. Balogh, The New UC3879 Phase Shifted PWM Controller Simplifies the Design of Zero Voltage
Transition Full--Bridge Converters, Application Note (SLUA122).
5. L. Balogh, Design Review: 100 W, 400 kHz, dc-to-dc Converter with Current Doubler Synchronous
Rectification Achieves 92% Efficiency, Unitrode Power Supply Design Seminar Manual, SEM--1100, 1996,
Topic 2.
6. UC3875 Phase Shift Resonant Controller, Datasheet, (SLUS229).
7. UC3879 Phase Shift Resonant Controller, Datasheet, (SLUS230).
8. UCC3895EVM--1, “Configuring the UCC3895 for direct Control Driven Synchronous Rectification, (Texas
Instrument’s Literature Number SLUU109A)
9. UCC3895, CD Output Asymetrical Duty Cycle Operation, (Texas Instrument’s Literature Number SLUA275)
10. Texas Instrument’s Literature Number SLUA323
11. Synchronous Rectifiers of a Current Doubler, (Texas Instrument’s Literature Number SLUA287)
UCC1895
UCC2895
UCC3895
SLUS157O -- DECEMBER 1999 -- REVISED APRIL 2010
16 www.ti.com
REVISION HISTORY
1. Page 6, changed REF pin description from “Do not use more than 1.0 μF of total capacitance on this pin.”
to “Do not use more than 4.7 μF of total capacitance on this pin.”
2. Page 2, added thermal information table.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
UCC1895J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
UCC1895L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
UCC2895DW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2895DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2895DWTR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2895DWTRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2895N ACTIVE PDIP N 20 20 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC2895NG4 ACTIVE PDIP N 20 20 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC2895PW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2895PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2895PWTR ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2895PWTRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2895Q ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
UCC2895QG3 ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
UCC3895DW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3895DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3895DWTR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3895DWTRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3895N ACTIVE PDIP N 20 20 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC3895NG4 ACTIVE PDIP N 20 20 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
UCC3895PW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3895PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3895PWTR ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3895PWTRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3895Q ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
UCC3895QG3 ACTIVE PLCC FN 20 46 Green (RoHS & CU SN Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 16-Oct-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC1895, UCC2895, UCC3895 :
•Automotive: UCC2895-Q1
•Enhanced Product: UCC2895-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 16-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC2895DWTR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
UCC2895PWTR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
UCC3895DWTR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
UCC3895PWTR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC2895DWTR SOIC DW 20 2000 367.0 367.0 45.0
UCC2895PWTR TSSOP PW 20 2000 367.0 367.0 38.0
UCC3895DWTR SOIC DW 20 2000 367.0 367.0 45.0
UCC3895PWTR TSSOP PW 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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