NC7WZ240L8X(Preliminary) - Fairchild Semiconductor

March 2001

Revised April 2003

NC7WZ240 TinyLogi c



UHS Dual Inverting Buffer with 3- STATE Outputs

NC7WZ240

TinyLogic UHS Dual Inverting Buffer

with 3-STATE Outputs

General Description

The NC7WZ240 is a Dual Inverting Buffer with indepen-

dent active LOW enables for the 3-STATE outputs. The

Ultra High Speed device is fabricated with advanced

CMOS technology to achieve superior switching perfor-

mance with high output drive while maintaining low static

power dissipation over a broad VCC operating range. The

device is spe cified to operate over the 1.6 5V to 5.5V VCC

operating range. The inputs and outputs are high imped-

ance when VCC is 0V. Inputs tolerate voltages up to 5.5V

indepen dent of VCC operat ing rang e. Outp uts tolera te vol t-

ages above VCC when in the 3-STATE condition.

Features

■Space saving US8 surface mount package

■MicroPak leadless package

■Ultra High Speed; tPD 2.3 ns typ into 50 pF at 5V VCC

■High Output Drive; ±24 mA at 3V VCC

■Broad VCC Operating Range: 1.65V to 5.5V

■Matches the performance of LCX when operated at

3.3V VCC

■Power down high impedance inputs/outputs

■Overvoltage tolerant inputs facilitate 5V to 3V translation

■Outputs are overvoltage tolerant in 3-STATE mode

■Patented noise/EMI reduction circuitry implemented

Ordering Code:

TinyLogic is a registered trad em ark of Fairc hild Semicond uc t or Corporation.

MicroPak is a trad em ark of Fairchild Sem icond uc t or Corporation.

Product Package Description Supplied AsOrder Package Code

Number Number Top Mark

NC7WZ240K8X MAB08A WZ40 8-Lead US8, JEDEC MO-187, V ariation CA 3.1mm Wide 3k Units on Tape and Reel

NC7WZ240L8X

(Preliminary) MAC08A U7 8-Lead MicroPak, 1.6 mm Wide 5k Units on Tape and Reel

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NC7WZ240

Logic Symbol

IEEE/IEC

Pin Descriptions

Function Table

H = HIGH Logi c Level

L = LOW Logic Level

Z = 3-STATE

Connection Diagrams

(Top View)

Pad Assignment for MicroPak

(Top Thru View)

Pin Names Description

OEnEnable Inputs for 3-STATE Outputs

AnInputs

Yn3-STATE Outputs

Inputs Output

OE AnYn

LLH

LHL

HLZ

HHZ

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NC7WZ240

Absolute Maxim um Ratings(Note 1) Recommended Operating

Conditions (Note 3)

Note 1: Abs olut e maxi mum ratin gs ar e DC value s beyond whi ch t he devi ce

may b e dam aged or h ave its usef ul li fe i mpa ired . Th e data she et sp ecif ica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading vari-

ables. Fairchild does not recommend operation outside datasheet specifi-

cations.

Note 2: The input and output negative voltage ratings may be exceeded if

the in put and outp ut diode current ratin gs are observe d.

Note 3: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Supply Voltage (VCC)−0.5V to +7.0V

DC Input Voltage (VIN) (Note 2) −0.5V to +7.0V

DC Output Voltage (VOUT)−0.5V to +7.0V

DC Input Diode Current (IIK)

@VIN < 0V −50 mA

DC Output Diode Current (IOK)

@VOUT < 0V −50 mA

DC Output Source/Sink Current (IOUT)± 50 mA

DC VCC/Ground Current (ICC/IGND)± 100 mA

Storage Temperature Range (TSTG)−65°C to +150°C

Junction Lead Temperature under Bias (TJ)+150°C

Junction Lead Temperature (TL)

(Soldering, 10 seconds) +260°C

Power Dissipation (PD) @ +85°C250 mW

Supply Voltage Operating (VCC) 1.65V to 5.5V

Supply Voltage Data Retention (VCC) 1.5V to 5.5V

Input Voltage (VIN) 0V to 5.5V

Output Voltage (VOUT)

Active State 0V to VCC

3-STATE 0V to 5.5V

Operating Temperature (TA)−40°C to +85°C

Input Rise and Fall Time (tr, tf)

VCC @ 1.8V, 0.15V, 2.5V ± 0.2V 0 ns/V to 20 ns/V

VCC @ 3.3V ± 0.3V 0 ns/V to 10 ns/V

VCC @ 5.0V ± 0.5V 0 ns/V to 5 ns/V

Thermal Resistance (θJA)250°C/W

Symbol Parameter VCC TA = +25°CT

A = −40°C to +85°CUnits Conditions

(V) Min Typ Max Min Max

VIH HIGH Level Input Voltage 1.65 to 1.95 0.75 VCC 0.75 VCC V

2.3 to 5.5 0.7 VCC 0.7 VCC

VIL LOW Level Input Voltage 1.65 to 1.95 0.25 VCC 0.25 VCC V

2.3 to 5.5 0.3 VCC 0.3 VCC

VOH HIGH Level Output Voltage 1.65 1.55 1.65 1.55

2.3 2.2 2.3 2.2 VIN = VIH IOH = −100 µA

3.0 2.9 3.0 2.9 or VIL

4.5 4.4 4.5 4.4

1.65 1.29 1.52 1.29

IOH = −4 mA

2.3 1.9 2.15 1.9 VIN = VIH IOH = −8 mA

3.0 2.4 2.80 2.4 or VIL IOH = −16 mA

3.0 2.3 3.68 2.3 IOH = −24 mA

4.5 3.8 4.20 3.8 IOH = −32 mA

VOL LOW Level Output Voltage 1.65 0.0 0.10 0.10

2.3 0.0 0.10 0.10 VIN = VIH IOL = 100 µA

3.0 0.0 0.10 0.10 or VIL

4.5 0.0 0.10 0.10

1.65 0.08 0.24 0.24

IOL = 4 mA

2.3 0.10 0.3 0.3 IOL = 8 mA

3.0 0.15 0.4 0.4 IOL = 16 mA

3.0 0.22 0.55 0.55 IOL = 24 mA

4.5 0.22 0.55 0.55 IOL = 32 mA

IIN Input Leakage Current 0 to 5.5 ±0.1 ±1µAV

IN = 5.5V, GND

IOZ 3-STATE Output Leakage 1.65 to 5.5 ±0.5 ±5µAV

IN = VIH or VIL

0 ≤ VOUT ≤ 5.5V

IOFF Power Off Leakage Current 0.0 1 10 µAV

IN or VOUT = 5.5V

ICC Quiescent Supply Current 1.65 to 5.5 1 10 µAV

IN = 5.5V, GND

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NC7WZ240

Noise Characteristics

Note 4: Parameter guaranteed by design.

AC Electrical Characteristics

Note 5: Parameter guaranteed by design. tOSLH = |tPLHmax − tPLHmin|; tOSHL = |tPHLmax − tPHLmin|.

Note 6: CPD is defined as the value of th e internal equivalent c apacita nc e which is deriv ed from dy namic operat ing current con su m pt ion (ICCD) at no output

loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to I CCD dynamic operating current by the expression:

ICCD = (CPD)(VCC)(fIN) + (ICCstatic).

Symbol Parameter VCC TA = + 25°CUnits Conditions

(V) Typ Max

VOLP (Note 4) Quiet Output Maximum Dynamic VOL 5.0 1.0 V CL = 50 pF

VOLV (Note 4) Quiet Output Minimum Dynamic VOL 5.0 1.0 V CL = 50 pF

VOHV (Note 4) Quiet Output Minimum Dynamic VOH 5.0 4.0 V CL = 50 pF

VIHD (Note 4) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50 pF

VILD (Note 4) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF

Symbol Parameter VCC TA = +25°CT

A = −40°C to +85°CUnits Conditions Figure

(V) Min Typ Max Min Max Number

tPLH, Propagation Delay 1.8 ± 0.15 2.0 12.0 2.0 13.0

CL = 15 pF

Figures

1, 3

tPHL An to Yn2.5 ± 0.2 1.0 7.5 1.0 8.0 RD = 1 MΩ

3.3 ± 0.3 0.8 5.2 0.8 5.5 S1= Open

5.0 ± 0.5 0.5 4.5 0.5 4.8

tPLH, Propagation Delay 3.3 ± 0.3 1.2 5.7 1.2 6.0 ns CL = 50 pF Figures

1, 3

tPHL An to Yn5.0 ± 0.5 0.8 5.0 0.8 5.3 RD = 500Ω

S1= Open

tOSLH, Output to Output Skew 3.3 ± 0.3 1.0 1.0 ns CL = 50 pF Figures

1, 3

tOSHL (Note 5) 5.0 ± 0.5 0.8 0.8 RD = 500Ω

S1= Open

tPZL, Output Enable Time 1.8 ± 0.15 3.0 14.0 3.0 15.0

CL = 50 pF

Figures

1, 3

tPZH 2.5 ± 0.2 1.8 8.5 1.8 9.0 RD, RU = 500 Ω

3.3 ± 0.3 1.2 6.2 1.2 6.5 S1 = GND for tPZH

5.5 ± 0.5 0.8 5.5 0.8 5.8 S1 = VI for tPZL

VI = 2 x VCC

tPLZ, Output Disable Time 1.8 ± 0.15 2.5 12.0 2.5 13.0

CL = 50 pF

Figures

1, 3

tPHZ 2.5 ± 0.2 1.5 8.0 1.5 8.5 RD, RU = 500 Ω

3.3 ± 0.3 0.8 5.7 0.8 6.0 S1 = GND for tPZH

5.0 ± 0.5 0.3 4.7 0.3 5.0 S1 = VI for tPZL

VI = 2 x VCC

CIN Input Capacitance 0 2.5 pF

COUT Output Capacitance 5.0 4

CPD Power Dissipation Capacitance 3.3 10 pF (Note 6) Figure 2

5.0 12

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NC7WZ240

AC Loading and Waveforms

CL include s l oad and str ay c apacitan ce

Input PRR = 1.0 MHz; t w = 500 ns

FIGURE 1. AC Test Circuit

Input = AC Wav efo r m; tr = tf = 1.8 ns ;

PRR = 10 MHz; Duty Cycle = 50 %

FIGURE 2. ICCD Test Circuit

FIGURE 3. AC Waveforms

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NC7WZ240

Tape and Reel Specification

Tape Format for US8

TAPE DIMENSIONS inches (millimeters)

Tape Format for MicroPak

TAPE DIMENSIONS inches (millimeters)

Package Tape Number Cavity Cover Tape

Designator Section Cavities Status Status

Leader (Start End) 125 (typ) Empty Sealed

K8X Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

Package Tape Number Cavity Cover Tape

Designator Section Cavities Status Status

Leader (Start End) 125 (typ) Empty Sealed

L8X Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

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NC7WZ240

Tape and Reel Specification (Continued)

REEL DIMENSIONS inches (millimeters)

Tape

Size ABCDN W1 W2 W3

8 mm 7.0 0.059 0.512 0.795 2.165 0.331 + 0.059/−0.000 0.567 W1 + 0.078/−0.039

(177.8) (1.50) (13.00) (20.20) (55.00) (8.40 + 1.50/−0.00) (14.40) (W1 + 2.00/−1.00)

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NC7WZ240

Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

Package Number MAB08A

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

9 www.fairchildsemi.com

NC7WZ240 TinyLogi c



UHS Dual Inverting Buffer with 3- STATE Outputs

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

8-Lead Micro Pa k, 1.6 mm Wide

Package Number MAC08A

(Preliminary)

Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circu it patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life sup por t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A c ritica l compo nent i n any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.