SLLS456B − NOVEMBER 2000 − REVISED APRIL 2005
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DDesigned for TIA/EIA-485, TIA/EIA-422, and
ISO 8482 Applications
DSignaling Rate† Exceeding 50 Mbps
DFail-Safe in Bus Short-Circuit, Open-Circuit,
and Idle-Bus Conditions
DESD Protection on Bus Inputs
Exceeds 6 kV
DCommon-Mode Bus Input Range
–7 V to 12 V
DPropagation Delay Times <16 ns
DLow Standby Power Consumption <20 µA
DPin-Compatible Upgrade for AM26LS32,
DS96F173, LTC488, and SN75173
description
The SN65LBC173A and SN75LBC173A are
quadruple differential line receivers with 3-state
outputs, designed for TIA/EIA-485 (RS-485),
TIA/EIA-422 (RS-422), and ISO 8482 (Euro
RS-485) applications.
These devices are optimized for balanced
multipoint bus communication at data rates up to
and exceeding 50 million bits per second. The
transmission media may be twisted-pair cables,
printed-circuit board traces, or backplanes. The
ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of
the media and the noise coupling to the
environment.
Each receiver operates over a wide range of positive and negative common-mode input voltages, and features
ESD protection to 6 kV, making it suitable for high-speed multipoint data transmission applications in harsh
environments. These devices are designed using LinBiCMOSt, facilitating low power consumption and
robustness.
The G and G inputs provide enable control logic for either positive- or negative-logic enabling all four drivers.
When disabled or powered off, the receiver inputs present a high-impedance to the bus for reduced system
loading.
The SN75LBC173A is characterized for operation over the temperature range of 0°C to 70°C. The
SN65LBC173A is characterized over the temperature range from −40°C to 85°C.
Copyright 2001, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments.
†The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
logic diagram
G
G
1A
1B 1Y
2A
2B 2Y
3A
3B 3Y
4A
4B 4Y
SN65LBC173A (Marked as 65LBC173A)
SN75LBC173A (Marked as 75LBC173A)
D or N PACKAGE
(TOP VIEW)
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2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each receiver)
DIFFERENTIAL INPUTS
ENABLES
OUTPUT
DIFFERENTIAL INPUTS
A – B (VID)G G
OUTPUT
Y
VID ≤ −0.2 V
H X
L
VID ≤ −0.2 V X L L
−0.2 V < VID < −0.01 V
H X
?
−0.2 V < VID < −0.01 V X L ?
−0.01 V ≤ VID
H X
H
−0.01 V ≤ VID X L H
X
L H
Z
XOPEN OPEN Z
Short circuit
H X
H
Short circuit X L H
Open circuit H X H
H = high level, L = low level, X = irrelevant, Z = high impedance (off),
? = indeterminate
AVAILABLE OPTIONS
PACKAGE
TAPLASTIC
SMALL OUTLINE†
(JEDEC MS-012)
PLASTIC
DUAL-IN-LINE
(JEDEC MS-001)
0°C to 70°C SN75LBC173AD SN75LBC173AN
−40°C to 85°C SN65LBC173AD SN65LBC173AN
†Add an R suffix for taped and reeled
equivalent input and output schematic diagrams
16 V
16 V
100 kΩ
18 kΩ
4 kΩ
4 kΩ
Input
A Input
VCC
16 V
16 V
100 kΩ
18 kΩ
4 kΩ
4 kΩ
Input
B Input
VCC
1 kΩ
8 V 100 kΩ
VCC
Input 1 kΩ
8 V
100 kΩ
VCC
Input
G Input
8 V
G Input
VCC
5 Ω
8 V 8 V
Y Output
Outpu
t
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) −0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any bus input (DC) −10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any bus input (transient pulse through 100 Ω, see Figure 5) −30 V to 30 V. . . . . . . . . . . . . .
Voltage input range at G and G, VI −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver output current, IO ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge:
Human body model (see Note 2): A and B to GND 6 kV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All pins 5 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged-device model (see Note 3): All pins 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation See Power Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to GND, and are steady-state (unless otherwise specified).
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR‡
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
D1080 mW 8.7 mW/°C690 mW 560 mW
N1150 mW 9.2 mW/°C736 mW 598 mW
‡This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air
flow.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Voltage at any bus terminal A, B −7 12 V
High-level input voltage, VIH
G, G
2 VCC
V
Low-level input voltage, VIL G, G 0 0.8 V
Output current Y −8 8 mA
Operating free-air temperature, TA
SN75LBC173A 0 70
°C
Operating free-air temperature, TASN65LBC173A −40 85 °C
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4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIT+ Positive-going differential input voltage threshold
−7 V ≤ VCM ≤12 V (VCM = (VA + VB )/2)
−80 −10
mV
VIT− Negative-going differential input voltage threshold −7 V ≤ VCM ≤12 V (VCM = (VA + VB )/2) −200 −120 mV
VHYS Hysteresis voltage (VIT+ − VIT−) 40 mV
VIK Input clamp voltage II = −18 mA −1.5 −0.8 V
VOH High-level output voltage VID = 200 mV,
IOH = −8 m A
See Figure 1
2.7 4.8
V
VOL Low-level output voltage VID = −20 0 m V,
IOL = 8 mA
See Figure 1 0.2 0.4 V
IOZ High-impedance-state output current VO = 0 V to VCC −1 1 µA
II
Line input current
Other input at 0 V,
VI = 12 V 0.9
mA
IILine input current
Other input at 0 V,
VCC = 0 V or 5 V VI = −7 V −0.7 mA
IIH High-level input current
Enable inputs G, G
100 µA
IIL Low-level input current Enable inputs G, G −100 µA
RIInput resistance A, B inputs 12 kΩ
ICC
Supply current
VID = 5 V G at 0 V, G at VCC 20 µA
ICC Supply current No load G at VCC, G at 0 V 11 16 mA
†All typical values are at VCC = 5 V and 25°C.
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
trOutput rise time 2 4 ns
tfOutput fall time
VID = −3 V to 3 V, See Figure 2
2 4 ns
tPLH Propagation delay time, low-to-high level output VID = −3 V to 3 V, See Figure 2 9 12 16 ns
tPHL Propagation delay time, high-to-low level output 9 12 16 ns
tPZH Propagation delay time, high-impedance to high-level output
See Figure 3
27 38 ns
tPHZ Propagation delay time, high-level to high-impedance output See Figure 3 7 16 ns
tPZL Propagation delay time, high-impedance to low level output
See Figure 4
29 38 ns
tPLZ Propagation delay time, low-level to high-impedance output See Figure 4 12 16 ns
tsk(p) Pulse skew (| (tPLH – tPHL) |) 0.2 1 ns
tsk(o) Output skew (see Note 4) 2 ns
tsk(pp) Part-to-part skew (see Note 5) 2 ns
†All typical values are at VCC = 5 V and 25°C.
NOTES: 4. Outputs skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs
connected together.
5. Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two
devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have
identical packages and test circuits.
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PARAMETER MEASUREMENT INFORMATION
VID
VO
IO
VA
VB
Figure 1. Voltage and Current Definitions
A
B
Generator 50 Ω
Generator 50 Ω
Y
CL = 15 pF
(Includes Probe and
Jig Capacitance)
Generators: PRR = 1 MHz, 50% Duty Cycle,
tr <6 ns, Zo = 50 Ω
90% 90%
1.5 V
1.5 V 3 V
0 V
tPLH tPHL
VOH
VOL
trtf
Input B
Input A
Output Y 10% 10%
1.5 V
Figure 2. Switching Test Circuit and Waveforms
A
B
Generator 50 Ω
Y
1.5 V1.5 V 3 V
0 V
tPZH tPHZ VOH
GND
G
YVOH −0.5 V
1.5 V
1.5 V
GG
VCC
1 kΩ
VCC
Generators: PRR = 1 MHz, 50% Duty Cycle,
tr <6 ns, Zo = 50 Ω
CL = 15 pF
(Includes Probe and
Jig Capacitance)
Figure 3. Test Circuit Waveforms, tPZH and tPHZ
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PARAMETER MEASUREMENT INFORMATION
A
B
Generator 50 Ω
Y
1.5 V1.5 V 3 V
0 V
tPZL tPLZ
VOL
VCC
G
YVOL + 0.5 V
1.5 V
−1.5 V
GG
VCC
1 kΩ
VCC
Generators: PRR = 1 MHz, 50% Duty Cycle,
tr <6 ns, Zo = 50 Ω
CL = 15 pF
(Includes Probe and
Jig Capacitance)
Figure 4. Test Circuit Waveforms, tPZL and tPLZ
Pulse Generator,
15 µs Duration,
1% Duty Cycle
100 Ω VTEST
0 V
15 µs1.5 ms VTEST
Figure 5. Test Circuit and Waveform, Transient Over-Voltage Test
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TYPICAL CHARACTERISTICS
Figure 6
−600
−400
−200
0
200
400
600
800
−10 −5 0 5 10 15
VCC = 0 V
VCC = 5 V
Bus Input Current −
Bus Input Voltage − V
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
Aµ
Figure 7
0
1
2
3
4
5
6
−150 −100 −50 0 50
VIC = −7 V
VIC = 0 V
VIC = 12 V
VIC = −7 V
VIC = 0 V
VIC = 12 V
VCC = 5 V
TA = 25°C
− Output Voltage − V
Differential Input Voltage − mV
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
VO
Figure 8
0
10
20
30
40
50
60
1 10 100
VCC = 5 V, No Load
VCC = 4.75 V, CL = 15 pF
VCC = 5 V, CL = 15 pF
VCC = 5.25 V, CL = 15 pF
− Supply Current − mA
Signaling Rate (All Four Channels) − Mbps
SUPPLY CURRENT
vs
SIGNALING RATE (ALL FOUR CHANNELS)
ICC
Figure 9
11
11.5
12
12.5
13
13.5
−40 −20 0 20 40 60 80
tPHL
tPLH
Propagation Delay Time − ns
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
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8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
A, B
500 mV
5 V
−500 mV
0 V
20 ns
Y
Figure 10. Receiver Inputs and Outputs, 50 Mbps Signaling Rate
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APPLICATION INFORMATION
TMS320F243
DSP
(Controller)
SPISIMO
SN65LBC174A SN65LBC173A TMS320F241
DSP
(Embedded
Application)
SPISIMO
IOPA1
SPISTE SPISTE
IOPA0
(Handshake
/Status)
SPICLK
IOPA0
IOPA1
(Enable)
SPICLK
SPISOMI SPISOMI
IOPA2
IOPA2
(Enable)
Figure 11. Typical Application Circuit, DSP-to-DSP Link via Serial Peripheral Interface
Servo
Drive SN65LBC173A
Encoder Phase A
Status Bit
Encoder Phase B
Encoder Index
Motion Controller
Figure 12. Typical Application Circuit, High-Speed Servomotor Encoder Interface
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
SN65LBC173AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 65LBC173A
SN65LBC173ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 65LBC173A
SN65LBC173ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 65LBC173A
SN65LBC173ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 65LBC173A
SN65LBC173AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 65LBC173A
SN65LBC173ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 65LBC173A
SN75LBC173AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 75LBC173A
SN75LBC173ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 75LBC173A
SN75LBC173ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 75LBC173A
SN75LBC173ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 75LBC173A
SN75LBC173AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 75LBC173A
SN75LBC173ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 75LBC173A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LBC173ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN75LBC173ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LBC173ADR SOIC D 16 2500 333.2 345.9 28.6
SN75LBC173ADR SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
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