ICM7555, ICM7556 S E M I C O N D U C T O R General Purpose Timers November 1996 Features Description * Exact Equivalent in Most Cases for SE/NE555/556 or TLC555/556 The ICM7555 and ICM7556 are CMOS RC timers providing significantly improved performance over the standard SE/NE555/6 and 355 timers, while at the same time being direct replacements for those devices in most applications. Improved parameters include low supply current, wide operating supply voltage range, low THRESHOLD, TRIGGER and RESET currents, no crowbarring of the supply current during output transitions, higher frequency performance and no requirement to decouple CONTROL VOLTAGE for stable operation. * Low Supply Current - ICM7555. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60A - ICM7556. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120A * Extremely Low Input Currents . . . . . . . . . . . . . . . 20pA * High Speed Operation . . . . . . . . . . . . . . . . . . . . . . 1MHz * Guaranteed Supply Voltage Range . . . . . . . 2V to 18V * Temperature Stability . . . . . . . . . . . . 0.005%/oC at 25oC * Normal Reset Function - No Crowbarring of Supply During Output Transition * Can be Used with Higher Impedance Timing Elements than Regular 555/6 for Longer RC Time Constants * Timing from Microseconds through Hours * Operates in Both Astable and Monostable Modes * Adjustable Duty Cycle * High Output Source/Sink Driver can Drive TTL/CMOS Specifically, the ICM7555 and ICM7556 are stable controllers capable of producing accurate time delays or frequencies. The ICM7556 is a dual ICM7555, with the two timers operating independently of each other, sharing only V+ and GND. In the one shot mode, the pulse width of each circuit is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled by two external resistors and one capacitor. Unlike the regular bipolar 555/6 devices, the CONTROL VOLTAGE terminal need not be decoupled with a capacitor. The circuits are triggered and reset on falling (negative) waveforms, and the output inverter can source or sink currents large enough to drive TTL loads, or provide minimal offsets to drive CMOS loads. Ordering Information * Outputs have Very Low Offsets, HI and LO PART NUMBER (BRAND) Applications * Precision Timing * Pulse Generation * Sequential Timing * Time Delay Generation * Pulse Width Modulation TEMP. RANGE (oC) PKG. NO. PACKAGE ICM7555CBA (7555CBA) 0 to 70 8 Ld SOIC M18.5 ICM7555IBA (7555IBA) -25 to 85 8 Ld SOIC M18.5 ICM7555IPA -25 to 85 8 Ld PDIP E8.3 ICM7555ITV -25 to 85 8 Pin Metal Can T8.C ICM7555MTV (Note) -55 to 125 8 Pin Metal Can T8.C * Pulse Position Modulation ICM7556IPD -25 to 85 14 Ld PDIP * Missing Pulse Detector ICM7556MJD (Note) -55 to 125 14 Ld CERDIP F14.3 E14.3 NOTE: Add /883B to part number if 883B processing is desired. Pinouts ICM7555 (PDIP, SOIC) TOP VIEW ICM7555 (METAL CAN) TOP VIEW VDD AND CASE DISCHARGE 1 8 GND 1 8 VDD TRIGGER 2 7 DISCHARGE OUTPUT 3 6 THRESHOLD GND 1 7 DISCHARGE TRIGGER 2 RESET 4 5 CONTROL VOLTAGE 6 THRESHOLD OUTPUT 3 4 ICM7556 (PDIP, CERDIP) TOP VIEW 5 CONTROL VOLTAGE THRESH- 2 OLD CONTROL 3 VOLTAGE RESET 4 OUTPUT 5 TRIGGER 6 RESET CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1996 8-170 GND 7 14 VDD 13 DISCHARGE 12 THRESHOLD 11 CONTROL VOLTAGE 10 RESET 9 OUTPUT 8 TRIGGER File Number 2867.2 ICM7555, ICM7556 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18V Input Voltage Trigger, Control Voltage, Threshold, Reset (Note 1). . . . . . . . . . . . . . . . . . . . . .V+ +0.3V to GND -0.3V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 80 24 Metal Can Package . . . . . . . . . . . . . . . 165 80 14 Lead PDIP Package . . . . . . . . . . . . 115 N/A 8 Lead PDIP Package . . . . . . . . . . . . . 110 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 170 N/A Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range ICM7555C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC ICM7555I, ICM7556I. . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC ICM7555M, ICM7556M. . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than V+ +0.3V or less than V- -0.3V may cause destructive latchup. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple supply systems, the supply of the ICM7555/6 must be turned on first. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Applies to ICM7555 and ICM7556, Unless Otherwise Specified (NOTE 4) -55oC TO 125oC TA = 25oC PARAMETER Static Supply Current SYMBOL IDD TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS - 40 200 - - 300 A - 60 300 - - 300 A - 80 400 - - 600 A VDD = 15V - 120 600 - - 600 A RA = 10K, C = 0.1F, VDD = 5V - 2 - - - - % - - - 858 - 1161 s VDD = 5V - - - - 150 - ppm/oC VDD = 10V - - - - 200 - ppm/oC VDD = 15V - - - - 250 - ppm/oC VDD = 5V to 15V - 0.5 - - 0.5 - %/V RA = RB = 10K, C = 0.1F, VDD = 5V - 2 - - - - % - - - 1717 - 2323 s VDD = 5V - - - - 150 - ppm/oC VDD = 10V - - - - 200 - ppm/oC VDD = 15V - - - - 250 - ppm/oC VDD = 5V to 15V - 0.5 - - 0.5 - %/V ICM7555 VDD = 5V VDD = 15V ICM7556 VDD = 5V Monostable Timing Accuracy Drift with Temperature (Note 3) Drift with Supply (Note 3) Astable Timing Accuracy Drift with Temperature (Note 3) Drift with Supply (Note 3) Threshold Voltage VTH VDD = 15V 62 67 71 61 - 72 % VDD Trigger Voltage VTRIG VDD = 15V 28 32 36 27 - 37 % VDD Trigger Current ITRIG VDD = 15V - - 10 - - 50 nA Threshold Current ITH VDD = 15V - - 10 - - 50 nA Control Voltage VCV VDD = 15V 62 67 71 61 - 72 % VDD Reset Voltage VRST VDD = 2V to 15V 0.4 - 1.0 0.2 - 1.2 V Reset Current IRST VDD = 15V - - 10 - - 50 nA 8-171 ICM7555, ICM7556 Electrical Specifications Applies to ICM7555 and ICM7556, Unless Otherwise Specified (NOTE 4) -55oC TO 125oC TA = 25oC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Discharge Leakage IDIS VDD = 15V - - 10 - - 50 nA Output Voltage VOL VDD = 15V, ISINK = 20mA - 0.4 1.0 - - 1.25 V VDD = 5V, ISINK = 3.2mA - 0.2 0.4 - - 0.5 V VDD = 15V, ISOURCE = 0.8mA 14.3 14.6 - 14.2 - - V VDD = 5V, ISOURCE = 0.8mA 4.0 4.3 - 3.8 - - V VDD = 5V, ISINK = 15mA - 0.2 0.4 - - 0.6 V VDD = 15V, ISINK = 15mA - - - - - 0.4 V 2.0 - 18.0 3.0 - 16.0 V VOH Discharge Output Voltage VDIS Supply Voltage (Note 3) VDD Functional Operation Output Rise Time (Note 3) tR RL = 10M, CL = 10pF, VDD = 5V - 75 - - - - ns Output Fall Time (Note 3) tF RL = 10M, CL = 10pF, VDD = 5V - 75 - - - - ns VDD = 5V, RA = 470, RB = 270, C = 200pF - 1 - - - - MHz Oscillator Frequency (Note 3) fMAX NOTES: 3. These parameters are based upon characterization data and are not tested. 4. Applies only to military temperature range product (M suffix). Functional Diagram VDD 4 8 R THRESHOLD 6 5 CONTROL VOLTAGE FLIP-FLOP RESET OUTPUT DRIVERS COMPARATOR A + OUTPUT - 3 7 R DISCHARGE n + TRIGGER 2 1 COMPARATOR B 1 GND R NOTE: This functional diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs. R = 100k, 20% (Typ) TRUTH TABLE THRESHOLD VOLTAGE TRIGGER VOLTAGE RESET OUTPUT DISCHARGE SWITCH Don't Care Don't Care Low Low On >2/3(V+) >1/3(V+) High Low On <2/3(V+) >1/3(V+) High Stable Stable Don't Care <1/3(V+) High High Off NOTE: RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD. 8-172 ICM7555, ICM7556 Schematic Diagram VDD P P P P R THRESHOLD N N CONTROL VOLTAGE NPN R OUTPUT P P TRIGGER R N N N N N RESET N N GND DISCHARGE R = 100k 20% (TYP) Application Information General 500 TA = 25oC SUPPLY CURRENT (mA) The ICM7555/6 devices are, in most instances, direct replacements for the NE/SE 555/6 devices. However, it is possible to effect economies in the external component count using the ICM7555/6. Because the bipolar 555/6 devices produce large crowbar currents in the output driver, it is necessary to decouple the power supply lines with a good capacitor close to the device. The 7555/6 devices produce no such transients. See Figure 1. The ICM7555/6 produces supply current spikes of only 2mA - 3mA instead of 300mA - 400mA and supply decoupling is normally not necessary. Also, in most instances, the CONTROL VOLTAGE decoupling capacitors are not required since the input impedance of the CMOS comparators on chip are very high. Thus, for many applications 2 capacitors can be saved using an ICM7555, and 3 capacitors with an ICM7556. 8-173 400 300 SE/NE555 200 100 0 ICM7555/56 0 200 400 TIME (ns) 600 800 FIGURE 1. SUPPLY CURRENT TRANSIENT COMPARED WITH A STANDARD BIPOLAR 555 DURING AN OUTPUT TRANSITION ICM7555, ICM7556 Power Supply Considerations Monostable Operation Although the supply current consumed by the ICM7555/6 devices is very low, the total system supply current can be high unless the timing components are high impedance. Therefore, use high values for R and low values for C in Figures 2 and 3. In this mode of operation, the timer functions as a one-shot, see Figure 3. Initially the external capacitor (C) is held discharged by a transistor inside the timer. Upon application of a negative TRIGGER pulse to pin 2, the internal flip-flop is set which releases the short circuit across the external capacitor and drives the OUTPUT high. The voltage across the capacitor now increases exponentially with a time constant t = RAC. When the voltage across the capacitor equals 2/ V+, the comparator resets the flip-flop, which in turn dis3 charges the capacitor rapidly and also drives the OUTPUT to its low state. TRIGGER must return to a high state before the OUTPUT can return to a low state. Output Drive Capability The output driver consists of a CMOS inverter capable of driving most logic families including CMOS and TTL. As such, if driving CMOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of 4.5V or more the ICM7555/6 will drive at least 2 standard TTL loads. tOUTPUT = -ln Astable Operation 1 8 TRIGGER 2 7 OUTPUT 3 6 RESET 4 5 ICM7555 f = 1.44 ( R A + 2R B ) C CONTROL VOLTAGE D = ( R A + R B ) ( R A + 2R B ) VDD VDD 10K 8 TRIGGER 2 7 3 6 4 5 OUTPUT DISCHARGE THRESHOLD ALTERNATE OUTPUT CONTROL VOLTAGE RESET R OPTIONAL CAPACITOR C FIGURE 2A. ASTABLE OPERATION VDD 1 8 2 7 OUTPUT 3 6 VDD 4 5 C FIGURE 3. MONOSTABLE OPERATION Control Voltage The duty cycle is controlled by the values of RA and RB, by the equation: C THRESHOLD VDD 18V The timer can also be connected as shown in Figure 2B. In this circuit, the frequency is: VDD DISCHARGE OPTIONAL CAPACITOR 1 f = -----------------1.4 RC 1 VDD RA The circuit can be connected to trigger itself and free run as a multivibrator, see Figure 2A. The output swings from rail to rail, and is a true 50% duty cycle square wave. (Trip points and output swings are symmetrical). Less than a 1% frequency variation is observed, over a voltage range of +5V to +15V. GND (1/3) RAC = 1.1RAC The CONTROL VOLTAGE terminal permits the two trip voltages for the THRESHOLD and TRIGGER internal comparators to be controlled. This provides the possibility of oscillation frequency modulation in the astable mode or even inhibition of oscillation, depending on the applied voltage. In the monostable mode, delay times can be changed by varying the applied voltage to the CONTROL VOLTAGE pin. RESET The RESET terminal is designed to have essentially the same trip voltage as the standard bipolar 555/6, i.e., 0.6V to 0.7V. At all supply voltages it represents an extremely high input impedance. The mode of operation of the RESET function is, however, much improved over the standard bipolar 555/6 in that it controls only the internal flip-flop, which in turn controls simultaneously the state of the OUTPUT and DISCHARGE pins. This avoids the multiple threshold problems sometimes encountered with slow falling edges in the bipolar devices. RA RB OPTIONAL CAPACITOR FIGURE 2B. ALTERNATE ASTABLE CONFIGURATION 8-174 ICM7555, ICM7556 1200 MINIMUM PULSE WIDTH (ns) SUPPLY CURRENT (ICM7555) (A) TA = 25oC 1100 1000 900 800 700 600 500 VDD = 2V 400 300 200 VDD = 5V 100 VDD = 18V 0 200 400 180 360 160 320 280 140 TA = -20oC 120 100 160 TA = 70oC 60 10 20 30 80 20 40 0 0 40 2 4 10 12 14 16 18 20 100 TA = 25oC TA = -20oC OUTPUT SINK CURRENT (mA) OUTPUT SOURCE CURRENT (mA) 8 FIGURE 5. SUPPLY CURRENT vs SUPPLY VOLTAGE -0.1 VDD = 2V -1.0 VDD = 5V -10.0 VDD = 18V -1.0 -0.1 OUTPUT VOLTAGE REFERENCED TO VDD (V) 10.0 VDD = 18V VDD = 5V VDD = 2V 1.0 0.1 0.01 -0.01 0.1 1.0 10.0 OUTPUT LOW VOLTAGE (V) FIGURE 6. OUTPUT SOURCE CURRENT vs OUTPUT VOLTAGE FIGURE 7. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE 100 100 TA =70oC OUTPUT SINK CURRENT (mA) TA = 25oC OUTPUT SINK CURRENT (mA) 6 SUPPLY VOLTAGE (V) FIGURE 4. MINIMUM PULSE WIDTH REQUIRED FOR TRIGGERING VDD = 18V VDD = 5V VDD = 2V 1.0 0.1 0.01 120 40 LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (%VDD) 10.0 200 TA = 25oC 80 0 0 -100 -10 240 SUPPLY CURRENT (ICM7556) (A) Typical Performance Curves 0.1 1.0 OUTPUT LOW VOLTAGE (V) 10.0 VDD = 18V 10.0 VDD = 5V VDD = 2V 1.0 0.1 0.01 0.1 1.0 10.0 OUTPUT LOW VOLTAGE (V) FIGURE 8. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE FIGURE 9. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE 8-175 ICM7555, ICM7556 (Continued) 100 8 TA = 25oC DISCHARGE SINK CURRENT (mA) NORMALIZED FREQUENCY DEVIATION (%) Typical Performance Curves 6 4 2 RA = RB = 10M C = 100pF 0 2 RA = RB = 10k C = 0.1F 4 6 8 0.1 1.0 10.0 TA = 25oC 10.0 VDD = 2V 1.0 0.1 0.01 100.0 0.1 1.0 DISCHARGE LOW VOLTAGE (V) SUPPLY VOLTAGE (V) 600 PROPAGATION DELAY (ns) VDD = 5V 500 400 300 TA = 70oC 200 TA = 25oC TA = -20oC 100 0 0 10 20 30 40 +1.0 RA = RB = 10k C = 0.1F +0.9 +0.8 +0.7 +0.6 VDD = 5V +0.5 +0.4 +0.3 +0.2 +0.1 0 -0.1 0 -20 20 60 80 FIGURE 13. NORMALIZED FREQUENCY STABILITY IN THE ASTABLE MODE vs TEMPERATURE 1.0 1.0 TA = 25oC 100m TA = 25oC RA 10m 10m 1k 10k 100k 1M 10M 100M (RA + 2RB) 1m 100 10 1 100n CAPACITANCE (F) CAPACITANCE (F) 40 TEMPERATURE (oC) FIGURE 12. PROPAGATION DELAY vs VOLTAGE LEVEL OF TRIGGER PULSE 10n 1m 100 10 1 100n 1k 10k 100k 1M 10M 100M 10n 1n 1n 100p 100p 10p 1p 0.1 VDD = 18V VDD = 2V LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (%VDD) 100m 10.0 FIGURE 11. DISCHARGE OUTPUT CURRENT vs DISCHARGE OUTPUT VOLTAGE NORMALIZED FREQUENCY DEVIATION (%) FIGURE 10. NORMALIZED FREQUENCY STABILITY IN THE ASTABLE MODE vs SUPPLY VOLTAGE VDD = 5V VDD = 18V 10p 1 10 100 1K 10K 100K 1M 1p 100n 10M FREQUENCY (Hz) FIGURE 14. FREE RUNNING FREQUENCY vs RA, RB AND C 1 10 100 1m 10m 100m 1 TIME DELAY (s) FIGURE 15. TIME DELAY IN THE MONOSTABLE MODE vs RA AND C 8-176 10