CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1993 8-21
SEMICONDUCTOR
AD7541
12-Bit Multiplying D/A Converter
Description
The AD7541 is a monolithic, low cost, high performance, 12-
bit accurate, multiplying digital-to-analog converter (DAC).
Harris’ wafer level laser-trimmed thin-film resistors on CMOS
circuitry provide true 12-bit linearity with TTL/CMOS compat-
ible operation.
Special tabbed-resistor geometries (improving time stability),
full input protection from damage due to static discharge by
diode clamps to V+ and ground, large IOUT1 and IOUT2 bus
lines (improving superposition errors) are some of the fea-
tures offered by Harris AD7541.
Pin compatible with AD7521, this DAC provides accurate
four quadrant multiplication over the full military temperature
range.
Features
• 12-Bit Linearity 0.01%
• Pretrimmed Gain
• Low Gain and Linearity Tempcos
• Full Temperature Range Operation
• Full Input Static Protection
• TTL/CMOS Compatible
• +5V to +15V Supply Range
• 20mW Low Power Dissipation
• Current Settling Time 1µs to 0.01% of FSR
• Four Quadrant Multiplication
File Number 3107
December 1993
Ordering Information
PART NUMBER NONLINEARITY TEMPERATURE RANGE PACKAGE
AD7541AD 0.02% (11-Bit) -25oC to +85oC 18 Lead Plastic DIP
AD7541BD 0.01% (12-Bit) -25oC to +85oC 18 Lead Plastic DIP
AD7541JN 0.02% (11-Bit) 0oC to +70oC 18 Lead Plastic DIP
AD7541KN 0.01% (12-Bit) 0oC to +70oC 18 Lead Plastic DIP
AD7541LN 0.01% (12-Bit) Guaranteed Monotonic 0oC to +70oC 18 Lead Plastic DIP
AD7541SD 0.02% (11-Bit) -55oC to +125oC 18 Lead Plastic DIP
AD7541TD 0.01% (12-Bit) -55oC to +125oC 18 Lead Plastic DIP
Pinout
AD7541
(PDIP)
TOP VIEW
Functional Diagram
Switches shown are for Digital Inputs “High”
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1RFEEDBACK
V+
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 8
VREF IN
BIT 7
IOUT1
IOUT2
GND
BIT 1 (MSB)
BIT 2
BIT 3
BIT 5
BIT 4
BIT 6
MSB
(4)
20kΩ
(3)
BIT 3BIT 2
VREF IN
20kΩ20kΩ20kΩ20kΩ20kΩ
10kΩ10kΩ10kΩ10kΩ
SPDT
NMOS
10kΩ
IOUT2 (2)
IOUT1 (1)
RFEEDBACK
(17)
SWITCHES
(18)
(5) (6)
8-22
Specifications AD7541
Absolute Maximum Ratings Thermal Information
Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . .V+ to GND
Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
Thermal Resistance θJA
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .90oC/W
Operating Temperature
JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
AD, BD Versions . . . . . . . . . . . . . . . . . . . . . . . . . .-25oC to +85oC
SD, TD Version . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
Maximum Power Dissipation
Plastic DIP Package up to +70oC . . . . . . . . . . . . . . . . . . . 670mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = +25oC, Unless Otherwise Specified
PARAMETER TEST CONDITIONS
TA +25oCT
A
MIN-MAX
UNITSMIN TYP MAX MIN MAX
SYSTEM PERFORMANCE
Resolution 12 - - 12 - Bits
Nonlinearity A, S, J -10V ≤ VREF ≤ +10V
VOUT1 = VOUT2 = 0V
See Figure 3
(Note 4)
--±0.024 - ±0.024 % of FSR
B, T, K - - ±0.012 - ±0.012 % of FSR
L--±0.012 - ±0.012 % of FSR
Monotonicity Guaranteed
Gain Error -10V ≤ VREF ≤ +10V (Note 4) - - ±0.3 - ±0.4 % of FSR
Output Leakage Current
(Either Output) VOUT1 = VOUT2 = 0 - - ±50 - ±200 nA
DYNAMIC CHARACTERISTICS
Power Supply Rejection V+ = 14.5V to 15.5V
See Figure 5, (Note 4) --±0.005 - ±0.01 % of FSR/% of
∆V+
Output Current Settling Time To 0.1% of FSR
See Figure 9, (Note 5) --1-1 µs
Feedthrough Error VREF = 20VPP, 10kHz
All Digital Inputs Low
See Figure 8, (Note 5)
--1-1mV
P-P
REFERENCE INPUTS
Input Resistance All Digital Inputs High
IOUT1 at Ground 5 10 20 5 20 kΩ
ANALOG OUTPUT
Voltage Compliance Both Outputs, See Maximum
Ratings (Note 6) -100mV to V+
Output Capacitance COUT1 All Digital Inputs High
See Figure 7, (Note 5) - - 200 - 200 pF
COUT2 - - 60 - 60 pF
COUT1 All Digital Inputs Low)
See Figure 7, (Note 5) - - 60 - 60 pF
COUT2 - - 200 - 200 pF
Output Noise (Both Outputs) See Figure 6 Equivalent to 10kΩ Johnson Noise
DIGITAL INPUTS
Low State Threshold, VIL (Note 1, 5) - - 0.8 - 0.8 V
High State Threshold, VIH 2.4 - - 2.4 - V
8-23
Specifications AD7541
Input Current VIN = 0V or V+ (Note 5) - - ±1-±1µA
Input Coding See Tables 1 & 2 (Note 5) Binary/Offset Binary
Input Capacitance (Note 5) - - 8 - 8 pF
POWER SUPPLY CHARACTERISTICS
Power Supply Voltage Range Accuracy is not guaranteed over
this range +5 to +16 V
I+ All Digital Inputs High or Low
(Excluding Ladder Network) - - 2.0 - 2.5 mA
Total Power Dissipation (Including Ladder Network) - 20 - - - mW
NOTES:
1. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electro-
static fields. Keep unused units in conductive foam at all times.
2. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK.
3. Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes.
4. Using internal feedback resistor, RFEEDBACK.
5. Guaranteed by design or characterization and not production tested.
6. Accuracy not guaranteed unless outputs at ground potential.
Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = +25oC, Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
TA +25oCT
A
MIN-MAX
UNITSMIN TYP MAX MIN MAX
Definition of Terms
Nonlinearity: Error contributed by deviation of the DAC
transfer function from a “best fit straight line” function. Nor-
mally expressed as a percentage of full scale range. For a
multiplying DAC, this should hold true over the entire VREF
range.
Resolution: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of LSB = (VREF)/2-N. A
bipolar converter of n bits has a resolution of LSB = (VREF)/
2-(N-1). Resolution in no way implies linearity.
Settling Time: Time required for the output function of the
DAC to settle to within 1/2 LSB for a given digital input
stimulus, i.e., 0 to Full Scale.
Gain Error: Ratio of the DAC’s operational amplifier output
voltage to the nominal input voltage value.
Feedthrough Error: Error caused by capacitive coupling
from VREF to output with all switches OFF.
Output Capacitance: Capacitance from IOUT1, and IOUT2
terminals to ground.
Output Leakage Current: Current which appears on IOUT1,
terminal when all digital inputs are LOW or on IOUT2 terminal
when all inputs are HIGH.
Detailed Description
The AD7541 is a 12-bit, monolithic, multiplying D/A converter.
A highly stable thin film R-2R resistor ladder network and
NMOS SPDT switches form the basis of the converter circuit.
CMOS level shifters provide low power TTL/CMOS compati-
ble operation. An external voltage or current reference and an
operational amplifier are all that is required for most voltage
output applications. A simplified equivalent circuit of the DAC
is shown on page 1, (Functional Diagram). The NMOS SPDT
switches steer the ladder leg currents between IOUT1 and
IOUT2 buses which must be held at ground potential. This con-
figuration maintains a constant current in each ladder leg
independent of the input code. Converter errors are further
eliminated by using wider metal interconnections between the
major bits and the outputs. Use of high threshold switches
reduces the offset (leakage) errors to a negligible level.
Each circuit is laser-trimmed, at the wafer level, to better than
12-bits linearity. For the first four bits of the ladder, special
trim-tabbed geometries are used to keep the body of the
resistors, carrying the majority of the output current, undis-
turbed. The resultant time stability of the trimmed circuits is
comparable to that of untrimmed units.
The level shifter circuits are comprised of three inverters with
a positive feedback from the output of the second to first
(Figure 1). This configuration results in TTL/COMS compati-
ble operation over the full military temperature range. With
the ladder SPDT switches driven by the level shifter, each
switch is binary weighted for an “ON” resistance proportional
to the respective ladder leg current. This assures a constant
voltage drop across each switch, creating equipotential ter-
minations for the 2R ladder resistor, resulting in accurate leg
currents.
8-24
AD7541
FIGURE 1. CMOS SWITCH
Typical Applications
General Recommendations
Static performance of the AD7541 depends on IOUT1 and
IOUT2 (pin 1 and pin 2) potentials being exactly equal to GND
(pin3).
The output amplifier should be selected to have a low input
bias current (typically less than 75nA), and a low drift
(depending on the temperature range). The voltage offset of
the amplifier should be nulled (typically less than ±200µV).
The bias current compensation resistor in the amplifier’s
non-inverting input can cause a variable offset. Non-inverting
input should be connected to GND with a low resistance
wire.
Ground-loops must be avoided by taking all pins going to
GND to a common point, using separate connections.
The V+ (pin 18) power supply should have a low noise level
and should not have any transients exceeding +17V.
Unused digital inputs must be connected to GND or VDD for
proper operation.
A high value resistor (~1MΩ) can be used to prevent static
charge accumulation, when the inputs are open-circuited for
any reason.
When gain adjustment is required, low tempco (approxi-
mately 50ppm/oC) resistors or trim-pots should be selected.
Unipolar Binary Operation
The circuit configuration for operating the AD7541 in unipo-
lar mode is shown in Figure 2. With positive and negative
VREF values the circuit is capable of 2-Quadrant multiplica-
tion. The “Digital Input Code/Analog Output Value” table for
unipolar mode is given in Table 1. A Schottky diode
(HP5082-2811 or equivalent) prevents IOUT1 from negative
excursions which could damage the device. This precaution
is only necessary with certain high speed amplifiers.
V+
TTL/CMOS
INPUT
13 4
5
6
72
89
TO LADDER
IOUT2 IOUT1
FIGURE 2. UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Zero Offset Adjustment
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output opera-
tional amplifier for 0V ±0.5mV (max) at VOUT.
Gain Adjustment
1. Connect all digital inputs to VDD.
2. Monitor VOUT for a -VREF (1 - 1/212) reading.
3. T o increase VOUT, connect a series resistor, (0Ω to 250Ω),
in the IOUT1 amplifier feedback loop.
4. T o decrease VOUT, connect a series resistor, (0Ω to 250Ω),
between the reference voltage and the VREF terminal.
Bipolar (Offset Binary) Operation
The circuit configuration for operating the AD7541 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage val-
ues Four-Quadrant multiplication can be realized. The “Digi-
tal Input Code/Analog Output Value” table for bipolar mode is
given in Table 2.
TABLE 1. CODE TABLE - UNIPOLAR BINARY OPERATION
DIGITAL INPUT ANALOG OUTPUT
111111111111 -VREF (1 - 1/212)
100000000001 -VREF (1/2 + 1/212)
100000000000 -VREF/2
011111111111 -VREF (1/2 - 1/212)
000000000001 -VREF (1/212)
000000000000 0
17 18
1
4
15 32
AD7541
BIT 1 (MSB)
BIT 12 (LSB)
16
+15V
VREF
GND
IOUT1
IOUT2 6
VOUT
-
+
RFEEDBACK
DIGITAL
INPUT CR1
5
±10V
A
8-25
AD7541
A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A “Logic 0”
input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one
another. The current amplifier at IOUT2 changes the polarity
of IOUT2 current and the transconductance amplifier at IOUT1
output sums the two currents. This configuration doubles the
output range of the DAC. The difference current resulting at
zero offset binary code, (MSB = “Logic 1”, All other bits =
“Logic 0”), is corrected by using an external resistive divider,
from VREF to IOUT2.
Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Set R4 to zero.
3. Connect all digital inputs to “Logic 1”.
4. Adjust IOUT1 amplifier offset zero adjust trimpot for 0V
±0.1mV at IOUT2 amplifier output.
5. Connect a short circuit across R2.
6. Connect all digital inputs to “Logic 0”.
7. Adjust IOUT2 amplifier offset zero adjust trimpot for 0V±0.1mV
at IOUT1 amplifier output.
8. Remove short circuit across R2.
9. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.
10. Adjust R4 for 0V ±0.2mV at VOUT.
Gain Adjustment
1. Connect all digital inputs to VDD.
2. Monitor VOUT for a -VREF (1 - 1/211) volts reading.
3. T o increase VOUT, connect a series resistor, (0Ω to 250Ω),
in the IOUT1 amplifier feedback loop.
4. To decrease VOUT, connect a series resistor , (0Ω to 250Ω),
between the reference voltage and the VREF terminal.
TABLE 2. CODE TABLE - BIPOLAR (OFFSET BINARY)
OPERATION
DIGITAL INPUT ANALOG OUTPUT
111111111111 -VREF (1 - 1/211)
100000000001 -VREF (1/211)
100000000000 0
011111111111 VREF (1/211)
000000000001 VREF (1 - 1/211)
000000000000 VREF
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
IOUT2
6
6
IOUT1
17 18
1
4
15 32
AD7541
BIT 1 (MSB)
BIT 12 (LSB)
16
+15V
VREF
DIGITAL
INPUT
10V
R1 10K
R5 10K
VOUT
-
+A1
-
+A2
GND
R2 10K R3
390k
R4
500Ω
NOTE: R1 AND R2 SHOULD BE 0.01%, LOW-TCR RESISTORS
8-26
AD7541
Test Circuits
FIGURE 4. NONLINEARITY TEST CIRCUIT
FIGURE 5. POWER SUPPLY REJECTION TEST CIRCUIT
FIGURE 6. NOISE TEST CIRCUIT
HA2600
CLOCK
14-BIT
REFERENCE
DAC
-
+
HA2600
-
+
12-BIT
BINARY
COUNTER AD7541
AD7541
17 16
18
1
2
3
15
5
4
LINEARITY
ERROR X 100
10K 0.01%
10K
0.01%
IOUT1
IOUT2
RFEEDBACK
1MΩ
+15V
VREF
BIT 1 (MSB)
BIT 12
(LSB)
VREF
GND
BIT 1
(MSB)
BIT 12
BIT 13
BIT 14
HA2600
+
-
HA2600
+
-
AD7541
17 16
18
1
2
3
15
5
4
VREF +10V
BIT 1 (MSB)
BIT 12
(LSB)
GND
RFEEDBACK
IOUT1
IOUT2
+15V
UNGROUNDED
SINE WAVE
GENERATION
40Hz 1.0VP-P
5K 0.01%
5K 0.01%
500K
VERROR X 100
101ALN
QUAN
TECH
MODEL
134D
WAVE
ANALYZER
AD7541
17 16
2
1
3
15
5
4
+11V (ADJUST FOR VOUT = 0V)
+15V
15µFIOUT2
IOUT1
100Ω10K
VOUT
1K50K
0.1µF
-50V
F = 1KHz
BW = 1Hz
1K
8-27
AD7541
FIGURE 7. OUTPUT CAPACITANCE TEST CIRCUIT FIGURE 8. FEEDTHROUGH ERROR TEST CIRCUIT
FIGURE 9. OUTPUT CURRENT SETTLING TIME TEST CIRCUIT
Test Circuits
(Continued)
SCOPE
AD7541
17 16
18
1
2
3
17
5
4
BIT 1 (MSB)
BIT 12 (LSB)
+15V NC +15V
NC
1K
100mVPP
1MHz HA2600
AD7541
17 16
18
1
2
3
15
5
4
+15V
VOUT
IOUT1
IOUT2
3
26
GND
VREF = 20VPP 10kHz SINE WAVE
BIT 1 (MSB)
BIT 12 (LSB)
VREF +15V
+10V
BIT 1 (MSB)
BIT 12 (LSB)
AD7541
EXTRAPOLATE
+100mV
100Ω
IOUT2
GND
+5V
0V
DIGITAL INPUT
17 16
1
2
3
15
5
4OSCILLOSCOPE
3t: 5% SETTLING
9t: 0.01% SETTLING
Dynamic Performance
The dynamic performance of the DAC, also depends on the
output amplifier selection. For low speed or static applica-
tions, AC specifications of the amplifier are not very critical.
For high-speed applications slew-rate, settling-time, open-
loop gain and gain/phase-margin specifications of the ampli-
fier should be selected for the desired performance.
The output impedance of the AD7541 looking into IOUT1 var-
ies between 10kΩ (RFEEDBACK alone) and 5KΩ (RFEEDBACK
in parallel with the ladder resistance).
Similarly the output capacitance varies between the mini-
mum and the maximum values depending on the input code.
These variations necessitate the use of compensation
capacitors, when high speed amplifiers are used.
A capacitor in parallel with the feedback resistor (as shown
in Figure 10) provides the necessary phase compensation to
critically damp the output.
A small capacitor connected to the compensation pin of the
amplifier may be required for unstable situations causing
oscillations. Careful PC board layout, minimizing parasitic
capacitances, is also vital.
FIGURE 10. GENERAL DAC CIRCUIT WITH COMPENSATION CAPACITOR, CC
VREF
+15V
+10V
BIT 1 (MSB)
BIT 12 (LSB)
AD7541
RFEEDBACK
IOUT2
GND
17 16
1
2
3
15
5
4
BIT 2 18
IOUT1
A
-
+VOUT
CC
