54AC374 •54ACT374
Octal D Flip-Flop with TRI-STATE®Outputs
General Description
The ’AC/’ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and TRI-STATE outputs for bus-oriented applications. Abuff-
ered Clock (CP) and Output Enable (OE) are common to all
flip-flops.
Features
nI
CC
and I
OZ
reduced by 50%
nBuffered positive edge-triggered clock
nTRI-STATE outputs for bus-oriented applications
nOutputs source/sink 24 mA
nSee ’273 for reset version
nSee ’377 for clock enable version
nSee ’373 for transparent latch version
nSee ’574 for broadside pinout version
nSee ’564 for broadside pinout version with inverted
outputs
n’ACT374 has TTL-compatible inputs
nStandard Military Drawing (SMD)
— ’AC374: 5962-87694
— ’ACT374: 5962-87631
Logic Symbols
Pin
Names Description
D
0
–D
7
Data Inputs
CP Clock Pulse Input
OE TRI-STATE Output Enable Input
O
0
–O
7
TRI-STATE Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT®is a registered trademark of Fairchild Semiconductor Corporation.
DS100289-1
IEEE/IEC
DS100289-2
August 1998
54AC374
•
54ACT374 Octal D Flip-Flop with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100289 www.national.com
Connection Diagrams
Functional Description
The ’AC/’ACT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and TRI-STATE true outputs.
The buffered clock and buffered Output Enable are common
to all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When the OE is HIGH, the out-
puts go to the high impedance state. Operation of the OE in-
put does not affect the state of the flip-flops.
Truth Table
Inputs Outputs
D
n
CP OE O
n
HNLH
L
N
LL
XXH Z
H
=
HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance
N=LOW-to-HIGH Transition
Logic Diagram
Pin Assignment for DIP
and Flatpak
DS100289-3
Pin Assignment for LCC
DS100289-4
DS100289-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=−0.5V −20 mA
V
I
=V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=−0.5V −20 mA
V
O
=V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)±50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’AC 2.0V to 6.0V
’ACT 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (V
O
) 0VtoV
CC
Operating Temperature (T
A
)
54AC/ACT −55˚C to +125˚C
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
V
IN
from 30%to 70%of V
CC
V
CC
@3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT®circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
54AC
Symbol Parameter V
CC
T
A
=−55˚C to +125˚C Units Conditions
(V) Guaranteed Limits
V
IH
Minimum High 3.0 2.1 V
OUT
=0.1V
Level Input 4.5 3.15 V or V
CC
− 0.1V
Voltage 5.5 3.85
V
IL
Maximum Low 3.0 0.9 V
OUT
=0.1V
Level Input 4.5 1.35 V or V
CC
− 0.1V
Voltage 5.5 1.65
V
OH
Minimum High 3.0 2.9 I
OUT
=−50 µA
Level Output 4.5 4.4 V
Voltage 5.5 5.4 (Note 2)
V
IN
=V
IL
or V
IH
3.0 2.4 −12 mA
4.5 3.7 V I
OH
−24 mA
5.5 4.7 −24 mA
V
OL
Maximum Low 3.0 0.1 I
OUT
=50 µA
Level Output 4.5 0.1 V
Voltage 5.5 0.1 (Note 2)
V
IN
=V
IL
or V
IH
3.0 0.50 12 mA
4.5 0.50 V I
OL
24 mA
5.5 0.50 24 mA
I
IN
Maximum Input 5.5 ±1.0 µA V
I
=V
CC
, GND
Leakage Current
I
OZ
Maximum V
I
(OE) =V
IL
,V
IH
TRI-STATE 5.5 ±5.0 µA V
I
=V
CC
, GND
Current V
O
=V
CC
, GND
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DC Characteristics for ’AC Family Devices (Continued)
54AC
Symbol Parameter V
CC
T
A
=−55˚C to +125˚C Units Conditions
(V) Guaranteed Limits
I
OLD
(Note 3) Minimum
Dynamic Output
Current
5.5 50 mA V
OLD
=1.65V Max
I
OHD
5.5 −50 mA V
OHD
=3.85V Min
I
CC
Maximum Quiescent 5.5 80.0 µA V
IN
=V
CC
Supply Current or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @3.0V are guaranteed to be less than or equal to the respective limit @5.5V VCC.
ICC for 54AC @25˚C is identical to 74AC @25˚C.
DC Characteristics for ’ACT Family Devices
54ACT
Symbol Parameter V
CC
T
A
=−55˚C to +125˚C Units Conditions
(V) Guaranteed Limits
V
IH
Minimum High
Level Input
Voltage
4.5 2.0 VV
OUT
=0.1V
5.5 2.0 or V
CC
− 0.1V
V
IL
Maximum Low
Level Input
Voltage
4.5 0.8 VV
OUT
=0.1V
5.5 0.8 or V
CC
− 0.1V
V
OH
Minimum High
Level Output
Voltage
4.5 4.4 V I
OUT
=−50 µA
5.5 5.4 (Note 5)
V
IN
=V
IL
or V
IH
4.5 3.70 V I
OH
−24 mA
5.5 4.70 −24 mA
V
OL
Maximum Low
Level Output
Voltage
4.5 0.1 V I
OUT
=50 µA
5.5 0.1 (Note 5)
V
IN
=V
IL
or V
IH
4.5 0.50 V I
OL
24 mA
5.5 0.50 24 mA
I
IN
Maximum Input 5.5 ±1.0 µA V
I
=V
CC
, GND
Leakage Current
I
OZ
Maximum 5.5 ±5.0 µA V
I
=V
IL
,V
IH
TRI-STATE Current V
O
=V
CC
, GND
I
CCT
Maximum 5.5 1.6 mA V
I
=V
CC
− 2.1V
I
CC
/Input
I
OLD
(Note 6) Minimum
Dynamic Output
Current
5.5 50 mA V
OLD
=1.65V Max
I
OHD
5.5 −50 mA V
OHD
=3.85V Min
I
CC
Maximum Quiescent 5.5 80.0 µA V
IN
=V
CC
Supply Current or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
Note 7: ICC for 54ACT @25˚C is identical to 74ACT @25˚C.
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AC Electrical Characteristics
54AC
V
CC
T
A
=−55˚C to +125˚C Fig.
Symbol Parameter (V) C
L
=50 pF Units No.
(Note 8) Min Max
f
max
Maximum Clock 3.3 60 MHz
Frequency 5.0 95
t
PLH
Propagation Delay 3.3 3.0 16.5 ns
CP to O
n
5.0 3.0 12.0
t
PHL
Propagation Delay 3.3 3.0 15.0 ns
CP to O
n
5.0 3.0 11.0
t
PZH
Output Enable Time 3.3 1.0 14.0 ns
5.0 1.5 10.5
t
PZL
Output Enable Time 3.3 1.0 14.0 ns
5.0 1.5 10.5
t
PHZ
Output Disable Time 3.3 1.0 16.0 ns
5.0 1.5 12.5
t
PLZ
Output Disable Time 3.3 1.0 13.0 ns
5.0 1.5 10.5
Note 8: Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements
54AC
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 9) C
L
=50 pF
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW 3.3 6.5 ns
D
n
to CP 5.0 5.0
t
h
Hold Time, HIGH or LOW 3.3 1.0 ns
D
n
to CP 5.0 1.5
t
w
CP Pulse Width, 3.3 6.5 ns
HIGH or LOW 5.0 5.0
Note 9: Voltage Range 3.3 is 3.3V ±0.3V
Voltage Range 5.0 is 5.0V ±0.5V
AC Electrical Characteristics
54ACT
V
CC
T
A
=−55˚C
Symbol Parameter (V) to +125˚C Units
(Note 10) C
L
=50 pF
Min Max
f
max
Maximum Clock 5.0 70 MHz
Frequency
t
PLH
Propagation Delay 5.0 1.5 12.0 ns
CP to O
n
t
PHL
Propagation Delay 5.0 1.5 11.5 ns
CP to O
n
t
PZH
Output Enable Time 5.0 1.5 11.5 ns
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AC Electrical Characteristics (Continued)
54ACT
V
CC
T
A
=−55˚C
Symbol Parameter (V) to +125˚C Units
(Note 10) C
L
=50 pF
Min Max
t
PZL
Output Enable Time 5.0 1.5 11.5 ns
t
PHZ
Output Disable Time 5.0 1.5 13.0 ns
t
PLZ
Output Disable Time 5.0 1.5 11.0 ns
Note 10: Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements
54ACT
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 11) C
L
=50 pF
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW 5.0 5.5 ns
D
n
to CP
t
h
Hold Time, HIGH or LOW 5.0 1.5 ns
D
n
to CP
t
w
CP Pulse Width, 5.0 5.0 ns
HIGH or LOW
Note 11: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF V
CC
=OPEN
C
PD
Power Dissipation 40 pF V
CC
=5.0V
Capacitance
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Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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20 Lead Ceramic Flatpak (F)
NS Package Number W20A
54AC374
•
54ACT374 Octal D Flip-Flop with TRI-STATE Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.