SMBJ28CA - STMICROELECTRONICS - Datasheet.Support

1. General description

The PCA9632 is an I2C-bus controlled 4-bit LED driver optimized for

Red/Green/Blue/Amber (RGBA) color mixing applications. The PCA9632 is a drop-in

upgrade for the PCA96 33 with 40 power reducti on. In Individual brightness control mode,

each LED output has its own 8-bit resolution (256 steps) fixed frequency Individual PWM

controller that operates at 1.5625 kHz with a duty cycle that is adjustable from 0 % to

99.6 % to allow the LED to be set to a specific brightness value. In group dimming mode,

each LED output has its own 6-bit resolution (64 steps) fixed frequency Individual PWM

controller that operates at 6.25 kHz with a duty cycle that is adjustable from 0 % to 98.4 %

to allow the LED to be set to a specific brightness value. A fifth 4-bit resolution (16 steps)

Group PWM controller has a fixe d fr eq ue ncy of 19 0 Hz that is used to dim all the LED s

with the same value.

While operating in the Blink mode, each LED output has its own 8-bit resolution

(256 steps) fixed frequency Individual PWM controller that operates at 1.5625 kHz with a

duty cycle that is adjus table from 0 % to 99.6 % to allow the LED to be set to a specific

brightness value. Blink rate is controlled by the Group frequency setting that has 8-bit

resolution (256 steps). The blink rate is adjustable between 24 Hz and once every

10.73 seconds. For Group frequency settings between 6 Hz and 24 Hz, the Group PWM

has a 6-bit resolution (64 steps) with a duty cycle that is adjustable from 0 % to 98.4 %.

For Group frequency settings be tween 6 Hz and 0.09 Hz (once in 10.73 seconds), the

Group PWM has an 8-bit resolution (256 steps) with a duty cycle that is adjustable from

0 % to 99.6 %.

Each LED output can be off, on (no PWM control), set at its Individual PWM controller

value or at both Individual and Group PWM controller values. The LED output driver is

programmed to be either open-drain with a 25 mA current sink capability at 5 V or

totem pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9632 operates with

a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be

directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external

drivers and a minimum amount of discrete com ponent s for larger current or higher voltage

LEDs.

The PCA9632 is in the new Fast-mode Plus (Fm+) family. Fm+ devices offer higher

frequency (up to 1 MHz) and more densely populated bus operation (up to 4000 pF).

Software programmable LED Group and three Sub Call I2C-bus addresses allow all or

defined groups of PCA9632 devices to respond to a common I2C-bus address, allowing

for example, all red LEDs to be turned on or off at the same time or ma rq ue e ch as ing

effect, thus minimizing I2C-bus commands.

PCA9632

4-bit Fm+ I2C-bus low power LED driver

Rev. 5 — 27 July 2011 Product data sheet

Product data sheet Rev. 5 — 27 July 2011 2 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9632

through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to

their default st ate causin g the outp uts to be set high-impedance . Thi s allows an ea sy an d

quick way to reconfigure all device registers to the same condition.

2. Features and benefits

40 power reduction compared to PCA9633

4 LED drivers. Each output programmable at:

Off

On

Programmable LED brightness

Programmable group dimming/blinking mixed with individual LED brightness

1 MHz Fast-mode Plus I2C-bus interface with 30 mA high drive capability on SDA

output for driving high capacitive buses

256-step (8-bit) linear programmable brightness per LED output varying from fully off

(default) to maximum brightness using a 1.5625 kHz PWM signal in Individual

brightness mode

64-step (6-bit) linear programmable brightness for each LED output varying from fully

off (default) to maximum brightness using a 6.25 kHz PWM signal in group dimming

mode

In group dimming mode, 16-step group brightness control allows global dimming

(using a 190 Hz PWM signal) from fully off to maximum brightness (default)

256-step (8-bit) linear programmable brightness per LED output varying from fully off

(default) to maximum brightness using a 1.5625 kHz PWM signal in group blinking

mode

64-step group blinking with frequency programmable from 24 Hz to 6 Hz and

duty cycle from 0 % to 98.4 %

256-step group blinking with frequency programmable from 6 Hz to 0.09 Hz (10.73 s)

and duty cycle from 0 % to 99.6 %

Four totem pole outputs (sink 25 mA and source 10 mA at 5 V) with software

programmable open -drain LED outputs selection (default at high-imp edance). No input

function.

10-pin package option provides two hardware address pins allowing four devices to

operate on the same bus

Output state change programmable on the Acknowledge or the STOP Command to

update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).

Software Reset feature (SWRST Call) allows the device to be reset through the

I2C-bus

400 kHz internal oscillator requires no external components

Internal power- on res et

Noise filter on SDA/SCL inputs

Edge rate control on outputs

No glitch on power-up

Supports hot insertion

Low standby current of < 1 A

Operating power supply voltage range of 2.3 V to 5.5 V

Product data sheet Rev. 5 — 27 July 2011 3 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

5.5 V tolerant inputs

40 C to +85 C operation

ESD protection exceeds 5000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: TSSOP8, TSSOP10, HVSON8, HVSON10

3. Applications

RGB or RGBA LED drivers for color mixing

LED status information

LED displays

LCD backlights

Keypad backlights for cellular phones or handheld devices

4. Ordering information

Table 1. Ordering information

Type number Topside

mark Package

Name Description Version

PCA9632DP1 9632 TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm SOT505-1

PCA9632DP2 9632 TSSOP10 plastic thin shrink small outline package; 10 leads;

body width 3 mm SOT552-1

PCA9632TK 9632 HVSON8 plastic thermal enhanced very thin small outline package;

no leads; 8 terminals; body 3 30.85 mm SOT908-1

PCA9632TK2 9632 HVSON10 plastic thermal enhanced very thin small outline package;

no leads; 10 terminals; body 3 30.85 mm SOT650-1

Product data sheet Rev. 5 — 27 July 2011 4 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

5. Block diagram

Fig 1. Block diagram of PCA9632

002aad039

I2C-BUS

CONTROL

INPUT FILTER

PCA9632

POWER-ON

RESET

SCL

SDA

VDD

VSS LED

STATE

SELECT

PWM

BRIGHTNESS

CONTROL

GRPFREQ

MUX/

CONTROL

'0' – permanently OFF

'1' – permanently ON

VDD

LEDn

190 Hz

6.25 kHz/

1.56 kHz

400 kHz

OSCILLATOR

24 Hz

0.09 Hz

A0 A1

10-pin version

Product data sheet Rev. 5 — 27 July 2011 5 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

6. Pinning information

6.1 Pinning

6.2 Pin description

[1] HVSON8 package die supply ground is connected to both the VSS pin and the exposed center pad. The

VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,

and board-level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board, and for proper heat conduction through the board thermal vias n eed to be

incorporated in the PCB in the thermal pad region.

Fig 2. Pin configuration for TSSOP8 Fig 3. Pin configuration for TSSOP10

Fig 4. Pin configuration for HVSON8 Fig 5. Pin configuration for HVSON10

PCA9632DP1

LED0 VDD

LED1 SDA

LED2 SCL

LED3 VSS

002aad040

PCA9632DP2

LED0 V

LED1 SDA

LED2 SCL

LED3 A1

A0 V

002aad637

002aad041

PCA9632TK

VSS

LED2

LED3

SCL

LED1 SDA

LED0 VDD

Transparent top view

3 6

2 7

1 8

terminal 1

index area

002aad638

PCA9632TK2

LED3

LED2 SCL

LED1 SDA

LED0 V

Transparent top view

4 7

3 8

2 9

1 10

terminal 1

index area

Table 2. Pin description for TSSOP8 and HVSON8

Symbol Pin Type Description

LED0 1 O LED drive r 0

LED1 2 O LED drive r 1

LED2 3 O LED drive r 2

LED3 4 O LED drive r 3

VSS 5[1] power supply supply ground

SCL 6 I serial clock line

SDA 7 I/O serial data line

VDD 8 power supply supply voltage

Product data sheet Rev. 5 — 27 July 2011 6 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

[1] HVSON10 package die supply ground is connected to both the VSS pin and the exposed center pad. The

VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,

and board-level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board, and for proper heat conduction through the board thermal vias n eed to be

incorporated in the PCB in the thermal pad region.

7. Functional description

Refer to Figure 1 “Block dia gram of PCA9632”.

7.1 Device addresses

Following a START condition, the bus ma st er mus t ou tpu t th e ad dr es s of th e slave it is

accessing.

There are a maximum of 4 possible programmable addresses using the 2 hardware

address pins for the 10-pin version and just one fixed address for the 8-pin version.

7.1.1 Regular I2C-bus slave address

The I2C-bus slave address of the PCA9 63 2 is shown in Figure 6. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW (10-pin versions only).

Remark: Using reserved I2C-bus addresses will interfere with other devices, but only if

the devices are on the bus and/or the bus will be open to other I2C-bus systems at some

later date. In a closed system where the designer controls the address assignment these

addresses can be used since the PCA9632 treats them like any other address. The

LED All Call, Software Reset and PCA9564 or PCA9665 slave address (if on the bus) can

never be used for individual device addresses.

•PCA9632 LED All Call address (1110 000) or Software Reset (0000 0110) which are

active on start-up

•PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on

start-up

•‘reserved for future use’ I2C- bus addresses (0000 011, 1111 1XX)

•slave devices that use the 10-bit addressing scheme (1111 0XX)

Table 3. Pin description for TSSOP10 and HVSON10

Symbol Pin Type Description

LED0 1 O LED drive r 0

LED1 2 O LED drive r 1

LED2 3 O LED drive r 2

LED3 4 O LED drive r 3

A0 5 I address input 0

VSS 6[1] power supply supply ground

A1 7 I address input 1

SCL 8 I serial clock line

SDA 9 I/O serial data line

VDD 10 power supply supply voltage

Product data sheet Rev. 5 — 27 July 2011 7 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

•slave devices that are designed to respond to the General Call address (0000 000)

•High-speed mode (Hs-mode) master code (0000 1XX)

The last bit of the addre ss byte defines the op eration to be per formed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

7.1.2 LED All Call I2C-bus address

•Default power-up value (ALLCALLADR register): E0h or 1110 000

•Programmable through I2C-bus (volatile programming)

•At power-up, LED All Call I2C-bus address is ena bled. PCA9632 se nds an ACK whe n

E0h (R/W = 0) or E1h (R/W = 1) is sent by th e ma st er.

See Section 7.3.8 “LED All Call I2C-bus address, ALLCALLADR” for more detail.

Remark: The default LED All Call I2C-bus address (E0h or 1110 000) must not be used as

a regular I2C-bus slave address since this address is enabled at power-up. All the

PCA9632s on the I2C-bus will acknowledge the address if sent by the I2C-bus master.

7.1.3 LED Sub Call I2C-bus addresses

•3 different I2C-bus addresses can be used

•Default power-up values:

–SUBADR1 register: E2h or 1110 001

–SUBADR2 register: E4h or 1110 010

–SUBADR3 register: E8h or 1110 100

•Programmable through I2C-bus (volatile programming)

•At power-up, Sub Call I2C-bus addresses are disabled. PCA9632 does not send an

ACK when E2h (R/W =0) or E3h (R/W= 1), E4h (R/W = 0) or E5h (R/W =1), or

E8h (R/W = 0) or E9h (R/W = 1) is sen t by th e ma st er.

See Section 7.3.7 “I2C-bus subaddress 1 to 3, SUBADRx” for more detail.

Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus

slave addresses as long as they are disabled.

a. 8-pin version b. 10-pin version

Fig 6. Slave address

R/W

002aab318

1100010

fixed

slave address

R/W

002aab295

1 1 0 0 0 A1 A0

fixed hardware

selectable

slave address

Product data sheet Rev. 5 — 27 July 2011 8 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

7.1.4 Software reset I2C-bus address

The address shown in Figure 7 is used when a re set of the PCA9632 needs to be

performed by the master. The Software Reset address (SWRST Call) must be used with

R/W = 0. If R/W = 1, the PCA9632 does not acknowledge the SWRST. See Section 7.5

“Software reset” for more detail.

Remark: The Software Reset I2C-bus address is a reserved address and cann ot be used

as a regular I2C-bus slave address or as an LED All Call or LED Sub Call address.

7.2 Control register

Following the successful acknowledgement of the slave address, L ED All Call address or

LED Sub Call address, the bus master will send a byte to the PCA9632, which will be

stored in the Control register.

The lowest 4 bit s are used as a pointer to determine which register will be accessed

(D[3:0]). The highest 3 bits are used as Auto-Increment flag and Auto-In crement options

(AI[2:0]). Bit 4 is unused and must be programmed with zero (0) for proper device

operation.

When the Auto-Increment flag is set (AI2 = 1), the four low order bits of the Control

program the registers sequentially. Four different types of Auto-Increment ar e po ss ible ,

depending on AI1 and AI0 values.

Fig 7. Software reset address

002aab416

0000011

R/W

reset state = 80h

Remark: The Control register does not apply to the Software Reset I2C-bus address.

Fig 8. Control register

002aab296

AI2 AI1 AI0 0 D3 D2 D1 D0

Auto-Increment flag

Auto-Increment options

Product data sheet Rev. 5 — 27 July 2011 9 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

Remark: Other combinations not shown in Table 4 (AI[2:0] = 001, 010, and 011) are

reserved and must not be used for proper device operation.

AI[2:0] = 000 is used when the same register must be accessed several times during a

single I2C-bus communication, for exa mple, changes the brightness of a single LED. Dat a

is overwritten each time the register is accessed during a write operation.

AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example,

power-up programming.

AI[2:0] = 101 is used when the four LED drive rs must be individually programmed with

different values during the same I2C-bus communication, for example, changing color

setting to another color setting.

AI[2:0] = 110 is used when the LED drivers must be globally programmed with different

settings during the same I2C-bus communication, for example, global brightness or

blinking change.

AI[2:0] = 111 is used when individual and global changes must be performed during the

same I2C-bus communication, for exam ple, ch angi ng a color and global brightness at the

same time.

Only the 4 least signific an t bits D[3:0] are affected by the AI[2:0] bits.

When the Control register is written, the register entry point determined by D[3:0] is the

first register that will be addres sed (read or write operation), and can be anywhere

between 0000 and 1100 (as defined in Table 5). When AI[2] = 1, the Auto-Increment flag

is set and the rollover value at which the point where the register increment stops and

goes to the next one is determined by AI[2:0]. See Table 4 for rollover values. For

example, if the Control register = 1110 1000 (E8h), then the register addressing sequence

will be (in hex):

08 …0C 00 …07 02 …07 02 …07 02 … as long

as the master keeps sending or reading data.

Table 4. Auto-Increment options

AI2 AI1 AI0 Function

0 0 0 no Auto-Increment

1 0 0 Auto-Increment for al l registers. D3, D2, D1, D0 roll over to ‘0000’ after

the last register (1100) is accessed .

1 0 1 Auto-Increment for Individual brightness registers only. D3, D2, D1, D0

roll over to ‘0010’ after the last register (0101) is accessed.

1 1 0 Auto-Increment fo r global control registers only. D3, D2 , D1, D0 roll over

to ‘0110’ after the last register (0111) is accessed.

1 1 1 Auto-Increment for individual and global control registers only. D3, D2,

D1, D0 roll over to ‘0010’ after the last register (0111) is accessed.

Product data sheet Rev. 5 — 27 July 2011 10 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

7.3 Register definitions

Table 5. Register summary

Only D[3:0] = 0000 t o 1100 are allowed and will be acknowledged. D[3:0] = 1101, 1110, or 1111 are rese rved and will not be

acknowledged.

When writing to the Control register, bit 4 mu st be programmed with logic 0 for proper device operation.

00h 0000MODE1 read/writeMode register 1

01h 0001MODE2 read/writeMode register 2

02h 0010PWM0 read/writebrightness control LED0

03h 0011PWM1 read/writebrightness control LED1

04h 0100PWM2 read/writebrightness control LED2

05h 0101PWM3 read/writebrightness control LED3

06h 0110GRPPWM read/writegroup duty cycle control

07h 0111GRPFREQ read/writegroup frequency

08h 1000LEDOUT read/writeLED output state

09h 1001SUBADR1 read/writeI

2C-bus subaddress 1

0Ah 1010SUBADR2 read/writeI

2C-bus subaddress 2

0Bh 1011SUBADR3 read/writeI

2C-bus subaddress 3

0Ch 1100ALLCALLADRread/writeLED All Call I

2C-bus address

Product data sheet Rev. 5 — 27 July 2011 11 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

7.3.1 Mode register 1, MODE1

[1] It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not

guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window.

[2] When the oscillator is off (Sleep mode), the LED outputs cannot be turned on, off or dimmed/blinked.

7.3.2 Mode register 2, MODE2

[1] See Section 7.6 “Using the PCA9632 with and without external drivers” for more details. Normal LEDs can be driven directly in either

mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI, protect the LEDs, and these must be

driven only in the open-drain mode to prevent overheating the IC.

[2] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9632. Applicable to registers from

02h (PWM0) to 08h (LEDOUT) only.

Table 6. MOD E 1 - Mode register 1 (address 00h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 AI2 read only 0 Register Auto-Increment disabled

1* Register Auto-Increment enabled

6 AI1 read only 0* Auto-Increment bit 1 = 0

1 Auto-Increment bit 1 = 1

5 AI0 read only 0* Auto-Increment bit 0 = 0

1 Auto-Increment bit 0 = 1

4 SLEEP R/W 0 Normal mode[1].

1* Low power mode. Oscillator off[2].

3 SUB1 R/W 0* PCA9632 does not respond to I2C-bus subaddress 1.

1 PCA9632 responds to I2C-bus subaddress 1.

2 SUB2 R/W 0* PCA9632 does not respond to I2C-bus subaddress 2.

1 PCA9632 responds to I2C-bus subaddress 2.

1 SUB3 R/W 0* PCA9632 does not respond to I2C-bus subaddress 3.

1 PCA9632 responds to I2C-bus subaddress 3.

0 ALLCALL R/W 0 PCA9632 does not respond to LED All Call I 2C-bus address.

1* PCA9632 responds to LED All Call I2C-bus address.

Table 7. MOD E 2 - Mode register 2 (address 01h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 - read only 0* reserved

6 - read only 0* reserved

5 DMBLNK R/W 0* Group control = dimming

1 Group control = blinking

4INVRT

[1] R/W 0* Output logic state not inverted. Value to use when no external driver used.

1 Output logic state inverted. Value to use when external driver used.

3 OCH R/W 0* Outputs change on STOP command.[2]

1 Outputs change on ACK.

2OUTDRV

[1] R/W 0* The 4 LED outputs are configured with an open-drain structure.

1 The 4 LED outputs are configured with a totem pole structure.

1 to 0 OUTNE[1:0] R/W 01* unused

Product data sheet Rev. 5 — 27 July 2011 12 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

7.3.3 PWM registers 0 to 3, PWMx — Individual brightness control registers

While operating in Individual brightness mode (LDRx = 10), a 1.5625 kHz fixed frequency

signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h

(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum

brightness). In this mode, all the 8 bits are used.

(1)

E.g., if IDCx[7:0] = 1111 1111, then duty cy cle = 255 / 256 = 99.6 %.

While operating in group dimming mode, a 6.25 kHz fixed frequency signal is used for

each output. Duty cycle is controlled through 64 linear steps from 00h (0 % duty cycle =

LED output off) to 3Fh (98.4 % duty cycle = LED output at maximum brightness). In this

mode only the 6 MSBs are used (IDCx[7:2]). The 2 LSBs IDCx[1:0] are ignored.

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).

(2)

E.g., if IDCx[7:2] = 111111, then duty cycle = 1111 1100 / 256 = 252 / 256 = 98.4 %.

While operating in blink mode, a 1.5625 kHz fixed frequency signal is used for each

output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED

output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). In this mode ,

all the 8 bits are used.

(3)

E.g., if IDCx[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %.

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).

Table 8. PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle

03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle

04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle

05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle

duty cycle IDCx 7:0

256

---------------------------

duty cycle IDCx 7:2,00

256

-----------------------------------

duty cycle IDCx 7:0

256

---------------------------

Product data sheet Rev. 5 — 27 July 2011 13 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

7.3.4 Group duty cycle control, GRPPWM

When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency

signal is superimposed with the 6.25 kHz Individual brightness control signal. GRPPWM

is then used as a global brightness control allowing the LED outputs to be dimmed with

the same value. The value in GRPFREQ is then a ‘don’t care’.

In the group dimming mode (DMBLNK = 0) global brightness for the 4 outputs is

controlled through 16 linear steps from 00h (0 % duty cycle = LED output off) to F0h

(93.75 % duty cycle = maximum brightness). In this mode only the 4 MSBs of the

GRPPWM[7:4] are used. Bits GRPPWM[3:0] are unused.

(4)

E.g., if GDC[7:4] = 1111, then duty cycle = 1111 0000 / 256 = 240 / 256 = 93.75 %.

When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define a

global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to

10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

In this mode, when GRPFREQ is programmed to provide a blinking with frequency

programmable from 24 Hz to 6 Hz, GRPPWM[7:2] is used to provide 64-step duty cycle

resolution from 0 % to 98.4 %. GRPPWM[1:0] bits ar e unused.

(5)

E.g., if GDC[7:2] = 111111, then duty cycle = 11111100 / 256 = 252 / 256 = 98.4 %.

When GRPFREQ is programmed to provide a blinking with frequency prog rammable from

6 Hz to 0.09 Hz (10.73 s), GRPPWM[7:0] is used to provide a 256-step duty cycle

resolution from 0 % to 99.6 %. In this case, all th e 8 bits of the GRPPWM register ar e

used.

(6)

E.g., If GDC[7:0] = 1111 1111, then duty cycle = 255 / 256 = 99.6 %.

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).

Table 9. GRPPWM - Group duty cycle control register (address 06h) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

06h GRPPWM 7:0 GDC[7: 0] R/W 11111111 GRPPWM register

duty cycle GDC 7:4,0000

256

-----------------------------------------

duty cycle GDC 7:2,00

256

-----------------------------------

duty cycle GDC 7:0

256

--------------------------

Product data sheet Rev. 5 — 27 July 2011 14 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

7.3.5 Group frequency, GRPFREQ

GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).

Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)

to FFh (10.73 seconds).

(7)

7.3.6 LED driver output state, LEDOUT

LDRx = 00 — LED driver x is off (default power-up state).

LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking

not controlled ).

LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx

LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be

controlled through its PWMx register and the GRPPWM registers.

7.3.7 I2C-bus subaddress 1 to 3, SUBADRx

Subaddresses are programmable through the I2C-bus. Default power-up va lues are E2h,

E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up

(the corresponding SUBx bit in MODE1 register is equal to logic 0).

Table 10. GRPFREQ - Group frequency register (address 07h) bit descri ption

Legend: * default value.

Address Register Bit Symbol Access Value Description

07h GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register

global blinking period GFRQ 7:01+

---------------------------------------- in ondssec=

Table 11. LEDOUT - LED driver output state register (address 08h) bit d escription

Legend: * default value.

Address Register Bit Symbol Access Value Description

08h LEDOUT 7:6 LDR3 R/W 00* LED3 output state control

5:4 LDR2 R/W 00* LED2 output state control

3:2 LDR1 R/W 00* LED1 output state control

1:0 LDR0 R/W 00* LED0 output state control

Table 12. SUBADR1 to SUBADR3 - I2C-bu s subaddress registers 0 to 3 (addres s 09h to

0Bh) bit description

Legend: * default value.

Address Register Bit Symbol Access Value Description

09h SUBADR1 7:1 A1[7:1] R/W 1110 001* I2C-bus subaddress 1

0 A1[0] R only 0* reserved

0Ah SUBADR2 7:1 A2[7:1] R/W 1110 010* I2C-bus subaddress 2

0 A2[0] R only 0* reserved

0Bh SUBADR3 7:1 A3[7:1] R/W 1110 100* I2C-bus subaddress 3

0 A3[0] R only 0* reserved

Product data sheet Rev. 5 — 27 July 2011 15 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

Once subaddresses have been programmed to their right values, SUBx bits need to be

set to 1 in order to have the device acknowledging these addresses (MODE1 register).

Only the 7 MSBs representing the I2C-bus subaddress are valid. The LSB in SUBADRx

When SUBx is set to 1, the corresponding I2C-bus subaddress can be used during either

an I2C-bus read or wr it e se qu en ce .

7.3.8 LED All Call I2C-bus address, ALLCALLADR

The LED All Call I2C-bus address allows all the PCA9632s in the bus to be programmed

at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default

state). This address is programmable through the I2C-bus and can be use d durin g eit her

an I2C-bus read or write sequence. The register address can be programmed as a

sub call.

Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in

ALLCALLADR register is a read-only bit (0).

If ALLCALL bit = 0, the device d oes not acknowledge the address programmed in register

ALLCALLADR.

7.4 Power-on reset

When power is applied to VDD, an internal power-on reset holds the PCA9632 in a reset

condition until VDD has reached VPOR. At this point, the re set condition is released and the

PCA9632 registers and I2C-bus state machine are initialized to their default states (all

zeroes) causing all the chann els to be deselected. Thereaf ter , V DD must be lowered below

0.2 V to reset the device.

7.5 Software reset

The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to

the power-up st ate value through a specific formatted I2C-bus comman d. To be p erformed

correctly, it implies th at the I2C-bus is functional and that there is no device hanging the

bus.

The SWRST Call function is defined as the following:

1. A START command is sent by the I2C-bus master.

2. The reserved SWRST I2C-bus address ‘0000 011’ with the R/W bit set to 0 (write) is

sent by the I2C-bus master.

3. The PCA9632 device(s) acknowledge(s) after seeing the SWRST Call address

‘0000 0110’ (06h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to

the I2C-bus master.

Table 13. ALLCALLADR - LED All Call I2C-bus address register (address 0Ch) bit

description

Legend: * default value.

Address Register Bit Symbol Access Value Description

0Ch ALLCALLADR 7:1 A C[7:1] R/W 1110 000* ALLCALL I2C-bus

address register

0 AC[0] R only 0* reserve d

Product data sheet Rev. 5 — 27 July 2011 16 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

4. Once the SWRST Call address has been sent and acknowledged, the master sends

2 by te s w ith 2 sp ecif ic valu es (SWRST da ta byte 1 and byte 2):

a. Byte 1 = A5h: the PCA9632 acknowledges this value only. If byte 1 is not equal to

A5h, the PCA9632 does not acknowledge it.

b. Byte 2 = 5Ah: the PCA9632 acknowledges this value only. If byte 2 is not equal to

5Ah, then the PCA9632 does not acknowledge it.

If more than 2 bytes of data are sent, the PCA9632 does not acknowledge any more.

5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and

correctly acknowledged, the master sends a STOP command to end the SWRST Call:

the PCA9632 then resets to the default value (power-up value) and is ready to be

addressed again within the specified bus free time (tBUF).

The I2C-bus master must interpret a non- acknowledge from th e PCA9632 (at any time) a s

a ‘SWRST Call Abort’. The PCA9632 does not initiate a reset of its registers. This

happens only when the format of the SWRST Call sequence is not correct.

7.6 Using the PCA9632 with and without external drivers

The PCA9632 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5 V.

If the device needs to drive LEDs to a higher voltage and/or higher current, use of an

external driver is required.

•INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the

same (PWMx and GRPPWM values directly calculated from their respective for mulas

and the LED output state determined by LEDOUT register value) independently of the

type of external driver.

•OUTDRV bit (MODE2 register) allows minimizing the amount of external component s

required to control the external driver (N-type or P-type device).

[1] Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through curren t limiting resistor).

[2] Optimum configuration when external N-type (NPN, NMOS) driver used.

[3] Optimum configuration when external P-type (PNP, PMOS) driver used.

Table 14. Use of INVRT and OUTDRV based on connection to the LEDn outputs

INVRT OUTDRV Direct connection to LEDn External N-type driver External P-type driver

Firmware External

pull-up

resistor

Firmware External

pull-up

resistor

Firmware External

pull-up

resistor

0 0 formulas and LED

output state values

apply[1]

LED current

limiting R[1] formulas and LED

output state

values inverted

required formulas and LED

output state values

apply

required

0 1 formulas and LED

output state values

apply[1]

LED current

limiting R[1] formulas and LED

output state

values inverted

not required formulas and LED

output state values

apply[3]

not

required[3]

1 0 formulas and LED

output state values

inverted

LED current

limiting R formulas and LED

output state

values apply

required formulas and LED

output state values

inverted

required

1 1 formulas and LED

output state values

inverted

LED current

limiting R formulas and LED

output state

values apply[2]

not

required[2] formulas and LED

output state values

inverted

not required

Product data sheet Rev. 5 — 27 July 2011 17 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

[1] External pull-up or LED current limiting resistor connects LEDn to VDD.

7.7 Individual brightness control with group dimming/blinking

A 1.5625 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is

used to control individually the brightness for each LED.

On top of this signal, one of the following si gnals can be super imposed (this sig nal can be

applied to the 4 LED outputs):

•A lower 190 Hz fixed frequency signal with programmable duty cycle (4 bits, 16 steps)

is used to provide a global brightness control.

•A programmable frequency signal from 24 Hz to 1⁄10.73 Hz (8 bits, 256 steps) with

programmable duty cycle ( 6 bit s, 64 ste p s) is use d to provide a global bl inking control

for (24 Hz to 6 Hz) and (8 bits, 256 steps) for (6 Hz to 1⁄10.73 Hz).

Table 15. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits

LEDOUT INVRT OUTDRV Upper transistor

(VDD to LEDn) Lower transistor (LED n to

VSS)LEDn state

LED driver off 0 0 off off high-Z[1]

01 on off V

10 off on V

11 off on V

LED driver on 00 off on V

01 off on V

1 0 off off high-Z[1]

11 on off V

Individual

brightness

control

0 0 off Individual PWM (non-inverted) VSS or high-Z[1] = PWMx value

0 1 Individual PWM

(non-inverted) Individual PWM (non-inverted) VSS or VDD = PWMx value

1 0 of f Individual PWM (inverted) high-Z[1] or VSS = 1 PWMx value

1 1 Individual PWM

(inverted) Individual PWM (inverted) VDD or VSS = 1 PWMx value

Individual +

group

dimming/

blinking

0 0 off Individual + Group PWM

(non-inverted) VSS or high-Z[1] =

PWMx/GRPPWM values

0 1 Individual PWM

(non-inverted) Individual PWM (non-inverted) VSS or VDD = PWMx/GRPPWM

values

1 0 off Individual + Group PWM

(inverted) high-Z[1] or VSS = (1 PWMx) or

(1 GRPPWM) values

1 1 Individual PWM

(inverted) Individual PWM (inverted) VDD or VSS =(1PWMx) or

(1 GRPPWM) values

Product data sheet Rev. 5 — 27 July 2011 18 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

Minimum pulse width for LEDn brightness control is 2.5 s.

Fig 9. Individual LED brightness control signals

123456789101112 507508509510511512 1234567891011

brightness control signal (LEDn) N × 2.5 μs

with N = (0 to 256)

(PWMx Register)

256 × 2.5 μs = 640 μs

(1.5625 kHz)

002aad101

Minimum pulse width for LEDn brightness control is 2.5 s.

Minimum pulse width for group dimming is 320 s (M = 1).

When M = 1 (GRPPWM register value), the resulting LEDn brightness control + group dimming signal will have 2 pulses of the

LED brightness control signal (pulse width = N 2.5 s, with ‘N’ defined in PWMx register).

Fig 10. Brightnes s + grou p dimming signa ls

123456789101112 2728293031321234567891011

brightness control signal (LEDn)

M × 64 × 2 × 2.5 µs

with M = (1 to 16)

(GRPPWM Register)

N × 2.5 µs

with N = (0 to 64)

(PWMx Register)

64 × 2.5 µs = 160 µs

(6.25 kHz)

1234567812345678

group dimming signal

resulting brightness + group dimming signal (M = 4)

16 × 64 × 2 × 2.5 µs = 5.24 ms (190.7 Hz)

002aad042

Table 16. Dimming and blinking resolution

Type of control LDRx DMBLNK GRPPWM GRPFREQ Frequency PWMx

Individual LED brightness

without dimming 10 X X X 1.5625 kHz 256 steps

Individual LED brightness

with global dimming 11 0 16 steps X 190 Hz with 6.25 kHz modulation 64 steps

Blinking (fast) 11 1 64 steps 256 steps blink frequency = 6 Hz to 24 Hz

PWMx frequency = 1.5625 kHz 256 steps

Blinking (slow) 11 1 256 steps 256 steps blink frequency = 0.09 Hz to 6 Hz

PWMx frequency = 1.5625 kHz 256 steps

Product data sheet Rev. 5 — 27 July 2011 19 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

8. Characteristics of the I2C-bus

The I2C-bus is for 2 -way, 2-line commu nication between dif ferent ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bi t is transferred durin g each clock pulse . The data o n the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 11).

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HI GH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 12).

8.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 13).

Fig 11. Bit trans f er

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 12. Definition of START and STOP conditions

mba608

SDA

SCL P

STOP condition

START condition

Product data sheet Rev. 5 — 27 July 2011 20 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

8.3 Acknowledge

The number of data bytes transferre d be tween the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addresse d must gener ate an acknowledg e af ter the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocke d ou t of th e sla ve tr an smitter. The device that acknowledges has to

pull down the SDA line during the acknowledge cl ock pulse , so that the SDA line is st able

LOW during the HIGH period of the acknowledge related clock pulse; set-up time a nd hold

time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter mus t leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 13. System configuration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Fig 14. Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 5 — 27 July 2011 21 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

9. Bus transactions

(1) 10-pin version only.

(2) See Table 5 for register definition.

Fig 15. Write to a specific register

1 0 0 0 A1 A0 0 AS 1

slave address(1)

START condition R/W

acknowledge

from slave

002aad043

data for register D3, D2, D1, D0(2)

X X 0 D3 D2 D1 D0X

control register

Auto-Increment flag

Auto-Increment options

acknowledge

from slave

acknowledge

from slave

STOP

condition

(1) 10-pin version only.

Fig 16. Write to all registers using the Auto-Increment feature

1 0 0 0 A1 A0 0 AS 1

slave address(1)

START condition R/W

acknowledge

from slave

002aad044

MODE1 register

0 0 0 0 0 0 01

control register

Auto-Increment on

Auto-Increment

on all registers

acknowledge

from slave

acknowledge

from slave

STOP

condition

(cont.)

MODE1

selection

MODE2 register

acknowledge

from slave

SUBADR3 register

acknowledge

from slave

ALLCALLADR register

acknowledge

from slave

Product data sheet Rev. 5 — 27 July 2011 22 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

(1) 10-pin version only.

Fig 17. M ultiple writes to Indi vidual brightnes s registers only using the Auto-Increment fe ature

1 0 0 0 A1 A0 0 AS 1

slave address(1)

START condition R/W

acknowledge

from slave

002aad045

PWM0 register

0 1 0 0 0 1 01

control register

Auto-Increment on

increment

on Individual

brightness

registers only

acknowledge

from slave

acknowledge

from slave

STOP

condition

(cont.)

PWM0

selection

PWM1 register

acknowledge

from slave

PWM2 register

acknowledge

from slave

PWM3 register

acknowledge

from slave

PWM0 register

acknowledge

from slave

PWMx register

acknowledge

from slave

(1) 10-pin version only.

Fig 18. Read all registers using the Auto-Increment featur e

1 0 0 0 A1 A0 0 AS 1

slave address(1)

START condition R/W

acknowledge

from slave

002aad046

0 0 0 0 0 0 01

control register

Auto-Increment on

Auto-Increment

on all registers

acknowledge

from slave

(cont.)

MODE1

selection

data from MODE1 register

acknowledge

from master

ReSTART

condition

A5 A4 A3 A2 A1 A0 1 AA6

slave address

R/W

acknowledge

from slave

data from MODE2 register

acknowledge

from master

data from PWM0

acknowledge

from master

data from

ALLCALLADR register

acknowledge

from master

data from

MODE1 register

acknowledge

from master

(cont.)

data from last read byte

not acknowledge

from master

STOP

condition

Product data sheet Rev. 5 — 27 July 2011 23 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

(1) 10-pin version is used for this figure. Four PCA9632DP2 or PCA9632TK2 and same sequence (A) (above) is sent to each of

them. A[1:0] = 00 to 11.

(2) ALLCALL bit in MODE1 register is equal to logic 1 for this example.

(3) OCH bit in MODE2 register is equal to logic 1 for this example.

Fig 19. LED All Call I2C-bus address programming and LED All Call sequence example

1 0 0 0 A1 A0 0 AS 1

slave address(1)

START condition R/W

acknowledge

from slave

002aad047

X X 0 1 1 0 0X

control register

Auto-Increment on

acknowledge

from slave

ALLCALLADR

0 1 0 1 0 1 X1

new LED All Call I2C-bus address(2)

STOP

condition

acknowledge

from slave

0 1 0 1 0 1 0 AS 1

LED All Call I2C-bus address

START condition R/W

acknowledge

from the

4 devices

X X 0 1 0 0 0X

control register

acknowledge

from the

4 devices

LEDOUT

1 0 1 0 1 0 10

LEDOUT register (LED fully ON)

STOP

condition

acknowledge

from the

4 devices

the 16 LEDs are on at the acknowledge(3)

sequence (A)

sequence (B)

Fig 20. Software Reset (SWRST) Call sequence

002aad048

0 0 0 0 1 1 0 AS 0

SWRST Call I

C address

START condition R/W

acknowledge

from slave(s)

01001011

SWRST data

Byte 1 = A5h

acknowledge

from slave(s)

1 0 1 1 0 1 00

SWRST data

Byte 2 = 5Ah

PCA9632 is(are) reset.

Registers are set to default power-up values.

acknowledge

from slave(s)

Product data sheet Rev. 5 — 27 July 2011 24 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

10. Application design-in information

Question 1: What kind of edge rate control is there on the outputs?

•The typical edge rates depend on the output configuration, supply voltage, and the

applied load. The output s can be configured as either open-drain NMOS or totem pole

outputs. If the cu stomer is using the p art to directly dr ive LEDs, they sh ould be using it

in an open-drain NMOS, if they are concerned about the maximum ISS and ground

bounce. The e dge rate control was desig ned primar ily to slow down the tu rn-on of the

output device; it turns off rather quickly (~ 1.5 ns). I n simulation, the typical turn-on

time for the open-drain NMOS was ~ 14 ns (VDD =3.6V; C

L=50pF; R

PU =500).

Question 2: Is ground bounce po ssible?

•Ground bounce is a possibility, especially if all 16 outputs transition at full current

(25 mA each). There is a fair amount of decoupling capacitance on chip (~ 50 pF),

which is intended to suppress some of the ground bounce. The customer will need to

determine if additional decoupling capacitance externally placed as close as

physically possible to the device is required.

Question 3: Can I really sink 400 mA through the single ground pin on the package and

will this cause any ground bounce problem due to the PWM of the LEDs?

•Yes, you can sink 400 mA through a single ground pin on the package. Although the

package only has one ground pin, there are two ground pads on the die itself

connected to this one pin. Although some ground bounce is likely, it will not disrupt the

operation of the part and would be reduced by the external deco upling capacitance.

Question 4: I can’t turn the LEDs on or off, but their register s are set properly. Why?

•Check the Mode register 1 bit 4 (MODE1[4]) SLEEP setting. The value needs to be a

logic 0 so that the OSC is turned on. If the OSC is turned off, the LEDs cannot be

turned on or off and also can’t be dimmed or blinked.

I2C-bus address = 1100 001X.

All of the 4 LED outputs configurable as either open-drain or totem pole. Mixing of configurations is

not possible.

Fig 21. Typical application

PCA9632

LED0

LED1

SDA

SCL

VDD = 2.5 V, 3.3 V or 5.0 V

I2C-BUS/SMBus

MASTER

002aad049

SDA

SCL

10 kΩ10 kΩ

LED2

LED3

VDD

VSS

5 V 12 V

Product data sheet Rev. 5 — 27 July 2011 25 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

Question 5: I’m using LEDs with integrated Zener diodes and the IC is getting very hot.

Why?

•The IC outputs can be set to either open-drain or push-pull and default to push-pull

outputs. In this application with the Zener diodes, they need to be set to open-drain

since in the push-pull architectu re there is a low resist ance p ath to ground th rough the

Zener and this is causing the IC to ove rheat. The PCA9632 /33/34/35 ICs a ll power-up

in the push-pull outp u t mo de and with th e lo gic state HIGH, so one of the first things

that need to be done is to s et the outputs to open-drain.

11. Limiting values

Table 17. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +6.0 V

VI/O voltage on an input/output pin VSS 0.5 5.5 V

IO(LEDn) output current on pin LEDn - 25 mA

ISS ground supply current - 100 mA

Ptot total power dissipation - 400 mW

Tstg storage temperature 65 +150 C

Tamb ambient temperature operating 40 +85 C

Product data sheet Rev. 5 — 27 July 2011 26 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

12. Static characteristics

[1] VDD must be lowered to 0.2 V in order to reset part.

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits.

Table 18. Static characteristics

VDD = 2.3 V to 5.5 V; VSS =0V; T

amb =





Cto+85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD supply voltage 2.3 - 5.5 V

IDD supply current operating mode; no load; fSCL =1MHz

VDD =2.3V - 38 150 A

VDD =3.3V - 53 150 A

VDD =5.5V - 108 150 A

Istb standby current no load; fSCL = 0 Hz; I/O = inputs; VI=V

VDD = 5.5 V, MODE1[4] = 1 (Sleep mode) - 0.005 1 A

VPOR power-on reset voltage no load; VI=V

DD or VSS [1] - 1.70 2.0 V

Input SCL; input/outpu t S DA

VIL LOW-level input voltage 0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -5.5V

IOL LOW-level output

current VOL = 0.4 V; VDD =2.3V 20 - - mA

VOL = 0.4 V; VDD =5.0V 30 - - mA

ILleakage current VI=V

DD or VSS 1-+1A

Ciinput capacitance VI=V

SS -610pF

LED driver outputs

IOL LOW-level output

current VOL = 0.5 V; VDD =2.3V [2] 12 - - mA

VOL = 0.5 V; VDD =3.0V [2] 17 - - mA

VOL = 0.5 V; VDD =4.5V [2] 25 - - mA

IOL(tot) total LOW-level output

current VOL =0.5V;V

DD =4.5V [2] --100mA

VOH HIGH-level output

voltage IOH =10 mA; VDD = 2.3 V 1.6 - - V

IOH =10 mA; VDD = 3.0 V 2.3 - - V

IOH =10 mA; VDD = 4.5 V 4.0 - - V

Cooutput capacitance - 2.5 5 pF

Product data sheet Rev. 5 — 27 July 2011 27 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

13. Dynamic characteristics

[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held

LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[2] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[3] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to Table 18, VIL of the SCL signal) in

order to bridge the undefined region of SCL’s falling edge.

[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum specified tf.

[6] Cb= total capacitance of one bus line in pF.

[7] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

Table 19. Dynamic characteristics

Symbol Parameter Conditions Standard- mode

I2C-bus Fast-mode

Plus I2C-bus Unit

Min Max Min Max Min Max

fSCL SCL clock frequency [1] 0 100 0 400 0 1000 kHz

tBUF bus free time between a

STOP and START condition 4.7 - 1.3 - 0.5 - s

tHD;STA hold time (repeated) START

condition 4.0 - 0.6 - 0.26 - s

tSU;STA set-up time for a repeated

START condition 4.7 - 0.6 - 0.26 - s

tSU;STO set-up time for STOP

condition 4.0 - 0.6 - 0.26 - s

tHD;DAT data hold time 0 - 0 - 0 - ns

tVD;ACK data valid acknowledge time [2] 0.3 3.45 0.1 0.9 0.05 0.45 s

tVD;DAT data valid time [3] 0.3 3.45 0.1 0.9 0.05 0.45 s

tSU;DAT data set-up time 250 - 100 - 50 - ns

tLOW LOW period of the SCL

clock 4.7 - 1.3 - 0.5 - s

tHIGH HIGH period of the SCL

clock 4.0 - 0.6 - 0.26 - s

tffall time of both SDA and

SCL signals [4][5] - 300 20 + 0.1Cb[6] 300 - 120 ns

trrise time of both SDA and

SCL signals - 1000 20 + 0.1Cb[6] 300 - 120 ns

tSP pulse width of spik es that

must be suppressed by the

input filter

[7] -50 - 50-50ns

Product data sheet Rev. 5 — 27 July 2011 28 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

14. Test information

Fig 22. Definition of timing

tSP

tBUF

tHD;STA PP S

tLOW

tHD;DAT

tHIGH tSU;DAT tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

Rise and fall times refer to VIL and VIH.

Fig 23. I2C-bus timing diagra m

SCL

SDA

HD;STA

SU;DAT

HD;DAT

BUF

SU;STA

LOW

HIGH

VD;ACK

002aab285

SU;STO

protocol START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6) bit 1

(D1) bit 0

(D0)

/ f

SCL

VD;DAT

acknowledge

(A)

STOP

condition

(P)

RL = Load resistor for LEDn. RL for SDA and SCL > 1 k (3 mA or less current).

CL = Load capacitance includes jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.

Fig 24. Test circuitr y for switching times

PULSE

GENERATOR

50 pF

500 Ω

002aab880

DUT

open

Product data sheet Rev. 5 — 27 July 2011 29 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

15. Package outline

Fig 25. Package outline SOT505-1 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.45

0.25 0.28

0.15 3.1

2.9 3.1

2.9 0.65 5.1

4.7 0.70

0.35 6°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1 99-04-09

03-02-18

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

1.1

pin 1 index

Product data sheet Rev. 5 — 27 July 2011 30 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

Fig 26. Package outline SOT908-1 (HVSON8)

0.50.21 0.05

0.00

A1Eh

UNIT D(1) ye

1.5

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

3.1

2.9

2.25

1.95

0.3

0.2 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT908-1 MO-229

E(1)

0.5

0.3

0.1

0.05

SOT908-1

HVSON8: plastic thermal enhanced very thin small outline package; no leads;

8 terminals; body 3 x 3 x 0.85 mm

A(1)

max.

05-09-26

05-10-05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

terminal 1

index area

B A

detail X

A1c

exposed tie bar (4×)

terminal 1

index area

eAC B

vMC wM

0 1 2 mm

scale

Product data sheet Rev. 5 — 27 July 2011 31 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

Fig 27. Package outline SOT552-1 (TSSOP10)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.15 0.23

0.15 3.1

2.9 3.1

2.9 0.5 5.0

4.8 0.67

0.34 6°

0°

0.1 0.10.10.95

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT552-1 99-07-29

03-02-18

0.25

10 6

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm SOT552-1

1.1

pin 1 index

Product data sheet Rev. 5 — 27 July 2011 32 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

Fig 28. Package outline SOT650-1 (HVSON10)

0.50.21 0.05

0.00

A1Eh

UNIT D(1) ye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.75

1.45

3.1

2.9

2.55

2.15

0.30

0.18 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT650-1 MO-229 - - -- - -

E(1)

0.55

0.30

0.1

0.05

0 2 mm1

scale

SOT650-1

HVSON10: plastic thermal enhanced very thin small outline package; no leads;

10 terminals; body 3 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

01-01-22

02-02-08

terminal 1

index area

terminal 1

index area

bAC

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Product data sheet Rev. 5 — 27 July 2011 33 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate prec a ut io ns ar e taken as

described in JESD625-A or equivalent standards.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 5 — 27 July 2011 34 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 29) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged . The peak temperature of the package

depends on package thickness and volume and is classified in acco rdance with

Table 20 and 21

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 29.

Table 20. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Packag e reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 21. Lead-free process (from J-STD-020C)

Package thickness (mm) Packag e reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 5 — 27 July 2011 35 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

For further information on temperature profile s, refer to Application Note AN10365

“Surface mount reflow soldering description”.

18. Abbreviations

MSL: Moisture Sensitivity Level

Fig 29. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 22. Abbreviations

Acronym Description

CDM Charged-Device Model

DUT Device Under Test

ESD ElectroS tatic Discharge

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

LCD Liquid Crystal Display

LED Light Emitting Diode

LSB Least Significant Bit

MSB Most Significant Bit

NMOS Negative-channel Metal-Oxide Semiconductor

PCB Printed-Circuit Board

PMOS Positive-channel Metal-Oxide Semiconductor

PWM Pulse Width Modulation

RGB Red/Green/Blue

RGBA Red/Green/Blue/Amber

SMBus System Management Bus

Product data sheet Rev. 5 — 27 July 2011 36 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

19. Revision history

Table 23. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9632 v.5 20110727 Product data sheet - PCA9632 v.4

Modifications: •Figure 10 “Brightness + group dimming signals” modified

PCA9632 v.4 20110701 Product data sheet - PCA9632 v.3

Modifications: •Section 2 “Features and benefits”, 24th bullet item: deleted phrase “200 V MM per JESD22-A115”

•Table 18 “St atic characteristics ”, sub-section “Supply”:

–Condition for IDD: changed from “fSCL = 0 MHz” to “fSCL =1MHz”

–Condition for Istb: app ended “, MODE1[4] = 1 (Sleep mode)”

PCA9632 v.3 20080715 Product data sheet - PCA9632 v.2

PCA9632 v.2 20080401 Product data sheet - PCA9632 v.1

PCA9632 v.1 20070928 Objective data sheet - -

Product data sheet Rev. 5 — 27 July 2011 37 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

20.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liabili ty towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-crit ical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the appl ication or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms an d conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 5 — 27 July 2011 38 of 39

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for automo tive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims result ing from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

20.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCA9632

4-bit Fm+ I2C-bus low power LED driver

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 July 2011

Document identifier: PCA9632

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

22. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Functional description . . . . . . . . . . . . . . . . . . . 6

7.1 Device addresses. . . . . . . . . . . . . . . . . . . . . . . 6

7.1.1 Regular I2C-bus slave address. . . . . . . . . . . . . 6

7.1.2 LED All Call I2C-bus address . . . . . . . . . . . . . . 7

7.1.3 LED Sub Call I2C-bus addresses . . . . . . . . . . . 7

7.1.4 Software reset I2C-bus address . . . . . . . . . . . . 8

7.2 Control register. . . . . . . . . . . . . . . . . . . . . . . . . 8

7.3 Register definitions. . . . . . . . . . . . . . . . . . . . . 10

7.3.1 Mode register 1, MODE1 . . . . . . . . . . . . . . . . 11

7.3.2 Mode register 2, MODE2 . . . . . . . . . . . . . . . . 11

7.3.3 PWM registers 0 to 3, PWMx — Individual

brightness control registers . . . . . . . . . . . . . . 12

7.3.4 Group duty cycle control, GRPPWM . . . . . . . 13

7.3.5 Group frequency, GRPFREQ . . . . . . . . . . . . . 14

7.3.6 LED driver output state, LEDOUT . . . . . . . . . 14

7.3.7 I2C-bus subaddress 1 to 3, SUBADRx. . . . . . 14

7.3.8 LED All Call I2C-bus address, ALLCALLADR. 15

7.4 Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . 15

7.5 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 15

7.6 Using the PCA9632 with and without external

drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.7 Individual brightness control with group

dimming/blinking. . . . . . . . . . . . . . . . . . . . . . . 17

8 Characteristics of the I2C-bus . . . . . . . . . . . . 19

8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.1.1 START and STOP conditions. . . . . . . . . . . . . 19

8.2 System configuration . . . . . . . . . . . . . . . . . . . 19

8.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20

9 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 21

10 Application design-in information . . . . . . . . . 24

11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 25

12 Static characteristics. . . . . . . . . . . . . . . . . . . . 26

13 Dynamic characteristics . . . . . . . . . . . . . . . . . 27

14 Test information. . . . . . . . . . . . . . . . . . . . . . . . 28

15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29

16 Handling information. . . . . . . . . . . . . . . . . . . . 33

17 Soldering of SMD packages . . . . . . . . . . . . . . 33

17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 33

17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 33

17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 33

17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 34

18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 35

19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 36

20 Legal information . . . . . . . . . . . . . . . . . . . . . . 37

20.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 37

20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 37

20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38

21 Contact information . . . . . . . . . . . . . . . . . . . . 38

22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39