2009-2011 Microchip Technology Inc. DS80485H-page 1
PIC16(L)F1826/1827
The PIC16(L)F1826/1827 family devices that you have
received conform functionally to the current Device Data
Sheet (DS41391D), except for the anomalies described
in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata describ ed in this document will be addressed
in future revisions of the PIC16(L)F1826/1827 silicon.
Data Sheet clarifications and co rrections st art on page 9,
following the discu ssion of silicon issues .
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1. Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
2. From the main menu in MPLAB IDE, select
Configure>Select Device, and then select the
target part number in the dialog box.
3. Select the MPLAB hardware tool
(Debugger>Select Tool).
4. Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the
development tool used, the part number and
Device Revision ID value appear in the Output
window.
The DEVREV values for the various PIC16(L)F1826/
1827 silicon revisions are shown in Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (A5).
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Par t Number Device ID(1) Revision ID for Silicon Revision(2)
A2 A3 A4 A5
PIC16F1826 10 0111 100x xxxx 2345
PIC16LF1826 10 1000 100x xxxx 2345
PIC16F1827 10 0111 101x xxxx 2345
PIC16LF1827 10 1000 101x xxxx 2345
Note 1: The Devic e ID is located in the l ast configuration memory space.
2: Refer to the “PIC16F/LF182X/PIC12F/LF1822 Memory Programming Specification” (DS41390) for
detailed information on Device and Revision IDs for your specific device.
PIC16(L)F1826/1827 Family
Silicon Errata and Data Sheet Clarification
PIC16(L)F1826/1827
DS80485H-page 2 2009-2011 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item
Number Issue Summary Affected Revisions(1)
A2 A3 A4 A5
Data EE Memory Memory Endurance 1.1 Erase/Write endurance limited. X X
Program Flash
Memory (PFM) Endurance 2.1 Erase/Write endurance limited. X X
Timer1 T imer0 Ga te Source 3.1 Toggle mode works improperly. X X
Oscillator HS mode 4.1 Frequency/Voltage range. X X X X
ADC ADC Conversion 5.1 ADC Conversion may not
complete. XX
Enhance d Captu re
Compare PWM
(ECCP)
Enhanced PWM 6.1 PWM 0% duty cycle direction
change. XX
Enhance d Captu re
Compare PWM
(ECCP)
Enhanced PWM 6.2 PWM 0% duty cycle port
steering. XX
Resets Power-on Reset (POR) 7.1 Reset und er low -po wer
conditions. X
Timer1 T1 Gate Toggle mode 8.1 T1 gate flip-flop does not clear. X X
BOR Wake-up from Sleep 9.1 Device resets on wake-up from
Sleep (LF devices only ). XXX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
2009-2011 Microchip Technology Inc. DS80485H-page 3
PIC16(L)F1826/1827
Silicon Errata Issues
1. Module: Data EE Memory
1.1 Data EE Memory Endurance
The ty pical write/ eras e endur ance of the Data EE
Memory is limited to 10k cycles.
Work around
Use error correction method that stores data in
multiple locations.
Affected Silicon Revisions
2. Module: Program Flash Memory (PFM)
2.1 Program Flash Memory Endurance
The typical write/erase endurance of the PFM is
limited to 1k cycles when VDD is above 3.0 volts.
Work around
Use an error correction method that stores data
in multiple locations.
Affected Silicon Revisions
3. Module: Timer1
3.1 Timer1 Gate Toggle Mode with Timer0 as
Gate Source
Timer1 Gate Toggle mode provides unexpected
results when Timer0 overflow is selected as the
Timer1 gate source. We do not recommend using
Timer0 overflow as the Timer1 gate source while
in Timer1 Gate Toggle mode or when Toggle
mode is used in conjunction with Timer1 Gate
Single-Puls e mode.
Work around
None.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A5).
A2 A3 A4 A5
X X
A2 A3 A4 A5
X X
A2 A3 A4 A5
X X
PIC16(L)F1826/1827
DS80485H-page 4 2009-2011 Microchip Technology Inc.
4. Module: Oscillator
4.1 HS Oscillator Frequency
The Standard Operating Conditions for the HS
Osci llator are as follows:
Work around
None.
Affected Silicon Revisions
Characteristic Min. Typ† Max. Units Conditions Operating Temperature
Oscillator Frequency 1 — 20 MHz HS Oscillator mode, VDD > 2.3V -40°C TA +85°C
Oscillator Frequency 1 — 20 MHz HS Oscillator mode, VDD 2.8V -40°C TA +125°C
A2 A3 A4 A5
XXXX
2009-2011 Microchip Technology Inc. DS80485H-page 5
PIC16(L)F1826/1827
5. Module: ADC
5.1 Analog-to-Digital Conversion
An ADC conversion may not c omplete unde r these
conditions:
1. When FOSC is greater than 8 MHz and it is the
clock source used for the ADC converter.
2. The ADC is operating from its ded icated int ernal
FRC oscillator and the device is not in Sleep
mode (any FOSC frequency).
When this occurs, the ADC Interrupt Flag (ADIF)
does not get set, the GO/DONE bit does not get
cleared, and the conversion result does not get
loaded into the ADRESH and ADRESL result
registers.
Work around
Method 1: Select the system clock, FOSC, as
the ADC clock s ource and reduce
the FOSC frequency to 8 MHz or
less when performing ADC
conversions.
Method 2: Select the dedicated FRC
osci llator as the AD C conve rsion
clock source and perform all
conversions with the device in
Sleep.
Method 3: This method is provided if the
application cannot use Sleep
mode and requires continuous
operation at frequencies above 8
MHz. This method requires early
termination of an ADC conver-
sion. Prov ide a fixed time delay in
software to stop the A-to-D
conversion manually, after all 10
bits are converted, but before the
conversion would complete
automatically. The conversion is
stopped by clearing the GO/
DONE bit in software. The GO/
DONE bit must be cleared during
the last ½ TAD cycle, before the
conversion would have
comple ted automatical ly. Refer to
Figure 1 for details.
FIGURE 1: INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE
In Figure 1, 88 instruction cycles (TCY) will be
required to complete the full c onvers ion. Each TAD
cycle consists of 8 TCY periods. A fixed delay is
provided to stop the A/D conversion after 86
instruction cycles and terminate the conversion at
the correct time as shown in the figure above.
FOSC = 32 MHz
TCY = 4/32 MHz = 125 nsec
TAD = 1 µsec, ADCS = FOSC/32
88 TCY
84 TCY
8 TCY
4 TCY
1 TAD 11 TAD
Stop the A/D conversion
between 10.5 and 11 TAD
cycles.
See the Analog-to-Digital
Conversion TAD Cycles
figure in the Analog-to-
Digital Converter chapter of
the device data sheet.
}
See the ADC Clock Period (TAD) vs. Device Operating Frequencies table, in the Analog-to-Digital Converter
section of the device data sheet.
PIC16(L)F1826/1827
DS80485H-page 6 2009-2011 Microchip Technology Inc.
EXAMPLE 1: CODE EXAMPLE OF
INSTRUCTION CYCLE
DELAY
For other combinations of FOSC, TAD values and
Instruction cycle delay counts, refer to Table 3.
TABLE 3: INSTRUCTION CYCLE DELAY
COUNTS BY TAD SELECTION
Affected Silicon Revisions
6. Module: Enhanced Capture Compare
PWM (ECCP)
6.1 Enhanced PWM
When the PW M is confi gured for Ful l-Bridge mod e
and the duty cycle is set to 0%, writing the
PxM<1:0> bits to change the direction has no
effect on PxA and PxC outputs.
Work around
Increas e the duty cycl e to a va lue grea ter than 0 %
before changing directions.
Affected Silicon Revisions
6.2 Enhanced PWM
In PWM mode, when the duty cycle is set to 0%
and the STRxSYNC bit is set, writing the STRxA,
STRxB, STRxC and the STRxD bits to enable/
disable steering to port pins has no effect on the
outputs.
Work around
Increas e the duty cycl e to a va lue grea ter than 0 %
before enabling/disabling steering to port pins.
Affected Silicon Revisions
Note: The exact delay time will depend on the
TAD divisor (ADCS) selection. The TCY
count s sho wn in the tim ing diag ram abo ve
apply to this example only. Refer to
Table 3 for the required delay counts for
other configurations.
TAD Instruction Cycle Delay Counts
FOSC/64 172
FOSC/32 86
FOSC/16 43
A2 A3 A4 A5
X X
BSF ADCON0, ADGO ; Start ADC conversion
; Provide 86
instruction cycle
delay here
BCF ADCON0, ADGO ; Terminate the
conversion manually
MOVF ADRESH, W ; Read conversion
result
A2 A3 A4 A5
X X
A2 A3 A4 A5
X X
2009-2011 Microchip Technology Inc. DS80485H-page 7
PIC16(L)F1826/1827
7. Module: Resets
7.1 Reset under Low-Power Conditions
This issue pertains only to the F product version,
PIC16F1826/1827. The LF product version,
PIC16LF 1826/1827 , is not af fected by th is issue in
any way.
When employing any one of the low-power
oscillators (ECL mode, LP mode, LFINTOSC, or
Timer1 Oscillator as alternate system clock
source) at temperatures of -20°C or colder while,
at the same time, the source voltage supplied to
the VDD pin drops below 2.7 volts, the device may
exper ience a Po wer-on Re set (POR). A lso, when
the source volt age supplied to the VDD pin is below
2.7 vol ts, at temperature s of -20°C or cold er , and a
SLEEP instruction is executed, the device may
experience a Power-on Reset (POR) upon
entering Sleep mode, regardless of the type of
clock source bein g used or which power-manage d
mode is being employed.
Work around
There are three separate work-arounds and one
recommendation available to avoid this Reset
condition. Employing any one of these will avoid
this reset condition.
1. Enabling the Brown-out Reset (BOR) circuitry.
2. Enabling the Fixed Voltage Reference (FVR)
module.
3. Maint aining a source voltage (VDD) to the device
above 2 .7 v ol ts when operating at tempera ture s
of -20°C or colder.
4. Use the LF product version (PIC16LF1826/
1827) when the VDD required is between 1.8V
and 3.6V.
The ‘Affected Silicon Revisions’ below refers only
to the F product version, PIC16F1826/1827.
Affected Silicon Revisions
8. Module: Timer1
8.1 Timer1 Gate Toggle mode
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a
Timer1 gate signal. To perform this function, the
Timer1 gate source is routed through a flip-flop
that changes state on every incrementing edge of
the gate signal. Timer1 Gate Toggle mode is
enabled by setting the T1GTM bit of the T1GCON
register. When working properly, clearing either
the T1GT M bit or th e TMR1ON bit wou ld also cle ar
the output value of this flip-flop, and hold it clear.
This is do ne in order to contr ol which edge is being
measured. The issue that exist s is that clearing the
TMR1ON bit does not clear the output value of the
flip-flop and hold it clear.
Work around
Clear the T1GTM bit in the T1GCON register to
clear and hold clear the output value of the flip-flop.
Affected Silicon Revisions
A2 A3 A4 A5
X
A2 A3 A4 A5
X X
PIC16(L)F1826/1827
DS80485H-page 8 2009-2011 Microchip Technology Inc.
9. Module: BOR
9.1 BOR Re set
This issue affects only the PIC16LF1826/1827
devices. The device may undergo a BOR Reset
when waking-up from Sleep and BOR is re-
enabled. A BOR Reset may also occur the
moment the software BOR is enable d.
Unde r certain voltage and te mper ature co nditi ons
and when either SBODEN or BOR_NSLEEP is
select ed, the devices may occasionally reset when
waking-up from Sleep or BOR is enabled.
Work around
Method 1: In appli catio ns w here BO R use is
not critical, turn off the BOR in the
Configurati on Word .
Method 2: Set the FVREN bit of the
FVRCON register. Maintain this
bit on at all times.
Method 3: When BOR module is needed
only during run-time, use the
softw are - en a ble d B OR by set ti ng
the SBODEN option on the
Conf igurat ion Word. BO R sho uld
be turned off by software before
Sleep, then follow the below
sequence for turning BOR on
after Wake-up:
a. Wake-up event occurs;
b. T urn on FVR (FVREN bit of the
FVRCON register);
c. Wait until FVRRDY bit is set;
d. Wait 15 µs after the FVR
Ready bit is set;
e. Manually turn on the BOR.
Method 4: Use the software-enabled BOR
as des cribed in Me thod 3, but us e
the following sequence:
a. Switch to internal 32 kHz
oscillator immediately before
Sleep;
b. Upon wake-up, turn on FVR
(FVREN bit of the FVRCON
register);
c. Manually turn on the BOR;
d. Switch the clock back to the
prefe rred clo ck sourc e.
Affected Silicon Revisions
Note: When using the software BOR follow the
steps in Methods 3 or 4 above when
enabling BOR for the first time during
program execution.
A2 A3 A4 A5
XXX
2009-2011 Microchip Technology Inc. DS80485H-page 9
PIC16(L)F1826/1827
Data Sheet Clarifications
The foll owing ty pographic corrections and clar ification s
are to be note d fo r the latest version of th e d evi ce data
sheet (DS41391D):
1. Module: Temperature Indicator
In Register 14-1: FVRCON: Fixed Voltage
Reference Control Register, the TSEN and
TSRNG bits that enable and select the range for
the temp erature ind icator module are missing. Th e
corrected register table is shown below.
REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FVREN FVRRDY(1) TSEN TSRNG CDAFVR<1:0> ADFVR<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 FVREN: Fixed Voltage Reference Enable bit
0 = Fixed Voltage Reference is disabled
1 = Fixed Voltage Reference is enabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
0 = Fixed Volt age Referen ce output is not ready or not enabled
1 = Fixed Volt age Referen ce output is ready for use
bit 5 TSEN: Te mperature Indicator Enable bit(3)
0 = Temperature Indicator is disabled
1 = Temperature Indicator is enab led
bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
0 =VOUT = VDD - 2VT (Low Range)
1 =V
OUT = VDD - 4VT (High Range)
bit 3-2 CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit
00 = Comparator and DAC Fixed Voltage Reference Peripheral output is off.
01 = Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V)
10 = Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11 = Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit
00 = ADC Fixed Voltage Referen ce Peri phe ral outp ut is off.
01 = ADC Fixed Voltage Referen ce Peri phe ral outp ut is 1x (1.024V)
10 = ADC Fixed Voltage Referen ce Peri phe ral outp ut is 2x (2.048V) (2)
11 = ADC Fixed Voltage Referen ce Peri phe ral outp ut is 4x (4.096V) (2)
Note 1: FVRRDY is always ‘1’ on devices with LDO (PIC16F1826/27).
2: Fixed Voltage Reference output cannot exceed VDD.
3: See Section 15.0, “Temperature Indicator Module”, for additional information.
PIC16(L)F1826/1827
DS80485H-page 10 2009-2011 Microchip Technology Inc.
APPENDIX A: DOCUMENT
REVISION HISTORY
Rev A Document (10/2009)
Initial release of this docum ent.
Rev B Document (02/2010)
Added PIC16F1826 and PIC16F1827 to this errata;
Added Rev. A3 for PIC16F/LF1826/1827.
Data Sheet Clarifications: Added Modules 1 thru 5.
Rev C Document (05/2010)
Added Modules 5, 6 and 7.
Rev D Document (06/2010)
Removed Module 6 (Oscillator); Added Modules 7
(Resets) and 8 (Timer1).
Data Sheet Clarifications: Removed Modules 1 to 5.
Rev E Document (07/2010)
Revised Module 5.1; Other minor corrections.
Rev F Document (09/2010)
Added Silicon Revision A4.
Rev G Document (02/2011)
Added Module 9.
Rev H Document (05/2011)
Added Silicon Revision A5.
Data Sheet Clarifications: Added Module 1.
2009-2011 Microchip Technology Inc. DS80485H-page 11
Information contained in this publication regarding device
applications a nd the lik e is provided only f or yo ur convenience
and may be supers ed ed by u pda t es . It is y our responsibil it y to
ensure that your application meets with your specifications.
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
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PIC32 logo, rfPIC and UNI/O are registered tr ademarks of
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Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense , HI- TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PI CC-18, PICDEM, PICDEM.net, PICkit,
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All other trademarks mentioned herein are property of their
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© 2009-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-194-0
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPI C® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS80485H-page 12 2009-2011 Microchip Technology Inc.
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Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Ma drid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921- 5869
Fax: 44-118-921-5820
Worldwide Sales and Service
05/02/11
