SN74AC373PWRG4 - Texas Instruments

SN54AC373, SN74AC373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D2-V to 6-V VCC Operation

DInputs Accept Voltages to 6 V

DMax tpd of 9.5 ns at 5 V

D3-State Noninverting Outputs Drive Bus

Lines Directly

DFull Parallel Access for Loading

description/ordering information

These 8-bit latches feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The eight latches are D-type transparent latches.

When the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is

taken low, the Q outputs are latched at the logic

levels set up at the D inputs.

A buffered output-enable (OE) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines in bus-organized systems without need for

interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

ORDERING INFORMATION

TAPACKAGE†ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AC373N SN74AC373N

SOIC DW

Tube SN74AC373DW

AC373

SOIC − DW Tape and reel SN74AC373DWR AC373

−40°C to 85°CSOP − NS Tape and reel SN74AC373NSR AC373

40 C

85 C

SSOP − DB Tape and reel SN74AC373DBR AC373

TSSOP PW

Tube SN74AC373PW

AC373

TSSOP − PW Tape and reel SN74AC373PWR AC373

CDIP − J Tube SNJ54AC373J SNJ54AC373J

−55°C to 125°CCFP − W Tube SNJ54AC373W SNJ54AC373W

55 C

125 C

LCCC − FK Tube SNJ54AC373FK SNJ54AC373FK

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

VCC

3 2 1 20 19

910111213

5D 8Q

GND

SN54AC373 . . . FK PACKAGE

(TOP VIEW)

SN54AC373 ...J OR W PACKAGE

SN74AC373 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SN54AC373, SN74AC373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

FUNCTION TABLE

(each latch)

INPUTS OUTPUT

OE LE D

OUTPUT

L H H H

LHL L

LLX Q

H X X Z

logic diagram (positive logic)

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

SN54AC373, SN74AC373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54AC373 SN74AC373

UNIT

MIN MAX MIN MAX UNIT

VCC Supply voltage 2 6 2 6 V

VCC = 3 V 2.1 2.1

VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V

VIH

High level

input

voltage

VCC = 5.5 V 3.85 3.85

VCC = 3 V 0.9 0.9

VIL Low-level input voltage VCC = 4.5V 1.35 1.35 V

VIL

Low level

input

voltage

VCC = 5.5 V 1.65 1.65

VIInput voltage 0 VCC 0 VCC V

VOOutput voltage 0 VCC 0 VCC V

VCC = 3 V −12 −12

IOH High-level output current VCC = 4.5 V −24 −24 mA

IOH

High level

output

current

VCC = 5.5 V −24 −24

VCC = 3 V 12 12

IOL Low-level output current VCC = 4.5 V 24 24 mA

IOL

Low level

output

current

VCC = 5.5 V 24 24

Δt/ΔvInput transition rise or fall rate 8 8 ns/V

TAOperating free-air temperature −55 125 −40 85 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25°C SN54AC373 SN74AC373

UNIT

PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT

3 V 2.9 2.9 2.9

IOH = −50 μA4.5 V 4.4 4.4 4.4

IOH

μA

5.5 V 5.4 5.4 5.4

VOH IOH = −12 mA 3 V 2.56 2.4 2.46 V

I24 mA

4.5 V 3.86 3.7 3.76

IOH = −24 mA 5.5 V 4.86 4.7 4.76

3 V 0.1 0.1 0.1

IOL = 50 μA4.5 V 0.1 0.1 0.1

IOL

μA

5.5 V 0.1 0.1 0.1

VOL IOL = 12 mA 3 V 0.36 0.5 0.44 V

I24 mA

4.5 V 0.36 0.5 0.44

IOL = 24 mA 5.5 V 0.36 0.5 0.44

IIVI = VCC or GND 5.5 V ±0.1 ±1±1μA

IOZ VO = VCC or GND 5.5 V ±0.25 ±5±2.5 μA

ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 μA

CiVI = VCC or GND 5 V 4.5 pF

SN54AC373, SN74AC373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ±0.3 V

(unless otherwise noted) (see Figure 1)

TA = 25°C SN54AC373 SN74AC373

UNIT

MIN MAX MIN MAX MIN MAX UNIT

twPulse duration, LE high 5.5 6.5 6 ns

tsu Setup time, data before LE↓5.5 6.5 6 ns

thHold time, data after LE↓1 1 1 ns

timing requirements over recommended operating free-air temperature range, VCC = 5 V ±0.5 V

(unless otherwise noted) (see Figure 1)

TA = 25°C SN54AC373 SN74AC373

UNIT

MIN MAX MIN MAX MIN MAX UNIT

twPulse duration, LE high 4 5 4.5 ns

tsu Setup time, data before LE↓4 5 4.5 ns

thHold time, data after LE↓1 1 1 ns

switching characteristics over recommended operating free-air temperature range,

VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)

PARAMETER

TO TO TA = 25°C SN54AC373 SN74AC373

UNIT

PARAMETER

(INPUT)

(OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT

tPLH

1.5 10 13.5 1 16.5 1.5 15

tPHL

D Q 1.5 9.5 13.0 1 16 1.5 14.5 ns

tPLH

1.5 10 13.5 1 16.5 1.5 15

tPHL

LE Q 1.5 9.5 12.5 1 15 1.5 14 ns

tPZH

1.5 9 11.5 1 14 1 13

tPZL

OE Q1.5 8.5 11.5 1 13.5 1 13 ns

tPHZ

1.5 10 12.5 1 16 1 14.5

tPLZ

OE Q1.5 8 11.5 1 13 1 12.5 ns

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER

TO TO TA = 25°C SN54AC373 SN74AC373

UNIT

PARAMETER

(INPUT)

(OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT

tPLH

1.5 7 9.5 1 11.5 1.5 10.5

tPHL

D Q 1.5 7 9.5 1 11.5 1.5 10.5 ns

tPLH

1.5 7.5 9.5 1 12 1.5 10.5

tPHL

LE Q 1.5 7 9.5 1 11 1.5 10.5 ns

tPZH

1.5 7 8.5 1 10.5 1 9.5

tPZL

OE Q1.5 6.5 8.5 1 10 1 9.5 ns

tPHZ

1.5 8 11 1 13.5 1 12.5

tPLZ

OE Q1.5 6.5 8.5 1 10.5 1 10 ns

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF

SN54AC373, SN74AC373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS540D − OCTOBER 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

50% VCC

VCC

0 V

tsu

VOLTAGE WAVEFORMS

Data Input

tPLH

tPHL

tPLH

VOH

VOL

VCC

0 V

50% VCC

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

50% VCC

VOLTAGE WAVEFORMS

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

2 × VCC

500 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × VCC

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

≈VCC

0 V

50%VCC VOL + 0.3 V

50% VCC

≈0 V

Open

VOLTAGE WAVEFORMS

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

2 × VCC

Open

TEST S1

3 V

0 V

VOLTAGE WAVEFORMS

Input

50% VCC 50% VCC

VOH − 0.3 V

50% VCC

VCC

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

PACKAGE OPTION ADDENDUM

www.ti.com 23-Mar-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

5962-87555012A ACTIVE LCCC FK 20 1 TBD Call TI Call TI

5962-8755501RA ACTIVE CDIP J 20 1 TBD Call TI Call TI

5962-8755501SA ACTIVE CFP W 20 1 TBD Call TI Call TI

5962-8755501VRA ACTIVE CDIP J 20 20 TBD A42 N / A for Pkg Type

5962-8755501VSA ACTIVE CFP W 20 25 TBD Call TI N / A for Pkg Type

SN74AC373DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI

SN74AC373DBR ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373DW ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373DWE4 ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373DWG4 ACTIVE SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373DWR ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

SN74AC373NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

SN74AC373NSR ACTIVE SO NS 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373NSRE4 ACTIVE SO NS 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373NSRG4 ACTIVE SO NS 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 23-Mar-2012

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

SN74AC373PW ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI

SN74AC373PWR ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AC373PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SNJ54AC373FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type

SNJ54AC373J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type

SNJ54AC373W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

PACKAGE OPTION ADDENDUM

www.ti.com 23-Mar-2012

Addendum-Page 3

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54AC373, SN54AC373-SP, SN74AC373 :

•Catalog: SN74AC373, SN54AC373

•Enhanced Product: SN74AC373-EP, SN74AC373-EP

•Military: SN54AC373

•Space: SN54AC373-SP

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

•Military - QML certified for Military and Defense Applications

•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN74AC373DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

SN74AC373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

SN74AC373NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1

SN74AC373PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74AC373DBR SSOP DB 20 2000 367.0 367.0 38.0

SN74AC373DWR SOIC DW 20 2000 367.0 367.0 45.0

SN74AC373NSR SO NS 20 2000 367.0 367.0 45.0

SN74AC373PWR TSSOP PW 20 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265