1. General description
The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin
compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three
binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight
mutually exclusive outputs (Y0 to Y7) that are LOW when selected.
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74AHC138; 74AHCT138 devices and one
inverter. The 74AHC138; 74AHCT138 can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data input and the remaining enable
inputs as strobes. Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
2. Features
■Balanced propagation delays
■All inputs have Schmitt-trigger action
■Demultiplexing capability
■Multiple input enable for easy expansion
■Ideal for memory chip select decoding
■Inputs accepts voltages higher than VCC
■For 74AHC138 only: operates with CMOS input levels
■For 74AHCT138 only: operates with TTL input levels
■ESD protection:
◆HBM JESD22-A114E exceeds 2000 V
◆MM JESD22-A115-A exceeds 200 V
◆CDM JESD22-C101C exceeds 1000 V
■Multiple package options
■Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
Rev. 03 — 28 November 2007 Product data sheet
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 2 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC138D −40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74AHCT138D
74AHC138PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74AHCT138PW
74AHC138BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal-enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 ×3.5 × 0.85 mm
SOT763-1
74AHCT138BQ
Fig 1. Logic symbol Fig 2. IEC logic symbol
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7 7
9
10
11
12
13
14
15A0
A1
A2
3
2
1
6
5
4E2
E1
E3
mna370
mna371
7
9
10
11
12
13
14
&
X/Y 15
7
EN6
5
4
3
2
1
0
6
5
4
3
2
11
4
2
7
9
10
11
12
13
14
&
DX
(a) (b)
15
7
6
5
4
3
2
1
0
6
5
4
3
2
10
2
G0
7
Fig 3. Functional diagram
mna372
ENABLE
EXITING
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7 7
9
10
11
12
13
14
15
A0
A1
A2 3-to-8
DECODER
3
2
1
6
5
4
E2
E1
E3
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 3 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration for SO16 and TSSOP16 Fig 5. Pin configuration for DHVQFN16
138
A0 VCC
A1 Y0
A2 Y1
E1 Y2
E2 Y3
E3 Y4
Y7 Y5
GND Y6
001aad033
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aad035
138
GND(1)
Y7 Y5
E3 Y4
E2 Y3
E1 Y2
A2 Y1
A1 Y0
GND
Y6
A0
VCC
Transparent top view
7 10
6 11
5 12
4 13
3 14
2 15
8
9
1
16
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
A0 1 address input
A1 2 address input
A2 3 address input
E1 4 enable input (active LOW)
E2 5 enable input (active LOW)
E3 6 enable input (active HIGH)
GND 8 ground (0 V)
Y0 to Y7 15, 14, 13, 12, 11, 10, 9, 7 output
VCC 16 supply voltage
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 4 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 °C.
[3] Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] Ptot derates linearly with 4.5 mW/K above 60 °C.
Table 3. Function table [1]
Input Output
E1 E2 E3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
HXXXXXHHHHHHHH
XHXXXXHHHHHHHH
XXLXXXHHHHHHHH
LLHLLLLHHHHHHH
LLHHLLHLHHHHHH
LLHLHLHHLHHHHH
LLHHHLHHHLHHHH
LLHLLHHHHHLHHH
LLHHLHHHHHHLHH
LLHLHHHHHHHHLH
LLHHHHHHHHHHHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
VIinput voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V [1] −20 - mA
IOK output clamping current VO<−0.5 V or VO>V
CC + 0.5 V [1] -±20 mA
IOoutput current VO = −0.5 V to (VCC + 0.5 V) - ±25 mA
ICC supply current - 75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125 °C
SO16 package [2] - 500 mW
TSSOP16 package [3] - 500 mW
DHVQFN16 package [4] - 500 mW
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 5 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74AHC138 74AHCT138 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
VIinput voltage 0 - 5.5 0 - 5.5 V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
∆t/∆V input transition rise
and fall rate VCC = 3.3 V ± 0.3 V - - 100 - - - ns/V
VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
For type 74AHC138
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage VI= VIH or VIL
IO=−50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=−50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO=−50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=−4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.4 - V
IO=−8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.7 - V
VOL LOW-level
output voltage VI= VIH or VIL
IO= 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 Vor GND;
VCC = 0 Vor 5.5 V - - 0.1 - 1.0 - 2.0 µA
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 4.0 - 40 - 80 µA
CIinput
capacitance - 3.0 10 - 10 - 10 pF
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 6 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
For type 74AHCT138
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO=−50 µA 4.4 4.5 - 4.4 - 4.4 - V
IO=−8.0 mA 3.94 - - 3.8 - 3.7 - V
VOL LOW-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 µA - 0 0.1 - 0.1 - 0.1 V
IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 Vor GND;
VCC = 0 Vor 5.5 V - - 0.1 - 1.0 - 2.0 µA
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 4.0 - 40 - 80 µA
∆ICC additional
supply current per input pin;
VI=V
CC −2.1 V; IO= 0 A;
other pins at VCC or GND;
VCC = 4.5 V to 5.5 V
- - 1.35 - 1.5 - 1.5 mA
CIinput
capacitance - 3.0 10 - 10 - 10 pF
Table 6. Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 7 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; For test circuit see Figure 8.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max Min Max
For type 74AHC138
tpd propagation
delay An to Yn; see Figure 6 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 6.0 11.4 1.0 13.0 1.0 14.5 ns
CL= 50 pF - 8.6 15.8 1.0 18.0 1.0 20.0 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 4.4 8.1 1.0 9.5 1.0 10.5 ns
CL= 50 pF - 6.3 10.1 1.0 11.5 1.0 13.0 ns
E3 to Yn; see Figure 6 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 5.8 12.8 1.0 15.0 1.0 16.0 ns
CL= 50 pF - 8.2 16.3 1.0 18.5 1.0 20.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 4.2 8.1 1.0 9.5 1.0 10.5 ns
CL= 50 pF - 6.0 10.1 1.0 11.5 1.0 13.0 ns
E1, E2 to Yn; see Figure 7 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 5.7 11.4 1.0 13.5 1.0 14.5 ns
CL= 50 pF - 8.2 14.9 1.0 17.0 1.0 19.0 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 4.2 8.1 1.0 9.5 1.0 10.5 ns
CL= 50 pF - 6.0 10.1 1.0 11.5 1.0 13.0 ns
CPD power
dissipation
capacitance
CL= 50 pF; fi = 1 MHz;
VI= GND to VCC
[4] - 18.0 - - - - - pF
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 8 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz, fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
Σ(CL×VCC2×fo) = sum of the outputs.
11. Waveforms
For type 74AHCT138
tpd propagation
delay An to Yn; see Figure 6 [2]
VCC = 4.5 V to 5.5 V
CL= 15 pF - 4.4 10.4 1.0 12.0 1.0 13.0 ns
CL= 50 pF - 6.2 11.4 1.0 13.0 1.0 14.5 ns
E3 to Yn; see Figure 6 [2]
VCC = 4.5 V to 5.5 V
CL= 15 pF - 4.3 9.1 1.0 10.5 1.0 11.5 ns
CL= 50 pF - 6.2 10.1 1.0 11.5 1.0 13.0 ns
E3 to Yn; see Figure 7 [2]
VCC = 4.5 V to 5.5 V
CL= 15 pF - 4.3 9.6 1.0 11.0 1.0 12.0 ns
CL= 50 pF - 6.2 10.6 1.0 12.0 1.0 13.5 ns
CPD power
dissipation
capacitance
CL= 50 pF; fi = 1 MHz;
VI= GND to VCC
[4] - 23.0 - - - - - pF
Table 7. Dynamic characteristics
…continued
GND = 0 V; For test circuit see Figure 8.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. The inputs An, E3 to outputs Yn propagation delays
001aah080
Yn output
VOH
VOL
VCC
GND
An, E3 input VM
tPHL tPLH
VM
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 9 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. The inputs En to outputs Yn propagation delays
001aah081
tPLH
tPHL
VM
VM
Yn output
E1, E2 input
VCC
GND
VOH
VOL
Table 8. Measurement points
Type Input Output
VMVM
74AHC138 0.5VCC 0.5VCC
74AHCT138 1.5 V 0.5VCC
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 10 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 8. Load circuit for switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
PULSE
GENERATOR
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74AHC138 VCC ≤ 3.0 ns 15 pF, 50 pF 1 kΩopen GND VCC
74AHCT138 3.0 V ≤ 3.0 ns 15 pF, 50 pF 1 kΩopen GND VCC
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 11 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
12. Package outline
Fig 9. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 12 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
Fig 10. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 13 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
Fig 11. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 14 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
LSTTL Low-power Schottky Transistor-Transistor Logic
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
CDM Charged-Device Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT138_3 20071128 Product data sheet - 74AHC_AHCT138_2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Section 3: DHVQFN16 package added.
•Section 8: derating values added for DHVQFN16 package.
•Section 12: outline drawing added for DHVQFN16 package.
74AHC_AHCT138_2 19990927 Product specification - 74AHC_AHCT138_1
74AHC_AHCT138_1 19900331 Product specification - -
74AHC_AHCT138_3 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 03 — 28 November 2007 15 of 16
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
© NXP B.V. 2007. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 November 2007
Document identifier: 74AHC_AHCT138_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
