AK4386ETP-E2 - AKM Semiconductor

[AK4386]

MS0280-E-01 2008/10

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GENERAL DESCRIPTION

The AK4386 is a 24bit low voltage & low power stereo DAC. The AK4386 uses the Advanced Multi-Bit ΔΣ

architecture, this architecture achieves DR=100dB at 3V operation. The AK4386 integrates a

combination of SCF and CTF filters increasing performance for systems with excessive clock jitter. The

AK4386 is suitable for the portable audio system like MP3 and the home audio systems like STB and TV,

etc as low power and small package. The AK4386 is offered in a space saving 16pin TSSOP package.

FEATURES

 Sampling Rate: 8kHz ∼ 96kHz

 24-Bit 8 times FIR Digital Filter

 SCF with high tolerance to clock jitter

 Single-ended output buffer

 Digital de-emphasis for 44.1kHz sampling

 I/F Format: 24-Bit MSB justified, 16/24-Bit LSB justified, I2S Compatible

 Master Clock:

512/768/1024/1536fs for Half Speed (8kHz ∼ 24kHz)

256/384/512/768fs for Normal Speed (8kHz ∼ 48kHz)

128/192/256/384fs for Double Speed (48kHz ∼ 96kHz)

 CMOS Input Level

 THD+N: −86dB

 DR, S/N: 100dB(@VDD=3.0V)

 Power Supply: 2.2 to 3.6V

 Ta = −20 ∼ 85°C (ET), −40 ∼ 85°C (VT)

 16pin TSSOP

LRCK

BICK

SDTI

Au dio

Data

Interface

MCLK

DIF1

ΔΣ

Modulator LOUT

8X

Interpolator SCF

CTF

ROUT

VDD

VSS

VCOM

De-emphasis

Control

PDN

Clock

Divider

DFS1

DFS0

ΔΣ

Modulator

8X

Interpolator SCF

CTF

DEMTES T

DIF0

100dB 96kHz 24-Bit 2ch ΔΣ DAC

AK4386

[AK4386]

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■ Ordering Guide

AK4386ET −20 ∼ +85°C 16pin TSSOP (0.65mm pitch)

AK4386VT −40 ∼ +85°C 16pin TSSOP (0.65mm pitch)

AKD4386 Evaluation Board for AK4386

■ Pin Layout

SDTI

LRCK

DFS1

DEM

MCLK

BICK

PDN

DFS0

Top View

8

7

6

5

4

3

2

1

9

10

11

12

13

14

15

16

VDD

VSS

ROUT

LOUT

VCOM

DIF1

TEST

DIF0

[AK4386]

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PIN/FUNCTION

No. Pin Name I/O Function

1 MCLK I Master Clock Input Pin

2 BICK I Audio Serial Data Clock Pin

3 SDTI I Audio Serial Data Input Pin

4 LRCK I Input Channel Cl ock Pin

5 PDN I Full Power Down Mode Pin

“L” : Power down, “H” : Power up

6 DFS0 I Sampling Speed Select 0 Pin

7 DFS1 I Sampling Speed Select 1 Pin

8 DEM I De-emphasis Filter Enable Pin

“L” : OFF, “H” : ON (De-emphasis of fs=44.1kHz is enable.)

9 DIF0 I Audio Interface Format 0 Pin

10 ROUT O Rch Analog Output Pin

11 LOUT O Lch Analog Output Pin

12 VCOM O Common Voltage Output Pin , 0.5 5 × VDD

Normally connected to VSS with a 4.7μF (min. 1μF, max. 10μF) electrolytic

capacitor.

13 VSS - Ground Pin

14 VDD - Power Supply Pi n, 2. 2 ∼ 3.6V

15 DIF1 I Audio Interface Format 1 Pin

16 TEST I TEST Pin

This pin should be connected to VDD.

Note: All digital input pins should not be left floating.

■ Handling of Unused Pin

The unused output pi ns sho uld be pr ocessed appropriatel y as below.

Classification Pin Name Setting

Analog LOUT, ROUT This pin should be open.

[AK4386]

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ABSOLUTE MAXIMUM RATINGS

(VSS=0V; Note 1)

Parameter Symbol min max Units

Power Supply VDD −0.3 4.6 V

Input Current, Any Pin Excep t Supplies IIN - ±10 mA

Digital Input Voltage VIND −0.3 VDD+0.3 V

AK4386ET Ta −20 85 °C

Ambient Temperature (Powered applied) AK4386VT Ta −40 85 °C

Storage Temperature Tstg −65 150 °C

Note 1. All voltages with respect to ground.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(VSS=0V; Note 1)

Parameter Symbol min typ max Units

Power Supply VDD 2.2 3.0 3.6 V

Note 1. All voltages with respect to ground.

WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.

[AK4386]

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ANALOG CHARACTERISTICS

(Ta=25°C; VDD=3.0V; VSS=0V; fs=44.1kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data;

Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 20Hz ∼ 40kHz at fs=96kHz; unless otherwise specified)

Parameter min typ max Units

Dynamic Characteristics:

Resolution 24 Bits

fs=44.1kHz

BW=20kHz 0dBFS

−60dBFS

−86

−37 −76

- dB

dB

THD+N

fs=96kHz

BW=40kHz 0dBFS

−60dBFS

−84

−34 -

- dB

dB

DR (−60dBFS with A-weighted) 92 100 dB

S/N (A-weighted) 92 100 dB

Intercha nnel Isolation 80 100 dB

DC Accuracy:

Intercha nnel G a i n Mi smatch 0.2 0.5 dB

Gain Drift 100 - ppm/°C

Output Voltage (Note 2) 1.85 2.0 2.15 Vpp

Load Resistance (Note 3) 10 kΩ

Load Capacitance 25 pF

Power Supplies

Power Supply Current

Normal Operation (PDN pin = “H”, fs=44.1kHz)

Normal Operation (PDN pin = “H”, fs=96kHz)

Power Save mode (PDN pin = “H”, MCLK Stop)

Full Power-down mode (PDN pin = “L”) (Note 4)

6

6.5

1.5

10

9

10

2.5

50

mA

μA

Note 2. Full-scale voltage (0dB). Output voltage scales with the voltage of VDD, Vout = 0.67 × VDD (typ).

Note 3. For AC-load.

Note 4. All dig ital input pi ns are fixed to VDD or VSS.

[AK4386]

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FILTER CHARACTERISTICS

(Ta=25°C; VDD=2.2 ∼ 3.6V; fs=44.1kHz; DEM=OFF)

Parameter Symbol min typ max Units

DAC Digital Filter:

Passband (Note 5)

±0.05dB

−6.0dB PB

0

-

22.05 20.0

- kHz

kHz

Stopband (Note 5) SB 24.1 kHz

Passband Ripple PR ±0.01 dB

Stopband Attenuation SA 64 dB

Group Delay (Note 6) GD - 24.0 - 1/fs

Digital Filter + SCF + CTF:

Frequency Response

0 ∼ 20kHz

∼ 40kHz (Note 7) FR

-

- ±0.5

±1.0 -

- dB

dB

Note 5. The passband and stopband frequencies scale with fs (system sampling rate).

Note 6. The calculating delay time which occurred by digital filtering. This time is from setting the 16 /24bit data

of both channels to input register to the output of analog signal.

Note 7. At fs=96kHz.

DC CHARACTERISTICS

(Ta=25°C; VDD=2.2 ∼ 3.6V)

Parameter Symbol min typ max Units

High-Level Input V ol t age

Low-Level Input Voltage VIH

VIL 70%VDD

- -

30%VDD V

V

Input Leakage Current Iin - - ±10 μA

[AK4386]

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SWITCHING CHARACTERISTICS

(Ta=25°C; VDD=2.2 ∼ 3.6V)

Parameter Symbol min typ max Units

Master Clock Frequency

Half Speed Mode (512/768/10 24/1536fs)

Normal Speed Mode (256/384/512/76 8fs)

Double Speed Mode (128/192/256/384fs)

Duty Cycle

fCLK

dCLK

4.096

2.048

6.144

40

36.864

60

MHz

%

LRCK Frequency

Half Speed Mode (DFS1-0 = “10”)

Normal Speed Mode (DFS1-0 = “00”)

Double Speed Mode (DFS1-0 = “01”)

Duty Cycle

fsh

fsn

fsd

dCLK

8

48

45

24

48

96

55

kHz

%

Audio Interface Timing

BICK Period

Half Speed Mode

Normal Speed Mode

Double Speed Mode

BICK Pulse Width Low

Pulse Width High

BICK “↑” to LRCK Edge (Note 8)

LRCK Edge to BICK “↑” (Note 8)

SDTI Hold Time

SDTI Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

1/128fs

1/64fs

70

40

ns

Power-Down & Reset Timing

PDN Pulse Width (Note 9)

tPD

4 × C

ms

Note 8. BICK rising edge must not occur at the same time as LRCK edge.

Note 9. The AK4386 can be reset by bringing PDN pin = “L”.

The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4 × C.

When C = 4.7μF, tPD is 19ms(min).

The value of the capacitor (C) connected with VCOM pin should be 1μF ≤ C ≤ 10μF.

When the states of DIF1-0 pins change, the AK4386 should be reset by PDN pin.

[AK4386]

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■ Timing Diagram

1/fCLK

tCLKL

VIH

tCLKH

MCLK VIL

1/fs

LRCK VIH

VIL

tBCK

tBCKL

VIH

tBCKH

BICK VIL

Clock Timing

LRCK VIH

VIL

tBLR

BICK VIH

VIL

tLRB

tSDS

SDTI VIL

tSDH

VIH

Audio Interface Timing

tPD

PDN VIL

Power Down & Reset Timing

[AK4386]

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OPERATION OVERVIEW

■ System Clock

The external clocks, which are required to operate the AK4386, are MCLK, BIC K and LRCK. The master clock (MCLK)

should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation

filter and the delta-sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK

automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 pi ns (Table 1).

The sampling s peed mode i s set dependi ng on t he MCLK fr equency automa tically for Auto m ode (D FS1 pin = DF S0 pi n

= “H”) (Table 2).

The AK4386 is automatically placed in the power save m ode when MCLK stops in t he normal operation m ode (PDN pin

= “H”), and the analog output becomes the V COM volta ge. After M CLK is i nput again, the AK438 6 is powe red up. A fter

exiting reset at power-up etc., the AK4386 is in the power-down mode until MCLK and LRCK are input.

When the states of DIF1-0 pins change in the normal operation mode, the AK4386 should be reset by PDN pin.

Mode DFS1 DFS0 fs MCLK Frequency

Normal Speed L L 8 ∼ 48kHz 256/384/512/768fs

Double Speed L H 48 ∼ 96kHz 128/192/256/384fs

Half Speed H L 8 ∼ 24kHz 512/768/1024/1536fs

Auto H H

8 ∼ 96kHz Table 2

Table 1. System Clock Exampl e

MCLK Frequency Sampling Speed Mode fs

512/768fs Normal Speed

8 ∼ 48kHz

128/192/256/384fs Double Speed

48 ∼ 96kHz

1024/1536fs Half Speed

8 ∼ 24kHz

Table 2. Auto Mode

■ Audio Interface Format

Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 pins as shown in Table 3 can select four

serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of

BICK. Mode 3 can be used for 16bit I2S Compatible format by zeroing the unused LSBs at BICK ≥ 48fs or BICK = 32fs.

Mode DIF1 DIF0 SDTI Format BICK Figure

0 L L 16bit, LSB justified ≥ 32fs Figure 1

1 L H 24bit, LSB justified ≥ 48fs Fi gu re 2

2 H L 24bit, MSB justified

≥ 48fs Figure 3

3 H H 16/24bit, I2S Compatible ≥ 48fs or 32fs Fi gu re 4

Table 3. Audio Interface Format

[AK4386]

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LRCK

BICK(32fs) 01102 3 9 1112131415 0 123 10109 1112131415

SDTI(i) Don't Care 1 0 15 14 13 21015 14 13 12 12Don't Care

SDTI-15:MSB, 0:LSB

SDTI(i) 15 14 13 7654321015 14 13 1576543210

BICK(64fs) 01182 3 19 20 31 0 1 2 3 1018 19 20 3117 17

Lch Data Rch Data

Figure 1. Mode 0 Timing

LRCK

BICK(64fs) 0 1 22431012 10312489 89

SDTI(i) Don't Care 0 8 10

23:MSB, 0:LSB

Lch Data Rch Data

23 8 Don't Care 231

Figure 2. Mode 1 Timing

LRCK

BICK(64fs) 0 1 220212431012 102220 21 312422 23 23

SDTI(i) Don't Care0 0

23:MSB, 0:LSB

Lch Data Rch Data

Don't Care

432123 22 23 22 231234

Figure 3. Mode 2 Timing

LRCK

BICK(64fs) 0122521 24 0 12 1022 2521 2422 23 233

SDTI(i) Don't Care0 0

23:MSB, 0:LSB

Lch Data Rch Data

Don't Care

432123 22 23 22 1234

Figure 4. Mode 3 Timing

[AK4386]

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■ De-emphasis Filter

The AK4386 includes the digital de-emphasis filter (tc=50/15μs) by IIR filter. This filter corresponds to 44.1kHz

sampling. The de-emphasis filter is enabled by setting DEM pin “H”. In case of Half speed and Double speed mode, the

digital de-emphasis filter is always off.

Mode DFS1 pin DFS0 pin DEM pin De-emphasis Filter

L L L OFF

Normal Speed L L H ON

Double Speed L H * OFF

Half Speed H L * OFF

H H L OFF

Auto H H H ON (Note)

Table 4. De-emephasis Filter (*: Don’ t care)

Note. The digital de-emphasis filter correspon ds to 44.1kHz sampling.

In case of Half speed and Double speed mode, the digital de-emphasis filter is always off.

■ Power-down

The AK4386 is placed in the power-down mode by bringing PDN pin = “L”. and the digital filter is reset at the sam e time.

This reset should always be done after power up.

When PDN pin = “L”, D AC outputs go to Hi-Z. Al so, the int er nal p o wer d ow n i s automati cally done when M C LK st o ps

during ope rating ( PDN pin =“H”) , and the a nalog output s go to the VC OM volt age. M CLK pi n s hould b e fixe d to “H” or

“L” when MCLK stops.

Mode PDN pin MCLK DAC Output State

0 L Don’t care Hi-Z Full Power Down

1 Supplied Normal Output Normal

2 H Not Supplied VCOM Voltage Power Save

Table 5. Power down mode

[AK4386]

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(1) Power down by PDN pin

Normal Operation

Internal

State

PDN

Power-down Normal Op eration

GD GD

“0” data

D/A Out

(Analog)

D/A In

(Digital)

Clock In

MCLK, BICK, LRCK

(2)

(4)

External

MUTE (6)

(4)

(2)

Mute ON

(3)

(5) Don’t care

(1)

Notes:

(1) PDN pi n should be “L” for 19ms or mo re when an electrolytic capacitor 4.7μF is attached between VCOM pin and

VSS.)

(2) The analog output corresponding to digital input has the group delay (GD).

(3) When PDN pin = “L”, the analog output is Hi-Z.

(4) Clic k noise occ urs in 3 ∼ 4LRC K at both ed ges (↑ ↓) of PDN signal . This noi se is out put even if “0” dat a is input .

(5) The external clocks (MCLK, BICK and LRCK) can be stopped in the power down mode (PDN pin = “L”).

(6) Please mute the analog output externally if the click noise (4) influences system application. The timing example

is shown in this figure.

Figure 5. Power-down/up sequence example 1

[AK4386]

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(2) Power save by MCLK stop (PDN pin = “H”)

Normal Operation

Internal

State Power-save Normal Operation

GD GD

D/A Out

(Analog)

D/A In

(Digital)

Clock In

MCLK, BICK, LRCK

(2)

(3)

External

MUTE (5)

VCOM

(2)

MCLK Stop

PDN pin

Power-down

(4) (4)

(4)

Hi-Z

(6) (6)

(5)

(1)

Notes:

(1) PDN pi n should be “L” fo r 19ms or m ore when an electrolytic capacitor 4.7μF is attached between VCOM pin and

VSS.)

(2) The analog output corresponding to digital input has the group delay (GD).

(3) The digital data can be stopped. The click noise after MCLK is input again by inputting the “0” data to this section

can be reduced.

(4) Clic k noise occurs i n 3 ∼ 4LRCK at both edges (↑ ↓) of PDN signal, MCLK inputs and MCLK stops. This noise is

output even if “0” data is input.

(5) The external clocks (BICK and LRCK) can be stopped in the power down mode (MCLK stop).

(6) Please mute the analog output externally if the click noise (4) influences system application. The timing example

is shown in this figure.

Figure 6. Power-down/up sequence example 2

[AK4386]

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SYSTEM DESIGN

Figure 7 shows the system connection diagram . An evaluation board is available which demonstrates application circuits,

the optimum layout, power supply arrangements and measurement results.

MCLK

1

BICK

2

SDTI

3

LRCK

4

PDN

5

DFS0

6

DFS1

7

DEM 8

TEST 16

DIF1 15

VDD 14

VSS 13

VCOM 12

LOUT 11

ROUT 10

DIF0 9

Master Clock

Mode

Setting

AK4386

fs

24bit Audio Data

Reset & Power down

64fs

4.7u

0.1u +

Rch Out

Lch Out

Analog Ground Digital Ground

A

nalog Suppl

y

2.2 to 3.6V

+

10u

(C)

Note:

- VSS of the AK43 86 shoul d be distri buted s eparately fr om the groun d of exter nal digital devices (MPU, DSP etc.).

- When AOUT drive some capacitive load, some resistor should be ad ded in series between AOUT and capacitive

load.

- The value of the capacitor connected to VCOM pin should be 1μF ≤ C ≤ 10μF.

- All digital input pins should not be left floating.

Figure 7. Typical Connection Diagram

1. Grounding and Power Supply Decoupling

The AK4386 requires car e ful attention to power supply and grounding arrangements. VDD is usually supplied from the

analog supply in the system. System analog ground and digital ground should be connected together near to where the

supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4386 as possible,

with the small value ceramic capacitor being the closest.

2. Voltage Reference

The differenti al Volta ge between VD D and VSS set s the analog o utput ra nge. VCOM is used as a com m on voltage of t he

analog signal. VCOM pin is a signal ground of this ch ip. An electrolytic capacitor about 4.7μF should be attached

between VCOM pin and VSS. No load current may be drawn from VCOM pin. Especially, the ceramic capacitor should

be connected to this pin as near as possible.

3. Analog Outputs

The analog outputs are single-ended and centered around the VCOM voltage (0.55 × VDD). The output signal range is

typically 2.0Vpp (typ@VDD=3.0V). The internal switched-capacitor filter and continuous-time filter attenuate the noise

generated by the delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for

7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage (0.55 × VDD) for

000000H (@24bit).

DC offsets on analog output s are elimi nated by AC coupling since analog outp uts have DC of fsets of VCOM + a few mV.

[AK4386]

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PACKAGE

0.1±0.1

0∼10°

Detail A

Seating Plane 0.10

0.17

±

0.05

0.22±0.1 0.65

5.0 1.10max

A

18

916

16

p

in TSSOP

(

Unit: mm

)

4.4

6.4±0.2

0.5±0.2

■ Material & Lead finish

Package molding compound: Epoxy

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

[AK4386]

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MARKING (AK4386ET)

AKM

4386ET

XXYYY

1) Pin #1 indicati on

2) Date Code : XXYYY (5 digits)

XX: Lot#

YYY: Date Code

3) Marketing Code : 4386ET

[AK4386]

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MARKING (AK4386VT)

AKM

4386VT

XXYYY

4) Pin #1 indicati on

5) Date Code : XXYYY (5 digits)

XX: Lot#

YYY: Date Code

6) Marketing Code : 4386VT

[AK4386]

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REVISION HISTORY

Date (YY/MM/DD) Revision Reason Page Contents

03/12/01 00 First edition

08/10/23 01 Spec Additio n The AK4386ET was added.

VT and ET datasheets were combined together.

IMPORTANT NOTICE

z These products and their specifications are subject to change without notice.

When you consider any use or application of these products, p lease make inquiries the sales office of Asahi Kasei

EMD Corporation (AKEMD) or authorized distributors as to current status of the products.

z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or

use of any information contained herein.

z Any export of these products, or devices or systems containing them, may require an export license or other official

approval u nde r t he l aw and regul at i o ns of the country of ex port pertaini n g t o c ust oms and tari f fs, currency exc ha nge,

or strategic materials.

z AKEMD pro ducts are neither intende d nor authorized f or use as critical component sNote1) in any safety, life support, or

other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use

approved wit h the express written consent by Representative Director of AKEMD. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,

whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and

which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or

for applications in medicine, aerospace, nuclear energy, or othe r fields, in which its failure to function or perform

may reasonably be expected to result in loss of life or in significant injury or damage to person or property.

z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise

places the product with a third pa rty, to notify suc h third party in advance of the above content and c onditions, and the

buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any

and all claims arising from the use of said product in the absence of such notification.