1. Product profile
1.1 General description
NPN/PNP double Resistor -Eq u ippe d Transistors (RET) in Surface-Mo unte d
Device (SMD) plastic packages.
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
PEMD9; PUMD9
NPN/PNP resistor-equipped transistors;
R1 = 10 k, R2 = 47 k
Rev. 6 — 22 November 2011 Product data sheet
Table 1. Product overview
Type number Package PNP/PNP
complement NPN/NPN
complement Package
configuration
NXP JEITA
PEMD9 SOT666 - PEMB9 PEMH9 ultra small and flat
lead
PUMD9 SOT363 SC-88 PUMB9 PUMH9 very small
100 mA output current capability Reduces component count
Built-in bias resistors Reduces pick and place costs
Simplifies circuit design AEC-Q101 qualified
Low current peripheral driver
Control of IC inputs
Replaces general-purpose transistors in digital applications
Table 2. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
Per transistor; for the PNP transistor (TR2) with negative polarity
VCEO collector-emitter voltage open base - - 50 V
IOoutput current - - 100 mA
R1 bias resistor 1 (input) 7 10 13 k
R2/R1 bias resistor ratio 3.7 4.7 5.7
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 2 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
2. Pinning information
3. Ordering information
4. Marking
[1] * = placeholder for manufacturing site code
Table 3. Pinning
Pin Description Simplified outline Graphic symbol
1 GND (emitter) TR1
2 input (base) TR1
3 output (collector) TR2
4 GND (emitter) TR2
5 input (base) TR2
6 output (collector) TR1
001aab555
6 45
1 32
65 4
123
R2
TR1 TR2
R1
R2 R1
006aaa143
Table 4. Orderin g information
Type number Package
Name Description Version
PEMD9 - plastic surface-mounted package; 6 leads SOT666
PUMD9 SC-88 plastic surface-mounted package; 6 leads SOT363
Table 5. Marking codes
Type number Marking code[1]
PEMD9 D9
PUMD9 D*9
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 3 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
5. Limiting values
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[2] Reflow soldering is the only recommended soldering method.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor; for the PNP transistor (TR2) with negative polarity
VCBO collector-base voltage open emitter - 50 V
VCEO collector-emitter voltage open base - 50 V
VEBO emitter-base voltage open collector - 6 V
VIinput voltage TR1
positive - +40 V
negative - 6V
input voltage TR2
positive - +6 V
negative - 40 V
IOoutput current - 100 mA
ICM peak collector current single pulse;
tp1ms -100mA
Ptot total power dissipation Tamb 25 C
PEMD9 (SOT666) [1][2] -200mW
PUMD9 (SOT363) [1] -200mW
Per device
Ptot total power dissipation Tamb 25 C
PEMD9 (SOT666) [1][2] -300mW
PUMD9 (SOT363) [1] -300mW
Tjjunction temperature - 150 C
Tamb ambient temperature 65 +150 C
Tstg storage temperature 65 +150 C
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 4 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
6. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Reflow soldering is the only recommended soldering method.
FR4 PCB, standard footprint
Fig 1. Per device: Power derating curve for SOT363 (SC-88) and SOT666
Tamb (°C)
-75 17512525 75-25
006aac749
200
100
300
400
Ptot
(mW)
0
Table 7. Thermal characteris tics
Symbol Parameter Conditions Min Typ Max Unit
Per transis tor
Rth(j-a) thermal resistance from
junction to ambient in free air
PEMD9 (SOT666) [1][2] - - 625 K/W
PUMD9 (SOT363) [1] - - 625 K/W
Per device
Rth(j-a) thermal resistance from
junction to ambient in free air
PEMD9 (SOT666) [1][2] - - 417 K/W
PUMD9 (SOT363) [1] - - 417 K/W
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 5 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
FR4 PCB, standard footprint
Fig 2. Per transistor: T ransient thermal impedance from junction to ambient as a function of pulse duration for
PEMD9 (SOT666); typical values
FR4 PCB, standard footprint
Fig 3. Per transistor: T ransient thermal impedance from junction to ambient as a function of pulse duration for
PUMD9 (SOT363); typical values
006aac751
10-5 1010-2
10-4 102
10-1 tp (s)
10-3 103
1
102
10
103
Zth(j-a)
(K/W)
1
duty cycle = 1
0.75 0.5
0.33 0.2
0.1
0.05
0.02 0.01
0
006aac750
10-5 1010-2
10-4 102
10-1 tp (s)
10-3 103
1
102
10
103
Zth(j-a)
(K/W)
1
duty cycle = 1
0.75 0.5
0.33
0.2
0.1 0.05
0.02 0.01
0
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 6 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
7. Characteristics
[1] Characteristics of built-in transistor
Table 8. Characteristics
Tamb =25
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per transistor; for the PNP transistor (TR2) with negative polarity
ICBO collector-base cut-off
current VCB =50V; I
E= 0 A - - 100 nA
ICEO collector-emitter cut-off
current VCE =30V; I
B=0A - - 1 A
VCE =30V; I
B=0A;
Tj= 150 C--5A
IEBO emitter-base cut-off
current VEB =5V; I
C=0A - - 150 A
hFE DC current gain VCE =5V; I
C= 5 mA 100 - -
VCEsat collector-emitter
saturation voltage IC=5mA; I
B=0.25mA - - 100 mV
VI(off) off-state input voltage VCE =5V; I
C= 100 A- 0.70.5V
VI(on) on-state input voltage VCE =0.3V; I
C=1mA 1.4 0.8 - V
R1 bias resistor 1 (input) 7 10 13 k
R2/R1 bias resistor ratio 3.7 4.7 5.7
Cccollector capacitance VCB =10V; I
E=i
e=0A;
f=1MHz
TR1 (NPN) - - 2.5 pF
TR2 (PNP) - - 3 pF
fTtransition frequency VCE =5V; I
C=10mA;
f=100MHz [1]
TR1 (NPN) - 230 - MHz
TR2 (PNP) - 180 - MHz
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 7 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
VCE =5V
(1) Tamb = 100 C
(2) Tamb =25C
(3) Tamb =40 C
IC/IB=20
(1) Tamb = 100 C
(2) Tamb =25C
(3) Tamb =40 C
Fig 4. TR1 (NPN): DC current gain as a function of
collector current; typical valu es Fig 5. TR1 (NPN): Collector-emitter saturation
voltage as a function of collector cur r e nt;
typical values
VCE =0.3V
(1) Tamb =40 C
(2) Tamb =25C
(3) Tamb = 100 C
VCE =5V
(1) Tamb =40 C
(2) Tamb =25C
(3) Tamb = 100 C
Fig 6. TR1 (NPN): On-state input voltage as a
function of collector current; typical values Fig 7. TR1 (NPN): Off-state input voltage as a
function of collector current; typical values
IC (mA)
10-1 102
101
006aac784
102
10
103
hFE
1
(1)
(2)
(3)
006aac785
IC (mA)
10-1 102
101
10-1
1
VCEsat
(V)
10-2
(1)
(2)
(3)
006aac786
IC (mA)
10-1 102
101
1
10
VI(on)
(V)
10-1
(1)
(2)
(3)
IC (mA)
10-1 101
006aac787
1
10
VI(off)
(V)
10-1
(1)
(2)
(3)
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 8 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
f=1MHz; T
amb =25CV
CE =5V; T
amb =25C
Fig 8. TR1 (NPN): Collector capacitance as a function
of collector-base voltage; typical values Fig 9. TR1 (NPN): Transition frequency as a function
of collector current; typical values of built-in
transistor
VCE =5V
(1) Tamb = 100 C
(2) Tamb =25C
(3) Tamb =40 C
IC/IB=20
(1) Tamb = 100 C
(2) Tamb =25C
(3) Tamb =40 C
Fig 10. TR2 (PNP): DC current gain as a function of
collector current; typical valu es Fig 11. TR2 (PNP): Collector-emitter saturation
voltage as a function of collector cur r e nt;
typical values
VCB (V)
0504020 3010
006aac788
1
2
3
Cc
(pF)
0
006aac757
IC (mA)
10-1 102
101
102
103
fT
(MHz)
10
IC (mA)
-10-1 -102
-10-1
006aac789
102
10
103
hFE
1
(1)
(2)
(3)
006aac790
IC (mA)
-10-1 -102
-10-1
-10-1
-1
VCEsat
(V)
-10-2
(1)
(2)
(3)
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 9 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
VCE =0.3 V
(1) Tamb =40 C
(2) Tamb =25C
(3) Tamb = 100 C
VCE =5V
(1) Tamb =40 C
(2) Tamb =25C
(3) Tamb = 100 C
Fig 12. TR2 (PNP): On-state input voltage as a
function of collector current; typical values Fig 13. TR2 (PNP): Off-st ate input voltage as a
function of collector current; typical values
f=1MHz; T
amb =25CV
CE =5V; T
amb =25C
Fig 14. TR2 (PNP): Collector ca pacit ance as a f unction
of collector-base voltage; typical values Fig 15. TR2 (PNP): Transition freque nc y as a function
of collector current; typical values of built-in
transistor
006aac791
IC (mA)
-10-1 -102
-10-1
-1
-10
VI(on)
(V)
-10-1
(1)
(2)
(3)
IC (mA)
-10-1 -10-1
006aac792
-1
-10
VI(off)
(V)
-10-1
(1)
(2)
(3)
VCB (V)
0 -50-40-20 -30-10
006aac793
7
Cc
(pF)
5
3
1
0
2
4
6
006aac763
IC (mA)
-10-1 -102
-10-1
102
103
fT
(MHz)
10
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 10 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
8. Test information
8.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
9. Package outline
10. Packing information
[1] For further information and the availability of packing methods, see Section 14.
[2] T1: normal taping
[3] T2: reverse taping
Fig 16. Packag e outline PEMD9 (SOT666) Fig 17. Package outline PUMD9 (SOT363)
Dimensions in mm 04-11-08
1.7
1.5
1.7
1.5
1.3
1.1
1
0.18
0.08
0.27
0.17
0.5
pin 1 index
123
456
0.6
0.5
0.3
0.1
06-03-16Dimensions in mm
0.25
0.10
0.3
0.2
pin 1
index
1.3
0.65
2.2
2.0 1.35
1.15
2.2
1.8 1.1
0.8
0.45
0.15
132
465
Table 9. Packing methods
The indicated -xxx are the last thre e digits of the 12NC ordering code.[1]
Type
number Package Description Packing quantity
3000 4000 8000 10000
PEMD9 SOT666 2 mm pitch, 8 mm tape and reel - - -315 -
4 mm pitch, 8 mm tape and reel - -115 - -
PUMD9 SOT363 4 mm pitch, 8 mm tape and reel; T1 [2] -115 - - -135
4 mm pitch, 8 mm tape and reel; T2 [3] -125 - - -165
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 11 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
11. Soldering
Reflow soldering is the only recommended soldering method.
Fig 18. Reflow soldering footprint PEMD9 (SOT666)
solder lands
placement area
occupied area
solder paste
sot666_fr
2.75
2.45
2.1
1.6
0.4
(6×)
0.55
(2×)
0.25
(2×)
0.6
(2×)
0.65
(2×)
0.3
(2×)
0.325
(4×)
0.45
(4×)
0.5
(4×)
0.375
(4×)
1.72
1.7
1.0750.538
Dimensions in mm
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 12 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
Fig 19. Reflow soldering footprint PUMD9 (SOT363)
Fig 20. Wave soldering footprint PUMD9 (SOT363)
solder lands
solder resist
occupied area
solder paste
sot363_fr
2.65
2.35 0.4 (2×)
0.6
(2×)
0.5
(4×)
0.5
(4×)
0.6
(4×)
0.6
(4×)
1.5
1.8
Dimensions in mm
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 13 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
12. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PEMD9_PUMD9 v.6 20111122 Product data sheet - PEMD9_PUMD9 v.5
Modifications: •The format of this document has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Section 1 “Product profile”: updated
•Section 4 “Marking”: updated
•Figure 1 to 15: added
•Section 5 “Limiting values”: updated
•Section 6 “Thermal characteristics”: updated
•Table 8 “Characteristics”: Vi(on) redefined to VI(on) on-state input voltage, Vi(off) redefined to
VI(off) off-state input voltage, ICEO updated, fT added
•Section 8 “Test information”: added
•Section 9 “Package outline”: superse ded by minimized package outline drawings
•Section 10 “Packing information”: added
•Section 11 “Soldering”: added
•Section 13 “Legal information”: updated
PEMD9_PUMD9 v.5 20040415 Product data sheet - PEMD9_PUMD9 v.4
PEMD9_PUMD9 v.4 20031104 Product specification - PEMD9 v.2
PUMD9 v.3
PEMD9 v.2 20020905 Product specification - PEMD9 v.1
PEMD9 v.1 20011022 Preliminary specification - -
PUMD9 v.3 20010216 Product specification - PUMD9 v.2
PUMD9 v.2 19990520 Product specification - PUMD9 v.1
PUMD9 v.1 19990107 Product specification - -
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 14 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
13. Legal information
13.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full dat a sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
13.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
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profits, lost savings, business interruption, costs related to the removal or
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Notwithstanding any damages that customer might incur for any reason
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customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
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authorized or warranted to be suit able for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or envi ronmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability rela ted to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the applica tion or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
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products are sold subject to the general terms and conditions of commercial
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applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
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Export control — This document as well as the item(s) described herein
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
PEMD9_PUMD9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 22 November 2011 15 of 16
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
13.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PEMD9; PUMD9
NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 47 k
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 22 Novem ber 2011
Document identifier: PEMD9_PUMD9
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
15. Contents
1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Thermal characteristics . . . . . . . . . . . . . . . . . . 4
7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Test information. . . . . . . . . . . . . . . . . . . . . . . . 10
8.1 Quality information . . . . . . . . . . . . . . . . . . . . . 10
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
10 Packing information . . . . . . . . . . . . . . . . . . . . 10
11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
14 Contact information. . . . . . . . . . . . . . . . . . . . . 15
15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16