July 2013
©2011 Fairchild Semiconductor Corporation
FDMC8030 Rev.C1 www.fairchildsemi.com
1
FDMC8030 Dual N-Channel Power Trench® MOSFET
FDMC8030
Dual N-Channel Power Trench® MOSFET
40 V, 12 A, 10 mΩ
Features
Max rDS(on) = 10 mΩ at VGS = 10 V, ID = 12 A
Max rDS(on) = 14 mΩ at VGS = 4.5 V, ID = 10 A
Max rDS(on) = 28 mΩ at VGS = 3.2 V, ID = 4 A
Termination is Lead-free and RoHS Compliant
General Description
This device includes two 40V N-Channel MOSFETs in a dual
Power 33 (3 mm X 3 mm MLP) package. The package is
enhanced for exceptional thermal performance.
Applications
Battery Protection
Load Switching
Point of Load
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage 40 V
VGS Gate to Source V oltage (Note 4) ±12 V
IDDrain Current -Continuous TA = 25 °C (Note 1a) 12 A
-Pulsed 50
EAS Single Pulse Avalanche Energy (Note 3) 21 mJ
PDPower Dissipation TA = 25 °C (Note 1a) 1.9 W
Power Dissipation TA = 25 °C (Note 1b) 0.8
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 65 °C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1b) 155
Device Marking Device Package Reel Size Tape Width Quantity
FDMC8030 FDMC8030 Power 33 13 ’’ 12 mm 3000 units
D1
D2
S1
G1
S2
G2
Power 33
Pin 1 S1S1
S2S2
G2
S2
G1
S1
S2
S2
S1
S1
4
3
2
18
7
6
5Bottom Drain1 Contact
Bot tom D r a in2 Cont ac t
Q2
Q1
FDMC8030 Dual N-Channel Power Trench® MOSFET
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©2011 Fairchild Semiconductor Corporation
FDMC8030 Rev.C1
Electrical Characteristics TJ = 25 °C unless otherwise noted
Off Characteristics
On Characteristic s
Dynamic Characterist ic s
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 40 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C 19 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V 1 μA
IGSS Gate to Source Leakage Current, Forward VGS = 12 V, VDS = 0 V 100 nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 1.0 1.5 2.8 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C -5 mV/°C
rDS(on) Static Drain to Source On Resistance
VGS = 10 V, ID = 12 A 8 10
mΩ
VGS = 4.5 V, ID = 10 A 10 14
VGS = 3.2 V, ID = 4 A 19 28
VGS = 10 V, ID = 12 A
TJ = 125 °C 13 16
gFS Forward Transconductance VDD = 5 V, ID = 12 A 57 S
Ciss Input Capacitance VDS = 20 V, VGS = 0 V
f = 1MHz
1462 1975 pF
Coss Output Capacitance 321 430 pF
Crss Reverse Transfer Capacitance 20 30 pF
RgGate Resistance 0.9 2.5 Ω
td(on) Turn-On Delay Time VDD = 20 V, ID = 12 A
VGS = 10 V, RGEN = 6 Ω
713ns
trRise Time 310ns
td(off) Turn-Off Delay Time 19 33 ns
tfFall Time 310ns
Qg(TOT) Total Gate Charge VGS = 0 V to 10 V VDD = 20 V
ID = 12 A
21 30 nC
Total Gate Charge VGS = 0 V to 5 V 12 17 nC
Qgs Gate to Source Charge 2.8 nC
Qgd Gate to Drain “Miller” Charge 2.5 nC
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 12 A (Note 2) 0.83 1.2 V
trr Reverse Recovery Time IF = 12 A, di/dt = 100 A/μs 25 40 ns
Qrr Reverse Recovery Charge 9 18 nC
NOTES:
1. RθJA is determine d with the de vice mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. EAS of 21 mJ is based on starting TJ = 25 oC, L = 0.3 mH, IAS = 12 A, VDD = 36 V, VGS = 10 V. 100% tested at L = 3 mH, IAS = 5 A.
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurence only. No continuous rating is implied.
a. 65 °C/W when mounted on
a 1 in2 pad of 2 oz copper b.155 °C/W when mounted on
a minimum pad of 2 oz copper
FDMC8030 Dual N-Channel Power Trench® MOSFET
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©2011 Fairchild Semiconductor Corporation
FDMC8030 Rev.C1
Typical Characteristics TJ = 25°C unless otherwise noted
Figure 1.
012345
0
10
20
30
40
50
VGS = 3 V
VGS = 10 V
VGS = 3.5 V
PULSE DURATION = 80μs
DUTY CYCLE = 0.5%MAX
VGS = 4.5 V
VGS = 3.2 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VO LTA GE (V)
On-Region Characteristics Figure 2.
0 1020304050
0
1
2
3
4
5
VGS = 10 V
PULSE DURATION = 80μs
DUTY CYCLE = 0.5%MAX
NORMALIZED
DRAIN TO SOU RC E ON-RESISTA NC E
ID, DRAIN CURRENT(A)
VGS = 3.5 V
VGS =3.2 V
VGS = 3 V
VGS = 4.5 V
Normalized On-Resistance
vs Drain Current and Gate Voltage
Figure 3. Normalized On- Resistance
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
ID = 12 A
VGS = 10 V
NORMALIZED
DRAIN TO SO UR CE ON-RESIST AN C E
TJ, JUNCTION TEMPERATURE (oC)
vs Junction Te mperature Figure 4.
246810
0
5
10
15
20
25
30
ID = 12 A
TJ = 25 oC
TJ = 125 oC
VGS, G ATE TO SOURCE VOLTAGE (V)
rDS(on), DRAIN T O
SOURCE ON-RESISTANCE (mΩ)
PULSE D U RATION = 80μs
DUTY CYCLE = 0.5%MAX
On-Resistance vs Gate to
Source Voltage
Figure 5. Transfer Characteristics
1234
0
10
20
30
40
50
TJ = 25 oC
TJ = -55 oC
VDS = 5 V
PULSE DURATION = 80μs
DUTY CYCLE = 0.5%MAX
TJ = 150 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
50
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Source to Drain Diode
Forward Voltage vs Source Current
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©2011 Fairchild Semiconductor Corporation
FDMC8030 Rev.C1
Figure 7.
0 5 10 15 20
0
2
4
6
8
10 ID = 12 A
VDD = 15 V
VDD = 20 V
VGS, GATE TO SOURCE VOLTAGE(V)
Qg, GATE CHARGE(nC)
VDD = 25 V
Gate Charge Characteristics Figure 8.
0.1 1 10 40
1
10
100
1000
2000
f = 1 M H z
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Capacitance vs Drain
to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 20
1
10
30
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE(ms)
IAS, AVALANCHE CURRENT(A)
Uncl a mped I nduc t ive
Switching Capability Figure 10.
0.01 0.1 1 10 100200
0.01
0.1
1
10
60
100 μs
10 ms
10 s
100 ms
DC
1 s
1 ms
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AR EA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJA = 155 oC/W
TA = 25 oC
Forward Bias Safe
Operating Area
Figure 11. Single Pulse Maximum Power Dissipation
10-4 10-3 10-2 10-1 110
100 1000
0.1
1
10
100
1000
P(PK), PEAK T RANSIENT POWER ( W )
SINGLE PULSE
RθJA = 155 oC/W
TA = 25 oC
t, PULSE WIDTH (sec)
Typical Characteristics TJ = 25°C unless otherwise noted
FDMC8030 Dual N-Channel Power Trench® MOSFET
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©2011 Fairchild Semiconductor Corporation
FDMC8030 Rev.C1
Figure 12. Junction-to-Ambient Transient Thermal Response Curve
10-4 10-3 10-2 10-1 110
100 1000
0.001
0.01
0.1
1
SINGLE PULSE
RθJA = 155 oC/W
DUTY CYC L E-DESC ENDING O RD ER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.0 5
0.0 2
0.0 1
2
PDM
t1t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
Typical Characteristics TJ = 25°C unless otherwise noted
FDMC8030 Dual N-Channel Power Trench® MOSFET
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©2011 Fairchild Semiconductor Corporation
FDMC8030 Rev.C1
Dimensional Outline and Pad Layout
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FDMC8030 Dual N-Channel Power Trench® MOSFET
©2011 Fairchild Semiconductor Corporation
FDMC8030 Rev.C1 7
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