Rev. 4202E–SCR–06/06
1
Features
•Clock Controller
– 80 C51 core wit h 6 clocks per inst ructi on
– 8 MHz On-Chip Oscillator
– PLL for generating clock to supply CPU core, USB and Smart Card Interfaces
– Programmabl e CPU clock from 500 KHz / X1 to 48 MHz / X1
•Reset Controller
– Powe r On Reset (POR) featur e avoiding an external reset capacitor
– Power Fail Detector (PFD)
– Wa tch-Dog T imer
•Power Managem ent
– Two power saving modes : Idle and Power Down
– Four Power Down W ake-u p Sources : Smart Card Detect ion, Keyboard Interrupt, USB
Resume, External Interrupt
– Input Voltage Range : 3.0V - 5. 5V
– Core’s Power Consumption (Without Smart Card and USB) :
•30 mA Maximum Ope rat ing Current @ 48 MHz / X1
•200 μA Maxim um Power-down Current @ 5.5V
•Interrupt Control ler
– up to 9 interrupt sources
– u p to 4 Lev e l Prio rity
•Memory Controller
– Int ernal Program memory :
•up to 32K B of Flash or CRAM or ROM for AT8xC5122
•up to 30K B of ROM for AT83C512 3
– Internal Dat a M em ory : 768 bytes in cluding 256 bytes of data and 512 byt es of XRAM
– Optional : internal data E2PROM 512 bytes
•Two 16-bit Timer/Counters
•USB 2.0 Full Speed Interface
–48 MHz DPLL
– On-Chip 3.3V USB volt age regulator and trans ceivers
– Software detach featur e
– 7 endpoints program m able with In or out direct ions and ISO, Bulk or Int errupt Tr ansfers :
•Endpoint 0: 32 Bytes Bidirectionnal FIFO for Control transfers
•Endpoints 1,2,3: 8 bytes FIFO
•Endpoints 4,5: 64 Bytes FIFO
•Endpoint 6: 2*64 bytes FIFO wit h Pin- Pong feature
•ISO 7816 UART Interface Fully Compliant with EMV, GIE-CB and WHQL Standards
– Programmable ISO clock f rom 1 M Hz to 4.8 MHz
– Card insertion/remov al detection with automatic dea cti vation sequence
– Programmable Baud Rate Generator from 372 to 11.625 clock pulses
– Synchronous/Asynchronous Protocols T=0 and T=1 with Direct or Inverse Convention
– Automatic character repetition on parity errors
– 32 Bit Wa it in g Tim e Count e r
– 16 Bit Guard Time Counter
– Internal Step Up/Down Converter with Programmable Voltage Output:
•VCC = 4.0V to 5.5V, 1.8V-30 mA , 3V-60 mA and 5V-60 mA
•VCC = 3.0V, 1.8V-30 mA, 3V -30 mA and 5V-30 mA
– Current overload prote ction
– 6 kV ESD (MIL/STD 833 Class 3) protection on whole Smart Car d Int erf ace
•Alternate Smart Car d Interface with CLK, IO and RST
•UART Inter face w ith I ntegrated Baud Rate Gener ator (BRG)
•Keyboard interface with up to 20x8 m atrix management capability
•Master/Slave SPI Inte rface
•Four 8 bit Ports, one 6 bit port, one 3-b it port
– Up to Seven LED outputs with 3 level programmable current source : 2, 4 and 10 mA
– Two General Purpose I/ O programmable as external i nterrupts
– Up to 8 input l ines programmable as interrupts
– Up to 30 ou tp ut lines
C51
Microcontroller
with USB and
Smart Card
Reader
Interfaces
AT83C5122
AT83EC5122
AT85C5122
AT89C5122
AT89C5122DS
AT83C5123
AT83EC5123
2
AT8xC5122/23
4202E–SCR–06/06
Reference Documents The user must get the following addit ionnal documents which are not included but which
comple te this product datas heet
• Product Errata Sheet
• Bootloader Datasheet
3
AT8xC5122/23
4202E–SCR–06/06
Pr oduct Description AT8xC5122/23 product s are high-performance CMOS derivatives of the 80C51 8-bit
microcont rollers designe d for U SB smart card reader applications.
The AT8x C5122 is proposed in four versions :
- R OM ve rsion w ith or wi thou t int erna l data E 2PROM . The RO M dev ice is on ly fa ctory
programmable.
- CR AM version withou t interna l data E2PR OM. The CRAM dev ice impl ements a v ola-
tile program memory which is programmed by means of an embedded ROMed
bootloader which transfer s the code from a remote software programming tool called
FLIP through UAR T or USB interfaces.
- Flash version without internal data E2PROM. At power-up, the program loca ted in the
flash memo ry is transferred into the CRAM then executed.
The A T83C512 3 is a low pin count of the AT 8xC5122 and is propos ed in ROM version
with or without internal data E2PROM . The ROM device is only factory programmable.
The AT8xC5122DS is a secure version of the AT8xC5122 on which the external pro-
gram me mory access m ode is disabled.
4
AT8xC5122/23
4202E–SCR–06/06
Note: The PLCC28 pinout i s com mon to AT8xC5122 and AT83C5123 products
Table 1. Product versions
Features AT83C5122 AT83EC5122 AT85C5122 AT89C5122 AT89C5122DS AT83C5123 AT83EC5123
Packages
VQFP64
QFN64
PLCC28
Die Form
VQFP64
PLCC28
PLCC68
VQFP64
PLCC28
Die Form
VQFP64
QFN64
PLCC28
VQFP64
QFN64
VQFP32
QFN32
PLCC28
Die Form
QFN32
VQFP32
PLCC28
Program memory 32KB ROM 30KB ROM 32KB CRAM 32KB
E2PROM 32KB E2PROM 30KB ROM 30KB ROM
Internal Data E2PROM No 512 Bytes No No No No 512 Bytes
Embedded bootloader No No Yes Yes Yes No No
Features
VQFP32,
QFN32
packages
Features not available :
- Keyboa rd Interface
- Master/Slave SPI
Interface
- External Program Memory
Access
Reduced features :
- Only 12 I/O with up to 4
LED Outputs with
Program mable Current
PLCC68,
VQFP64,QFN64
packages
All fea tures are available
All features are
available
except External
Pr ogram Mem ory
Access
PLCC28 package
Featur e s not avai lab le :
- Alternat e Smart C ard Inte rfa ce
- Keyboard Interface
- Master/Slave SPI Interface
- External Program Mem ory Access
Red uced features :
- Only 7 I/O with up to 4 LED Outputs with Programmable Current
5
AT8xC5122/23
4202E–SCR–06/06
AT8 xC 5122 Block Diagram
AT8 3C 5123 Block Diagram
DC/DC
Converter
LI
CVCC
CVSS
UART
Interface
TxD
RxD
16-BIT
TIMERS
T[0-1]
Interrupt
Controller
INT[0-1]
Alternate
Card
CRST1
CCLK1
CIO1
3.3 V
Regulator
VCC
VSS
WATCH-DOG
POR
PFD
RESET
RST
PLLPLLF
XTAL1
XTAL2 8 M Hz
Oscillator 256 x 8
RAM 512 x 8
XRAM
80C51 8-BIT CORE
256 x 8
RAM
INTERNAL ADDRESS AND DATA BUS
32K x 8
ROM (1) 32K x 8
E2PROM (1)
32K x 8
CRAM (1) External Memory
Controller
EA
PSEN
ALE
A[8-15]
AD[0-7]
WR
RD
D+
D-
VREF
USB
Interface
ISO 7816
Interface
CCLK
CRST
CPRES
CC8
CC4
CIO
3.3V
Regulator
AVSS
AVCC
DVCC
Note 1 : the implementation of these features depends on product versions
512 x 8
E2PROM (1)
Parallel I/O Ports
P0[0-7]
8-BIT
PORT 8-BIT
PORT
P2[0-7]
8-BIT
PORT
P3[0-7]
6-BIT
PORT
P4[0-5]
8-BIT
PORT
P5[0-7]
LED's
LED[0-6]
3-BIT
PORT
P1[2,6-7]
SPI
Interface
MISO
MOSI
SCK
SS
KBD
Interface
KB[0-7]
DC/DC
Converter
LI
CVCC
CVSS
UART
Interface
TxD
RxD
16-BIT
TIMERS
T[0-1]
Interrupt
Controller
INT[0-1]
Alternate
Card
CRST1
CCLK1
CIO1
3.3 V
Regulator
VCC
VSS
WATCH-DOG
POR
PFD
RESET
RST
PLLPLLF
XTAL1
XTAL2 8 MHz
Oscillator 256 x 8
RAM 512 x 8
XRAM
80C51 8-BIT CORE
256 x 8
RAM
INTERNAL ADDRESS AND DATA BUS
30K x 8
ROM 512 x 8
E2PROM (1)
Parallel I/O Ports
8-BIT
PORT
P3[0-7]
D+
D-
VREF
USB
Interface
ISO 7816
Interface
CCLK
CRST
CPRES
CC8
CC4
CIO
3.3V
Regulator
AVSS
AVCC
DVCC
Note 1 : the implementation of these features depe nds on p rodu ct versions
1-BIT
PORT
P5.0
LED's
LED[0-3]
3-BIT
PORT
P1[2,6-7]
6
AT8xC5122/23
4202E–SCR–06/06
Pinout
High Pin Count Package
Description
AT8xC5122 version Figure 1. VQFP64 Package Pinout
62 61 60 59 58 63
57
56 55 54 53
P0.1/AD1
P0.3/AD3
P0.5/AD5
P0.7/AD7 D+
P4.1/MOSI
P4.0/MISO
P4.2/SCK
P4.5/LED6
P3.1/TxD
P4.3/LED4
P4.4/LED5
P3.6/WR/LED2
D-
XTAL1
XTAL2 P2.5/A13
P2.4/A12
P2.2/A10
P2.1/A9
P2.0/A8
CRST
CCLK
LI
P2.3/A11
2
3
4
5
6
7
8
9
10
11
48
47
46
45
44
43
42
41
40
39
38
VQFP64
64 52
12
13 36
37
VCC
VSS
P5.0/KB0
P3.7/RD/LED3
51 50
AVSS
49
AVCC
P3.3/INT1
35
33
34
P3.4/T0/LED1
P3.5/T1/CRST1
CVCC
14
15
16
CVSS
31 32
P0.0/AD0
P1.2/CPRES
P0.2/AD2
P0.4/AD4
P0.6/AD6
P1.6/SS
P2.7/A15
P2.6/A14
P1.7/CCLK1
P5.1/KB1
P5.2/KB2
P5.3/KB3
P5.4/KB4
P5.5/KB5
P5.6/KB6
P5.7/KB7
P3.2/INT0/LED0/CIO1
CC4
PLLF
ALE
PSEN
DVCC
CC8
CIO
P3.0/RxD
1
30 29 28 27 26 25 24 23 22 21 20 19 18 17
VREF
EA
RST
7
AT8xC5122/23
4202E–SCR–06/06
Fi gure 2. PLCC68 Package Pinout (for engineering purpose only)
18
17
16
15
14
13
11
P0.1/AD1
P0.3/AD3
P0.5/AD5
P0.7/AD7
D+
P4.1/MOSI
P4.0/MISO
P4.2/SCK
P4.5/LED6
CC8
P4.3/LED4
P4.4/LED5
P3.6/WR/LED2
D-
XTAL2
XTAT1 P2.5/A13
P2.4/A12
P2.2/A10
P2.1/A9
P2.0/A8
P3.1/TxD
CCLK
LI
P2.3/A11
PLCC68
VCC
VSS
P5.0/KB0
P3.7/RD/LED3 AVSS
AVCC
P3.3/INT1
P3.4/T0/LED1
P3.5/T1/CRST1
CVCC
CVSS
CIO
P0.0/AD0
P3.0/RxD
P0.2/AD2
P0.4/AD4
P0.6/AD6
P1.6/SS
P2.7/A15
P2.6/A14
P1.7/CCLK1
P5.1/KB1
P5.3/KB3
P5.4/KB4
P5.5/KB5
P5.6/KB6
P5.7/KB7
P3.2/INT0/LED0/CIO1
VREF
CC4
PLLF
ALE
PSEN
DVCC
P1.2/CPRES
CRST
N/A
N/A
16867
66 65 64 63 62 6123456789
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
12
19
20
21
22
24
25
26 35 36 37 38 39 40 41 42 433433323130292827
23
NC
NC
EA
RST
P5.2/KB2
NC : not connected
N/A : not available
8
AT8xC5122/23
4202E–SCR–06/06
Fi gure 3. QFN64 P acka ge Pinout
62 61 60 59 58 63
57
56 55 54 53
P0.1/AD1
P0.3/AD3
P0.5/AD5
P0.7/AD7 D+
P4.1/MOSI
P4.0/MISO
P4.2/SCK
P4.5/LED6
P3.1/TxD
P4.3/LED4
P4.4/LED5
P3.6/WR/LED2
D-
XTAL1
XTAL2 P2.5/A13
P2.4/A12
P2.2/A10
P2.1/A9
P2.0/A8
CRST
CCLK
LI
P2.3/A11
2
3
4
5
6
7
8
9
10
11
48
47
46
45
44
43
42
41
40
39
38
QFN64
64 52
12
13 36
37
VCC
VSS
P5.0/KB0
P3.7/RD/LED3
51 50
AVSS
49
AVCC
P3.3/INT1
35
33
34
P3.4/T0/LED1
P3.5/T1/CRST1
CVCC
14
15
16
CVSS
31 32
P0.0/AD0
P1.2/CPRES
P0.2/AD2
P0.4/AD4
P0.6/AD6
P1.6/SS
P2.7/A15
P2.6/A14
P1.7/CCLK1
P5.1/KB1
P5.2/KB2
P5.3/KB3
P5.4/KB4
P5.5/KB5
P5.6/KB6
P5.7/KB7
P3.2/INT0/LED0/CIO1
CC4
PLLF
ALE
PSEN
DVCC
CC8
CIO
P3.0/RxD
1
30 29 28 27 26 25 24 23 22 21 20 19 18 17
VREF
EA
RST
9
AT8xC5122/23
4202E–SCR–06/06
AT89C5122DS version Fi gure 4. VQFP64 Package Pinout
62 61 60 59 58 63
57
56 55 54 53
P0.1/AD1
P0.3/AD3
P0.5/AD5
P0.7/AD7 D+
P4.1/MOSI
P4.0/MISO
P4.2/SCK
P4.5/LED6
P3.1/TxD
P4.3/LED4
P4.4/LED5
P3.6/WR/LED2
D-
XTAL1
XTAL2 P2.5/A13
P2.4/A12
P2.2/A10
P2.1/A9
P2.0/A8
CRST
CCLK
LI
P2.3/A11
2
3
4
5
6
7
8
9
10
11
48
47
46
45
44
43
42
41
40
39
38
VQFP64
64 52
12
13 36
37
VCC
VSS
P5.0/KB0
P3.7/RD/LED3
51 50
AVSS
49
AVCC
P3.3/INT1
35
33
34
P3.4/T0/LED1
P3.5/T1/CRST1
CVCC
14
15
16
CVSS
31 32
P0.0/AD0
P1.2/CPRES
P0.2/AD2
P0.4/AD4
P0.6/AD6
P1.6/SS
P2.7/A15
P2.6/A14
P1.7/CCLK1
P5.1/KB1
P5.2/KB2
P5.3/KB3
P5.4/KB4
P5.5/KB5
P5.6/KB6
P5.7/KB7
P3.2/INT0/LED0/CIO1
CC4
PLLF
ALE
PSEN
DVCC
CC8
CIO
P3.0/RxD
1
30 29 28 27 26 25 24 23 22 21 20 19 18 17
VREF
VCC
RST
10
AT8xC5122/23
4202E–SCR–06/06
Fi gure 5. QFN64 P acka ge Pinout
62 61 60 59 58 63
57
56 55 54 53
P0.1/AD1
P0.3/AD3
P0.5/AD5
P0.7/AD7 D+
P4.1/MOSI
P4.0/MISO
P4.2/SCK
P4.5/LED6
P3.1/TxD
P4.3/LED4
P4.4/LED5
P3.6/WR/LED2
D-
XTAL1
XTAL2 P2.5/A13
P2.4/A12
P2.2/A10
P2.1/A9
P2.0/A8
CRST
CCLK
LI
P2.3/A11
2
3
4
5
6
7
8
9
10
11
48
47
46
45
44
43
42
41
40
39
38
QFN64
64 52
12
13 36
37
VCC
VSS
P5.0/KB0
P3.7/RD/LED3
51 50
AVSS
49
AVCC
P3.3/INT1
35
33
34
P3.4/T0/LED1
P3.5/T1/CRST1
CVCC
14
15
16
CVSS
31 32
P0.0/AD0
P1.2/CPRES
P0.2/AD2
P0.4/AD4
P0.6/AD6
P1.6/SS
P2.7/A15
P2.6/A14
P1.7/CCLK1
P5.1/KB1
P5.2/KB2
P5.3/KB3
P5.4/KB4
P5.5/KB5
P5.6/KB6
P5.7/KB7
P3.2/INT0/LED0/CIO1
CC4
PLLF
ALE
PSEN
DVCC
CC8
CIO
P3.0/RxD
1
30 29 28 27 26 25 24 23 22 21 20 19 18 17
VREF
RST
VCC
11
AT8xC5122/23
4202E–SCR–06/06
Low Pin Coun t Package
Description
AT8x C5122 and AT83C5123
versions Figu re 6. P LCC28 Pac kage Pinout
AT83C5123 version Figure 7. VQFP32 Package Pinout
CIO
PLCC28
P3.1/TxD
CCLK
VSS
CC4
DVCC
CC8
XTAL1
XTAL2
LI
VCC
P3.7/LED3
CVCC
CVSS
P3.6/LED2
CRST P3.3/INT1
P1.2/CPRES
D-
D+
AVCC
AVSS
PLLF
P3.2/INT0/LED0
P3.4/T0/LED1
P3.0/RxD
1234282726
5
6
7
8
9
10
11
25
24
23
22
21
20
19
15141312 161718
VREF
RST
CIO
VQFP32
P3.1/TxD
CCLK
P5.0
CC4
DVCC
CC8
XTAL1
LI
VCC
P3.7/LED3
CVCC
CVSS
P3.6/LED2
CRST
P1.2/CPRES
D-
D+
AVCC
AVSS
PLLF
P3.4/T0/LED1
P3.0/RxD
28 27 26
1
2
3
4
5
6
7
24
23
22
21
20
19
18
1211109 131415
VSS 81617
P1.6
P3.5/T1/CRST1
P1.7/CCLK1
VREF
2529303132
XTAL2
RST
P3.2/INT0/LED0/CIO1
P3.3/INT1
12
AT8xC5122/23
4202E–SCR–06/06
Fi gure 8. QFN32 P acka ge Pinout
CIO
QFN32
P3.1/TxD
CCLK
P5.0
CC4
DVCC
CC8
XTAL1
LI
VCC
P3.7/LED3
CVCC
CVSS
P3.6/LED2
CRST
P1.2/CPRES
D-
D+
AVCC
AVSS
PLLF
P3.4/T0/LED1
P3.0/RxD
28 27 26
1
2
3
4
5
6
7
24
23
22
21
20
19
18
1211109 131415
VSS 81617
P1.6
P3.5/T1/CRST1
P1.7/CCLK1
VREF
2529303132
XTAL2
RST
P3.2/INT0/LED0/CIO1
P3.3/INT1
13
AT8xC5122/23
4202E–SCR–06/06
Pin De scr ipt ion
Table 2. Pin Description
Port
VQFP64
VQFP32
PLCC68
PLCC28
QFN64
QFN32
Internal
Power
Supply ESD I/O Reset
Level Alt Reset
Confi g Conf 1 Conf 2 C onf 3 Le d
P0.0 30 - 41 - 30 - VCC 2KV I/O Float AD0 P0 KB_OUT Push-pull
P0.1 29 - 40 - 29 - VCC 2KV I/O Float AD1 P0 KB_OUT Push-pull
P0.2 28 - 39 - 28 - VCC 2KV I/O Float AD2 P0 KB_OUT Push-pull
P0.3 27 - 38 - 27 - VCC 2KV I/O Float AD3 P0 KB_OUT Push-pull
P0.4 25 - 36 - 25 - VCC 2KV I/O Float AD4 P0 KB_OUT Push-pull
P0.5 24 - 35 - 24 - VCC 2KV I/O Float AD5 P0 KB_OUT Push-pull
P0.6 23 - 34 - 23 - VCC 2KV I/O Float AD6 P0 KB_OUT Push-pull
P0.7 22 - 33 - 22 - VCC 2KV I/O Float AD7 P0 KB_OUT Push-pull
CIO 64 32 9 4 64 32 CVCC 6KV I/O 0 Port51
CVCC inactive at reset.
ESD teste d with a 10µF on CVCC
An external pull-up of 10K is
recommended to support ICC’s
with too high internal pull-ups.
CC4 3 3 12 7 3 3 CVCC 6KV I/O 0 Port51 CVCC inactive at reset
ESD teste d with a 10µF on CVCC
P1.2 2 2 11 6 2 2 VCC 2KV I/O 1 CPRES Port51 W e ak & me di um pul l- u p ca n be
disconnected
CC4 9 5 18 9 9 5 CVCC 6KV I/O 0 Port51 CVCC inactive at reset
ESD teste d with a 10µF on CVCC
CCLK 12 6 21 10 12 6 CVCC 6KV O 0 Push-pull CVCC inactive at reset
ESD teste d with a 10µF on CVCC
CRST 6 4 15 8 6 4 CVCC 6KV O 0 Push-pull CVCC inactive at reset
ESD teste d with a 10µF on CVCC
P1.6 47 23 58 - 47 23 VCC 2KV I/O 1 SS Port51
P1.7 62 31 7 - 62 31 VCC 2KV I/O 1 CCLK1 Port51
P2.0 58 - 3 - 58 - VCC 2KV I/O 1 A8 Port51 Push-pull KB_OUT Input
WPU
P2.1 57 - 2 - 57 - VCC 2KV I/O 1 A9 Port51 Push-pull KB_OUT Input
WPU
P2.2 56 - 1 - 56 - VCC 2KV I/O 1 A10 Port51 Push-pull KB_OUT Input
WPU
P2.3 52 - 65 - 52 - VCC 2KV I/O 1 A11 Port51 Push-pull KB_OUT Input
WPU
P2.4 51 - 64 - 51 - VCC 2KV I/O 1 A12 Port51 Push-pull KB_OUT Input
WPU
P2.5 50 - 63 - 50 - VCC 2KV I/O 1 A13 Port51 Push-pull KB_OUT Input
WPU
14
AT8xC5122/23
4202E–SCR–06/06
P2.6 49 - 62 - 49 - VCC 2KV I/O 1 A14 Port51 Push-pull KB_OUT Input
WPU
P2.7 46 - 57 - 46 - VCC 2KV I/O 1 A15 Port51 Push-pull KB_OUT Input
WPU
P3.0 45 22 56 24 45 22 VCC 2KV I/O 1 RxD Port51 Push-pull KB_OUT Input
WPU
P3.1 48 24 59 25 48 24 VCC 2KV I/O 1 TxD Port51 Push-pull KB_OUT Input
WPU
P3.2 43 20 54 23 43 20 VCC 2KV I/O 1 INT0 Port51 LED0
P3.3 41 19 52 22 41 19 VCC 2KV I/O 1 INT1 Port51 Push-pull KB_OUT Input
WPU
P3.4 39 18 50 21 39 18 VCC 2KV I/O 1 T0 Port51 Push-pull KB_OUT Input
WPU LED1
P3.5 44 21 55 - 44 21 VCC 2KV I/O 1 T1 Port51
P3.6 36 17 47 20 36 17 VCC 2KV I/O 1 WR Port51 LED2
P3.7 26 13 37 16 26 13 VCC 2KV I/O 1 RD Port51 LED3
P4.0 42 - 53 - 42 - VCC 2KV I/O 1 MISO Port51
P4.1 40 - 51 - 40 - VCC 2KV I/O 1 MOSI Port51
P4.2 38 - 49 - 38 - VCC 2KV I/O 1 SCK Port51
P4.3 37 - 48 - 37 - VCC 2KV I/O 1 Port51 Push-pull KB_OUT Input
MPU LED4
P4.4 35 - 46 - 35 - VCC 2KV I/O 1 Port51 Push-pull KB_OUT Input
MPU LED5
P4.5 33 - 44 - 33 - VCC 2KV I/O 1 Port51 Push-pull KB_OUT Input
MPU LED6
P5.0 14 7 23 - 14 7 VCC 2KV I/O 1 KB0 Port51 Push-pull Input
MPU Input
WPU
P5.1 13 - 22 - 13 - VCC 2KV I/O 1 KB1 Port51 Push-pull Input
MPU Input
WPU
P5.2 11 - 20 - 11 - VCC 2KV I/O 1 KB2 Port51 Push-pull Input
MPU Input
WPU
P5.3 10 - 19 - 10 - VCC 2KV I/O 1 KB3 Port51 Push-pull Input
WPD Input
WPU
P5.4 8 - 17 - 8 - VCC 2KV I/O 1 KB4 Port51 Push-pull Input
WPD Input
WPU
Table 2. Pin Description (Continued)
Port
VQFP64
VQFP32
PLCC68
PLCC28
QFN64
QFN32
Internal
Power
Supply ESD I/O Reset
Level Alt Reset
Confi g Conf 1 Conf 2 C onf 3 Le d
15
AT8xC5122/23
4202E–SCR–06/06
P5.5 7 - 16 - 7 - VCC 2KV I/O 1 KB5 Port51 Push-pull Input
WPD Input
WPU
P5.6 5 - 14 - 5 - VCC 2KV I/O 1 KB6 Port51 Push-pull Input
WPD Input
WPU
P5.7 4 - 13 - 4 - VCC 2KV I/O 1 KB7 Port51 Push-pull Input
WPD Input
WPU
RST 34 16 45 19 34 16 VCC I/0
Reset Input
The Port pins are driven to their reset conditions when a voltage
lower than VIL is applied, whether or not the oscillator is running.
This pin has an internal 10K pull-up resistor which allows the device
to be reset b y connecting a capacitor betw een this pi n and VSS.
Asserting RST when the chip is in Idle mode or Power-Down mode
returns the chip to normal operation.
The output is active for at least 12 oscillator periods when an internal
reset oc curs.
D+ 60 29 5 2 60 29 DVCC I/O
USB Positive Data Upstream Port
This pin requires an external serial resistor of 27Ω (AT8xC122) or
33Ω (AT83C5123) and a 1.5 K
Ω
pull-up to VREF for full speed
configuration.
D- 59 28 4 1 59 28 DVCC I/O USB Negative Da ta Upstream Port
This pin requires an external serial resistor of 27Ω (AT8xC122) or
33Ω (AT83C5123)
VREF 61 30 6 3 61 30 AVCC O USB Volta ge Reference: 3.0 < VREF < 3.6 V
VREF can be connected to D+ through a 1.5 K
Ω
resistor. The VREF
voltage is controlled by software.
XTAL
131 14 42 17 31 14 VCC I Input to the on-chip inverting oscillator amplifier
To use th e internal oscillator, a crystal or an external oscillator must
be connected to this pin.
XTAL
232 15 43 18 32 15 VCC O Output of the on-chip inverting oscillator amplifier
To use th e internal oscillator, a crystal circuit m ust be connected to
this pin. If an external oscillator is used, leave XTAL2 unconnected.
EA/
VCC 63 - 8 - 63 - VCC I
External Access Enable (Only AT8xC5122)
EA must be strapped to ground in order to enable the device to fetch
c ode from external memory locations 0000h to FFFFh.
If security level 1 is programmed, EA will be latched on reset.
Warning : EA pin cannot be left floating. If the External Access
Ena bl e mode i s not u sed, E A pi n m us t b e st r apped t o VC C. If th is l ast
condition is not met,the MCU may have an unpredictable behaviour.
VC C (Only AT89C5122DS)
ALE21-32-21- VCC O
Address Latch Enable/Program Pulse: Ou tp ut pulse f or latc hing
the low byte of the address during an access to external memory. In
normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2
mode ) the os cil l ator f re qu enc y, and ca n be use d fo r ex te rna l t imi ng or
c locking. No te that one ALE pulse i s skipped during each access to
ex ternal d ata memory. ALE can be di sabled by setting SFR’s
AUXR.0 bit. With this bit set, ALE will be inactive during internal
fetches
Table 2. Pin Description (Continued)
Port
VQFP64
VQFP32
PLCC68
PLCC28
QFN64
QFN32
Internal
Power
Supply ESD I/O Reset
Level Alt Reset
Confi g Conf 1 Conf 2 C onf 3 Le d
16
AT8xC5122/23
4202E–SCR–06/06
PSEN 15 - 24 - 15 - VCC O
Program Strobe Enable: The read strobe to external program
memory. When executing code from the external program memory,
PSEN is activated twice each machine cycle, except that two PSEN
activations are skipped during each access to external data memory.
PSEN is not activated during fetches from internal program memory.
PLLF 54 26 67 27 54 26 AVCC O PLL Low Pass Filter input
Receives the RC network of the PLL low pass filter .
AVCC 55 27 68 28 55 27 PWR Analog Supply Voltage
AVCC is used t o supply the internal 3.3V anal og regulator wh ich
s upplies the i nternal USB driver
VCC201231152012 PWR Supply Voltage
VCC is used to supply the internal 3.3V digital regulator which
s upplies the PLL, CPU core and in ternal I /O’s
LI 18 10 29 13 18 10 PWR
DC/DC Input
LI supplies the current for the charge pump of the DC/DC converter.
- LI tied directly to VCC : the DC/DC converter must be configured in
regulat or mode.
- LI tied to VCC t hroug h an external 10µH coil : the DC/ DC converter
c an be configured e ither in regulator or in pump mode.
CVCC 17 9 28 12 17 9 PWR
Card Supply Voltage
CV CC is the ouput of internal DC/ DC converter whic h supplies the
Smart Card Interface. It must be connected to an external decoupling
capacitor of 10 µF with the lowest ESR as this parameter influences
on the CVCC noise
DVCC 1 1 10 5 1 1 PWR
Digital Supply Voltage
DV CC is the output of the internal an alog 3.3V regulator which
supplies the USB driver. This pin must be connected to an external
680nF decoupling capacitor if the USB interface is used.
Thi s ou t pu t can be use d by th e appl ic at i on wi th a max imum of 10 mA .
CVSS 19 11 30 14 19 11 GND DC/DC Groun d
CVSS is used to sink high shunt currents from the external coil
VSS 16 8 25 11 16 8 GND Digital Ground
VSS is used to supply the PLL, buffer ring and the digita l core
AVSS 53 25 66 26 53 25 GND Analog Ground
AVSS is used to supply the USB driver.
Table 2. Pin Description (Continued)
Port
VQFP64
VQFP32
PLCC68
PLCC28
QFN64
QFN32
Internal
Power
Supply ESD I/O Reset
Level Alt Reset
Confi g Conf 1 Conf 2 C onf 3 Le d
17
AT8xC5122/23
4202E–SCR–06/06
Typical Applic at ions
Recommended External components
All the external componen ts d escribed in the figure and table below must be imple-
mented as close as possible from the microcontroller package.
Table 3. External Components Bill Of Materials
Reference Description Value Comments
R1 USB Full Sp eed Pull-up 1.5 KΩ +/-10% All product versions
R2 USB pad serial resistor 27 Ω +/-10% For AT8xC5122 v ersions
33 Ω +/-10% For AT83C5123 versions
R3 USB pad serial resistor 27 Ω +/-10% For AT8xC5122 v ersions
33 Ω +/-10% For AT83C5123 versions
R4 PL L fil t er resisto r 1. 8 KΩ +/- 10% All product versions
R5 CIO Pull-up resistor 10 KΩ +/ 10% All product v ersions
C1 Power Supply filter cap acitor 100 nF +80/-20% All product versions
C2 PLL filter capacitor 33 pF +/-10% All product versions
C3 PLL filter capacitor 150 pF +/-10% All product versions
C4 USB pad decoupling cap acitor 680 nF +/-30% All product versions.
If USB interface is not used, this capacitor is optional
C5 Smart Card clock filter capacitor 27 pF +/-10% All product versions.
C6 DC/DC Converter decoupling capacitor 10 µF +/-10 %
Low ES R All product versions.
This capacitor does not impact the USB Inrush Current
C7 DC/DC Converter filter capacitor 100 nF +80/-20% All product versions
C8 Power Supply decoupling capacitor 4.7 µF +/-10% All products versions
This capacitor impacts the USB Inrush Current. Maximum
application capacitance allowed by the USB standard is 10 µF.
C9 Power Supply filter cap acitor 100 nF +80/-20C All produc t versions
C10 Reset capacitor 10 µF +/-10% Optional ca pacitor for all product ve rsions
L1 DC/ DC converter input inductance 10 µH +/- 10%
Min rated current : 200 mA
Min rated freq. : 4 MHz
All product versions.
Qualified component : Murata LQH32CN100K21L
If DC/DC converter is not used at 5V, this inductance is optional.
Q1 Crystal 8.0000 Mh z +/- 2500 ppm
max
ESR max : 100 Ω
All product versions
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AT8xC5122/23
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USB Keyboard with Smart Card Reader Using the AT8xC5122 and AT89C5122DS Versions
LEDx
VCC
KB1
KB2
KB3
KB4
KB5
KB6
KB7
R19
R18
R17
R16
R15
P3[0-1,3-4]
P2[0-7]
R14
R13
R12
R11
R10
R09
R08
P0[0-7]
R07
R06
R05
R04
R03
R02
R01
R00
Keyb oard Matrix
C1
C2
C3
C4
C5
C6
C7
KB0
C0
GNDC1
EA/VCC (1)
GND GNDC8
C9
VCC
VCC VCC AVCC
XTAL2XTAL1
Q1
VCC
R2
GND
D-
D+
VREF
D+
D-
VCC
VBUS
GND
USB
R3
R1
AVSS
GND
C2
R4
C3
PLLF
VSS
GND
GND
C4 DVCC
10mA Max
GND
CCLK1
CRST1
CIO1
RST
CLK
I/O
C2
C3
C7
VCC
C1
GND
C5
Altern at e C ard
VCC
GND
RST Optional
Capacitor
C10
Notes :
1 - Pin configuration depends on product versions
LI L1
Smart Card
C1
C2
C3
C4
C7
C8
C5
VCC
RST
CLK
C4
I/O
C8
GND
S1
CPRES S2
GND
GND
C6
S1
C7
CC8
CIO
CC4
CCLK
CRST
CVSS
CVCC
VCC
R5
19
AT8xC5122/23
4202E–SCR–06/06
USB Smart Card Reader Using the AT83C5123 Version
LEDx
VCC
GND
RST Optional
Capacitor
GND
GNDC1
EA
GND GNDC8
C9
VCC
VCC VCC AVCC
XTAL2XTAL1
Q1
VCC
R2
GND
D-
D+
VREF
D+
D-
VCC
VBUS
GND
USB
R3
R1
C10
CCLK1
CRST1
CIO1
RST
CLK
I/O
C2
C3
C7
VCC
C1
GND
C5
Altern ate Card
AVSS
GND
C2
R4
C3
PLLF
VSS
GND
GND
C4 DVCC
10mA Max
VCC
LI L1
Smart Card
C1
C2
C3
C4
C7
C8
C5
VCC
RST
CLK
C4
I/O
C8
GND
S1
CPRES S2
GND
GND
C6
S1
C7
CC8
CIO
CC4
CCLK
CRST
CVSS
CVCC
VCC
R5
20
AT8xC5122/23
4202E–SCR–06/06
Me m ory Or ga nization The AT8xC5122/23 devices have separated address spaces for Program and Data
Memory, as shown in Figure 13 on page 29, Figure 14 on page 31 and Figure 15 on
page 32. The logical separation of Program and Data mem ory allows the Data Memory
to be a ccessed by 8-bi t addresses , w hich can be m ore quickly s tored and m anipul ated
by an-bit CPU. Nevertheless, 16-bit Data Memory addresses can also be generat ed
through the DPTR register.
Program Memory
Managament Depending on the state of EA pin, the MCU fetches the code from internal or external
pro gram memory (R OMless mo de)
Warning : th e E A pi n can no t be le ft f loati ng, ot her wis e MC U ma y h ave an un pred ict-
able behaviour.
If EA is strapped to VCC, the MCU fe tches the co de from the internal program m emo ry.
Th e w ay t he MC U work s in this mod e depe nds on the d evi ce ve rsi on. S ee nex t pa ra-
graphs for further det ails.
If the EA is strapped to GND, the MCU fetches the code from external program memory.
This mode is common for all device versions wich supports it. After reset, the CPU
begins the execut ion from location 0000h. There can be up to 64 KBytes of program
memory. In this mode, the internal program memories are disabled.
The hardware conf iguration for external program execution is shown in F i gure 9.
Fi gure 9. Execut ing from External Program Memor y
Note that the 16 I/O line s (Ports 0 and 2) are dedicated to bus func tions during ex ternal
Pro gram Mem or y fe tches. P ort 0 serves a s a multi plexed a ddre ss/dat bus. It emits th e
low byt e of the Program Counte r (P CL) as an address , a nd then goes into a float state
aw aiting the arrival of the code byte from t he Prog ram Mem ory . During the time that the
low byte of the Program Counter is valid o n P 0, the signal ALE (Address Latch Enable)
clocks the by te into a n a ddress latch. Mea nwhile , Port 2 emits the high byte of the Pro-
gram Counter (PCH). Then PSEN strobes t he External Progra m Mem ory and the c ode
byte is read into t he MCU.
PSEN is not activated and Ports P0 and P2 are not aff ec ted during internal program
fetches.
EXTERNAL PROGRAM
MEMORY
AT8xC5122
P2
P0 AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE Latch
OEPSEN#
21
AT8xC5122/23
4202E–SCR–06/06
Data Memory
Managament All device versi ons implements :
- 256 Bytes of RAM to increase data parameter handling and high level language usage
- 512 bytes of XRAM (Extended RAM) to store program data.
RAM Ach itecture The internal RAM is mapped into three separate segmen ts :
• The Lower 128 bytes (addresses 00h to 7Fh) are directly and indirectly
addressable.
• The Upper 128 bytes (addresses 80h to FFh) are indirectly addressable only.
• The Special Function Registers (SFRs) (addresses 80h to FFh) are directly
addressable only.
Th e Upper 128 bytes an d SFR’s ha ve the same ad dress space but ar e phys ically
separated.
W hen an instruction ac cesses an i nternal location ab ove addre ss 7Fh, the CPU kn ows
whether the access is in the uppe r 128 bytes of data RAM or to SFR spa ce by the
address ing mode used in the in struction.
• Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, ac cess es the SFR at location 0A0h (which is P2).
• Instructions that use indirect addressing access the Upper 128 bytes of data RA M .
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
The stack pointer (SP) may be located anywhere in the 256 bytes R AM (lower and
upper RAM) internal data memory. The st ack may not be located in the XRAM.
Th e M0 bit allows to st retc h the X RA M ti mings . If M 0 is s et, t he re ad an d w rite pu ls es
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
XRAM Achitecture De pendin g on t he st ate of EX TR AM bit in AU XR reg ister (See T able 5 on page 24), the
MCU fetches data from internal or external XRAM .
If EX TRAM=0 (reset condition), the MCU fetc hes the data from internal XRAM. The size
of internal XRAM is configured by the bit XRS0 in AUXR register (See Table 5 o n pa ge
24).
The X RA M logically occupies the first bytes of external data memo ry. The bi t XRS0 c an
be use d to hide a part of the available XRAM . This can be useful if external peripherals
are mapped at addresses already used by t he internal XRAM.
The X RAM is indirect ly a ddressed, usin g t he MOVX instruction in comb ination with any
of the registers R0, R1 of the selected bank or DPT R.
For example, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at
addres s 0A0H rather than external memory.
Tab le 4. XRAM Size Configuration
XRS0 XRAM size
Address
Start End
0256 Bytes
(Reset condition) 000h 0FFh
1 512 bytes 000h 1FFh
22
AT8xC5122/23
4202E–SCR–06/06
An a ccess to e xternal XRAM m emory loca tions hig her than the accessi ble size of th e
mem ory (roll-over feature) will be perform ed with t he M OVX DPTR i nstructions, with P 0
and P2 as data/address busses, WR and R D as respectively write and read signals.
Accesses above XRAM size can only be done by the use of DPTR.
If EXTRAM= 1 the MCU fetches the data from external XRAM Memory. There can be up
to 64 KBytes of external XRAM M emo ry.
The hardware conf iguration for external Data Memory Access is shown in Figure 10
Fi gure 10. Accessing to External XRAM Memory
MOVX @ R i an d M OVX @DP T R wil l be similar to the standard 80C51. MOV X @ Ri will
provide an eight-bit address multiplexed with data on Port 0 and any output port pins
ca n be use d to ou tput hi gher ord er a ddress bits. Thi s is to p rovide t he ext ernal pagin g
ca pability. MO VX @DP TR will generate a sixteen -bit addre ss. Po rt 2 outpu ts the high-
order eigh t address bits (DPH) while Port0 m ultiplexes the low -order eight address bits
(DPL) with data. MO VX @ Ri and M OVX @DPTR will generat e e ither read or write sig-
nals on WR and RD.
Ports P0, P2 are not affected and RD, WR signals are not activated during access to
int ernal XRAM.
Note that external XRAM Memory access is onl y available on High Pin Count Packages.
External P rogram Memory and ext ernal XRAM Mem ory may be combined if des ired by
applying the RD and PSEN sig nals to t he in puts o f a n AND gat e and using the ouput of
the gate as the read strobe to the external program/data memory.
Dual Data Pointer
Register (DDPTR) The ad dition al da ta po inter ca n b e used t o spe ed up code exe cuti on and reduc e cod e
size.
The dual DPTR structure is a way by which the chip will specify the address of an exter-
nal data memory l ocation. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 7) that allow the program
code to swi tch between them (Figure 11).
EXT ERN AL XR AM
MEMORY
AT8xC5122/23
P2
P0 AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
WR
OERD#
WR#
Latch
RD
PSEN
STROBE
23
AT8xC5122/23
4202E–SCR–06/06
Figu re 11 . Use of Dual Pointer
a. Bit 2 stuck at 0; this allows to use INC AUXR 1 to toggle DPS without changing GF3.
Assembly Language
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 QU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ;increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit i n the AUXR1
SFR. However, note that t he INC instruction does not directly force the DPS bit to a par-
ticular s tate, but simply t oggles it. In simple rou tines, such a s the bloc k move exam ple,
only the fact that DPS is toggled in the proper sequence matters, not its actual value.
For exam ple , the block move routine work s th e sam e whether DPS is '0' or '1' on entry.
Observ e that witho ut the last in struction (INC AU XR1), th e routine will exit with DPS in
the opposite s tate.
Exte rna l Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
24
AT8xC5122/23
4202E–SCR–06/06
Registers
Rese t Value = 0XXX X000b
Table 5. Auxi lia r y R egi ster - AUXR (8Eh)
76543210
DPU - - - XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7DPU
Disable weak Pull-up
0 weak pull-up is enabled
1 w eak pull-up is disabled
6-3 - Reserved
The value read from this bit is indeterminate. Do not change these bits .
2XRS0
XRAM Size
0 256 bytes (default)
1 512 bytes
1 EXTRAM
EXTRAM bit
Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Power-up regardin g Hardware Security Byte
(HSB), default setting , XRAM selected.
0AO
ALE Output bit
Cleared , ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 m ode is used)(default).
Set , ALE is active only when a MOVX or MO VC instruction is used.
25
AT8xC5122/23
4202E–SCR–06/06
Table 6. Auxiliary Register 1 AUXR1- (0A2h) for A T8xC512 2
Rese t Value = XX1X XX0X0b (Not bit addressabl e)
Table 7. Auxiliary Register 1 AUXR1- (0A2h) for A T83C5 123
Reset Value = XXXX XX0X0b (Not bit addressable)
7 6 5 4 3 2 1 0
--ENBOOT-GF30-DPS
Bit
Number Bit
Mnemonic Description
7 - 6 - Reserved
T he valu e r ea d fr o m thi s bi t is ind eterm in ate. Do no t cha ng e t h es e bits .
5 ENBOOT
Enable Boot ROM (CRAM / E2PROM version only)
Set this bit to map the Boot ROM from 8000h to FFFFh. If the PC increments
beyond 7FFFh address, the code is fetch from internal ROM
Clear this bit to disable Boot ROM. If the PC increments beyond 7FFFh address,
the code is fetch from external code memory (C51 standard roll over function)
This bit is forced to 1 at reset
4-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. Do not chang e th is bit.
3 GF3 This bit is a general-purpose user flag.
2 0 Always cleared.
1-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. Do not chang e th is bit.
0DPS
Data Pointer Selection
Cleared to select DPTR0. Set to select DPTR1.
7 6 5 4 3 2 1 0
----GF30-DPS
Bit
Number Bit
Mnemonic Description
7 - 6 - Reserved
T he valu e r ea d fr o m thi s bi t is ind eterm in ate. Do no t cha ng e t h es e bits .
5Reserved
T he valu e r ea d fr o m thi s bi t is ind eterm in ate. Do no t cha ng e t h es e bits .
4-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. Do not chang e th is bit.
3 GF3 This bit is a general-purpose user flag.
2 0 Always cleared.
1-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. Do not chang e th is bit.
0DPS
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
26
AT8xC5122/23
4202E–SCR–06/06
Reset Value = XXXX 0XXXb
AT8xC5122’s CRAM and E2PROM Versions
The AT8xC5122’s CRAM and E2PROM versions implements :
- 32 KB of ROM mappe d from 8000 to FFFF in which is em bedded a bootlo ader for In-
System P rogramming feature
- 32 KB of CRAM (Code RAM) , a volatile program memo ry mapped fro m 0000 to 7FFF
In CRAM versions only :
- 512 bytes of E2PROM can be optionally implem ented to store permane nt data
In E2 PR OM ve r sion :
- 32KB of E2PRO M are implem ented to store permanen t code
Warning s :
– some bytes of u ser program memory space are reserved for bootloader
configuration. Depending on the c onfiguration, up to 256 bytes of code may
be not available for the user code f rom 7F0 0h location. Refer to bootloader
datasheet for further details.
– Por t P3.7 may be used by the bootloader as a har dware condition at reset to
select the In-System Programming mode. Once the bootloader has started,
the P3.7 Port is no more used.
Table 8. CRAM Configuration Register - RCON (D1h)
76543210
----RPS---
Bit
Number Bit
Mnemonic Description
7 - 4 - Reserved
The value read from this bit is indeterminate. Do not change these bits .
3RPS
CRAM Memory Mapp ing Bit
Set to map the CRAM memory during MOVX instructions
Clear to map the XR AM m emory d uring MOVX .
This bit has priority over the EXTRA M bit.
2-0 - Reserved
The value read from this bit is indeterminate. Do not change these bits .
27
AT8xC5122/23
4202E–SCR–06/06
When pin EA =1 and after the reset, the MCU begins the execution of the embedded
boot loade r from loca tion F800h o f th e ROM. The b ootl oader im plemen ts an I n-System
Programming (ISP) mode which manages the transfer of the code in the volatile Pro-
gra m Memor y ( C R A M) .
For CR AM ve rsion, th e code is sup plied b y the ATM EL’s FL exible I n-s yste m Program -
ming soft ware (FLIP) through USB or UART interface
For E 2PR OM vers ion, the c ode is supplied from the internal code E2PROM or by F LI P.
Th e s tate of pin P3.7 at re set de term ines the co de so ur ce. If P3 .7= 1 (re set cond ition )
the source is the internal E2PRO M and the transfer takes about 1.5 seconds . If P3.7=0
the source is FLIP and the transfer time depends mainly o n external conditions not
related to bootloader.
Once the code is running in CRAM, the roll-over condition (code fetched beyond
address 7FFFh) depends on the state of ENBOOT bit of AUXR1 register (Table 6 on
page 25).
If ENBOOT=1 (reset condition) the MCU fetches the code from bootloader ROM. If
ENBOO T=0, the MCU fetches the cod e from the e xternal Program Mem ory. In this last
case, PSEN is activated and Ports P0 and P2 are used to emit data and address
signals.
Warning : external Program Memory access is not allowed on Low Pin Count
Packages.
7FFFh
0000h
7EFFh
7F00h Reserved
User code
Bootloader
FFFFh
P3.7
AT8xC5122 Microcontroller
28
AT8xC5122/23
4202E–SCR–06/06
Using CRAM Memory The CRAM is a read / write volatile memory that is mapped in the program memory
sp ace. Then wh en the p ower is sw itched o ff the cod e is lost and ne eds to be reload at
each pow er up. In return, the CRAM enabl es a l ot of f lexibility in the co d e developm ent
as it can be p rogrammed in definitely. The us er code runnin g in the CRAM c an perform
read operat ions in CRAM itself by m eans of MOV C instructions like any C51 microcon-
troller does. Although the writing operations in CRAM are usually handled by the
bootloader, it is possible for the user code to hand le its own writing operations in CRAM
as well. T he user co de must c all API functi ons pr ovide d by th e boot loade r in the R OM
memory. Refer to bootloader datasheet for further details about the use of these API
functi ons. These API functions use a mechanism provided by the A T8xC5122 microcon-
troller. When the bit RPS is set in RCON register (Table 8 on page 2 6), the MOVX
intructions are configured t o wri te in CRAM inst ead of XRAM m em ory. Howev er, due t o
C51 arc hitecture, it is not pos sible for the user c ode to write directly in CRAM when it is
itself running in CRAM. This is why the API functions must be called in or der to have the
code executing in ROM while the CRAM is written.
Fi gure 12. Read / Write Mechanis ms in CRAM Memory
MOVX
API functions
RPS=1
Read operation
Writing operation
User cod e
CRAM
BOOTLOADER
API Cal l
MOVC
29
AT8xC5122/23
4202E–SCR–06/06
Figu re 13. AT8xC5122’s CRAM and E2PROM Versions
Reset@<0000>
EA = 0
PROGRAM
EXTERNAL
PROGRAM
PSEN
Reset@
0000
7FFF
8000
FFFF
32K
ROM
32K
CRAM
<F800>
EA = 1
INTERNAL
INTERNAL
32K
PROGRAM
EXTERNAL
ENBOOT=1 ENBOOT=0
8000
FFFF
MEMORY
On-chip
512 bytes
XRAM
0000
01FF
FFFF
RD WR
DATA MEMORY
(Read / Write)
0000
EXTRAM=0 EXTRAM=1
EXTERNAL
EXTERNAL
XRAM
XRAM
01FF
0200
PSEN
Roll-Over
Roll-Over
MEMORY
MEMORY
32K
INTERNAL
E2PROM
(Read/Write)
(Read Only)
(Read/Write)
SFR
Space
80
FF
00
7F
80
FF Upper
128 Bytes
RAM
Lower
128 Bytes
RAM
On-Chip 256 bytes RAM
Direct
Addressing
Indirect
Addressing
512 Bytes
INTERNAL
E2PROM
01FF
0000
Optional
FFFF
8000
(applicable only to CRAM version)
(E2PROM version)
30
AT8xC5122/23
4202E–SCR–06/06
AT8xC5122’s ROM
Version The A T8xC5122’s ROM version implements :
- 32 K of ROM m apped from 0 000h to 7FFF h in which i s em bedded the user c ode. T he
ROM device is only factory programmable .
- 512 byte s of E 2P ROM can be op tiona lly imp lem ente d to s tore perman en t data. Wi th
this option, the size of ROM is reduced to 30K.
Aft er the res et, th e MCU b egins t he exe cutio n of the user code fr om loc ation 00 00h of
the ROM.
Access to external Program Memory is not allowed.
Security Le ve l There are two security levels (applicable to High Pin Coun t packages only) :
The security l evel 2 can be used to prot ect the user code from piracy. This option is con-
figured at factory and must be requested by the customer at order time.
Table 9. Securi ty Le ve l s Des cri pt i on
Security Level Protection descripti on
1 No protection lock enabled
2
MOVC instruction exe cuted from ext ernal Pr ogram M emory is disabled when fetching
code b y tes from internal Program Memory
EA is sampled and latched on reset.
External code ex ecution is enabled.
31
AT8xC5122/23
4202E–SCR–06/06
Figu re 14. AT8xC5122’s ROM Version
P R OG R AM MEMORY
(Read only)
0000
7FFF
FFFF
EA=1
INTERNAL
32K ROM
EA=0
EXTERNAL
EXTERNAL
RESET@
<0000>
SFR
Space
80
FF
On-chip
512 bytes
XRAM
0000
01FF
FFFF
RD WR 00
7F
80
FF Upper
128 Bytes
RAM
Lower
128 Bytes
RAM
DATA MEMORY
(Read / Write)
0000
EXTRAM=0 EXTRAM=1
EXTERNAL
EXTERNAL
XRAM
XRAM
01FF
0200
8000
Roll-Over
PSEN
On-Chip 256 bytes RAM
Direct
Addressing
Indirect
Addressing
512 Bytes
INTERNAL
E2PROM
01FF
0000
Optional
Roll-Over
32
AT8xC5122/23
4202E–SCR–06/06
AT83C5123 Version The AT83C5123 device is a low pin count version of the AT8xC5122.
The ROM version implement s :
- 30 KB of R OM mapp ed from 0000 to 77 FF in w hich is embed ded the user co de. Th e
ROM device is only factory programmable .
- 512 bytes of E2PROM can be optionally implem ented to store permane nt data
Figu re 15. AT83C5123’s Device
P R OG R AM MEMORY
(Read only)
7FFF
INTERNAL
30K ROM
RESET@
<0000>
SFR
Space
80
FF
On-chip
512 bytes
XRAM
0000
01FF
00
7F
80
FF Upper
128 Bytes
RAM
Lower
128 Bytes
RAM
DATA MEMORY
(Read / Wri te)
On-C hip 256 bytes RAM
Direct
Addressing
Indi rect
Addressing
512 Bytes
INTERNAL
E2PROM
01FF
0000
OPTIONAL
33
AT8xC5122/23
4202E–SCR–06/06
Special Functi on
Reg is ter s (S FR ’s)
Introduction The Special Function Registers (SFRs) of the AT8xC5122/23 can be ranked into the fol-
lowing categories:
• C51 Core Regist ers: ACC, B, DPH, DPL, PSW, SP
• System Configu ration Registers: PCON, CKRL, CKCON0, CKCON1, CKSEL,
PLLC O N , PL L DIV, AUXR, AUXR1, RCON
• I/O Port Registers: P0, P1, P2, P3, P4, P5, PMOD1, PMOD2
• Timer Registers: TCON, TH0, TH1, TMOD, TL0, TL1
• Wa tchdog (WD) Registers: WDTRST, WDTPRG
• Serial I/O Port Registers: SADDR , SADEN, SBUF, SCON
• Baud Rate Generato r (BRG) Registers: BRL, BDRCON
• System Interrupt Registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
• Smart Card Inter face (SCI) Register s: SC SR, SC C ON/SCETU0, SCISR /SCETU1,
SC IER /SCIIR, SCI BUF, SCGT0 /SCWT0, SCGT1/S C WT1 , SC ICR /SCWT 2 , SCIC L K
• DC/DC Converter Regi ster s: DCCKPS
• Keyboard Interf ace Regist ers: KBE, K BF, KBLS
• Seri a l Port In ter f a ce (S P I) Reg is ter s : SPCON , SPSTA, SP D AT
• Universal Serial Bus (US B) Registers:U SBCON, USBADDR, USBINT, USBIEN,
UE PN UM, UEPC O N X, UEPSTAX, UEPRST, UEPI NT, UEPIEN, UEP D ATX,
UBYCTX, UFNUML, UF NUM H
• LED Controller Regi sters: LEDCON0, LEDCON1
34
AT8xC5122/23
4202E–SCR–06/06
AT8 xC5122 Versio n
Notes: 1. Mapping is done using SCRS bit in SCSR register.
2. Grey areas : do not write in.
Bit
addressable Not bit addressable
0/ 8 1 /9 2/A 3/ B 4/ C 5/ D 6/ E 7/F
F8h UEPINT
0000 0000
F0h B
0000 0000 LEDCON0
0000 0000
E8h P5
1111 1111
E0h ACC
0000 0000 LEDCON1
XX00 0000 UBYCTX
0000 0000
D8h
D0h PSW
0000 0000 RCON
XXXX 0XXX UEPCONX
1000 0000 UEPRST
0000 0000
C8h UEPSTAX
0000 0000 UEPDATX
0000 0000
S
C
R
S
1
C0h P4
1111 1111
SCICLK (1)
0X10 1111 UEPIEN
0000 0000 SPCON
0001 0100 SPSTA
0000 0000 SPDAT
1111 1111 USBADDR
1000 0000 UEPNUM
0000 0000
0SCWT3 (1)
0000 0000
B8h IPL 0
X000 000 SADEN
0000 0000 UFNUML
0000 0000 UFNUMH
0000 0000 USBCON
0000 0000 USBINT
0000 0000 USBIEN
0000 0000 DCCKPS
0000 0000
S
C
R
S
1
B0h P3
1111 1111 IEN1
XXXX X000 IPL1
00XX 00X0 IPH1
00XX 00X0
SCGT0 (1)
0000 1100 SCGT1(1)
XXXX XXX0 SCICR (1)
0000 0000 IPH0
X000 0000
0SCWT0(1)
1000 0000 SCWT1 (1)
0010 0101 SCWT2 (1)
0000 0000
S
C
R
S
1
A8h IEN0
0000 0000 SADDR
0000 0000 SCIBUF
XXXX XXXX SCSR
X000 1000
SCETU0 (1)
0111 0100 SCETU1 (1)
XXXX X001 SC IER (1)
0X00 0000
0 SCCON (1)
0000 0000 SCISR (1)
10X0 0000 SCIIR (1)
0X00 0000
A0h P2
1111 1111 ISEL
0000 0100 AUXR1
XX 1X 0XX0 PLLCON
XXXX X000 PLLDIV
0000 0000 WDTRST
XXXX XXXX WDTPRG
XXXX X00 0
98h SCON
0000 0000 SBUF
XXXX XXXX BRL
0000 0000 BDRCON
X XX 0 00 00 KBLS
0000 0000 KBE
0000 0000 KBF
0000 0000
90h P1
1111 1111 PMOD0(2)
0000 0000 CKRL
XXXX 1111
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
0XXX X000 CKCON0
X0X0 X000
80h P0
1111 1111 SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PMOD1
0000 0000 CKSEL
XXXX XXX0 PCON
00X1 0000
35
AT8xC5122/23
4202E–SCR–06/06
AT8 3C5123 Versio n
Notes: 1. Mapping is done using SCRS bit in SCSR register.
2. Grey areas : do not write in.
Bit
addressable Not bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h UEPINT
0000 0000
F0h B
0000 0000 LEDCON0
0000 0000
E8h P5
XXXX XXX1
E0h ACC
0000 0000 UBYCTX
0000 0000
D8h
D0h PSW
0000 0000 UEPCONX
1000 0000 UEPRST
0000 0000
C8h UEPSTAX
0000 0000 UEPDATX
0000 0000
S
C
R
S
1
C0h P4
11XX XXXX
SCICLK (1)
0X10 1111 UEPIEN
0000 0000 USBADDR
1000 0000 UEPNUM
0000 0000
0SCWT3 (1)
0000 0000
B8h IPL0
X000 000 SADEN
0000 0000 UFNUML
0000 0000 UFNUMH
0000 0000 USBCON
0000 0000 USBINT
0000 0000 USBIEN
0000 0000 DCCKPS
0000 0000
S
C
R
S
1
B0h P3
1111 1111 IEN1
X0XX 0XX X IPL1
X0XX 0XXX IPH1
X0XX 0XXX
SCGT0 (1)
0000 1100 SCGT1(1)
XXXX XXX0 SCICR (1)
0000 0000 IPH0
X000 0000
0SCWT0(1)
1000 0000 SCWT1 (1)
0010 0101 SCWT2 (1)
0000 0000
S
C
R
S
1
A8h IEN0
0000 0000 SADDR
0000 0000 SCIBUF
XXXX XXXX SCSR
X000 1000
SCETU0 (1)
0111 0100 SCETU1 (1)
XXXX X001 SCIER (1)
0X0 0 00 00 CKCON1
XXXX XXX0
0 SCCON (1)
0000 0000 SCISR (1)
10X0 0000 SCIIR (1)
0X0 0 00 00
A0h ISEL
0000 0100 AUXR1
XXXX 0XX0 PLLCON
XXXX X000 PLLDIV
0000 0000 WDTRST
XXXX XXXX WDTPRG
XXXX X000
98h SCON
0000 0000 SBUF
XXXX XXXX BRL
0000 0000 BDRCON
XXX0 0000
90h P1
1111 1111 PMOD0
00XX 0XXX CKRL
XXXX 1111
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
0XXX X000 CKCON0
X0X0 X000
80h SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PMOD1
XXXX 00XX CKSEL
XXXX XXX0 PCON
00X1 0000
36
AT8xC5122/23
4202E–SCR–06/06
SFR’s De scr ipt ion
Note: 1. Only for AT8 xC5122
Note: 1. Only for AT8 xC5122
Tab le 10. C51 Core SFRs
MnemonicAddName 76543210
ACC E0h Accumulator ACC
B F0h B Register B
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP 81h Stack Pointer SP
DPL 82h Data Pointer Low byte (LSB
of DPTR) DPL
DPH 83h Data Pointer High byte
(MSB of DPTR) DPH
Table 1 1. Clock SFRs
MnemonicAddName 76 5 43210
PCON 87h Power Controller SMOD1 SMOD0 POF GF1 GF0 PD IDL
CKCON0 8Fh Clock Co ntroller 0 WDX2 SIX2 T1X2 T0X2 X2
CKCON1 AFh Clock Controller 1 SPIX2
CKSEL 85h Clock Selection CKS
CKRL 97h Clock Reload Register CKREL 3-0
PLLCON A3h PLL Controller Register EXT48 PLLEN PLOCK
PLLDIV A4h PL L Divider register R3-0 N3-0
AUXR 8Eh Auxiliary Register 0 DPU XRS0 EXTRAM A0
AUXR 1 A2h Auxiliary Register 1 ENBOOT(1) GF3 DPS
RCON (1) D1h C R AM me m or y
Configuration RPS
Tab le 12. I/O Port SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
P0(1) 80h Port 0 P0
P1 90h Port 1 P1
P2(1) A0h Port 2 P2
P3 B0h Port 3 P3
P4(1) C0h Port 4 P4
P5 E8h Port 5 P5 (only P5.0 for AT8xC5122)
PMOD0 91h Port Mode Register 0 P3C1 P3C0 P2C1(1) P2C0(1) CPRESRES - P0C1(1) P0C0(1)
PMOD1 84h Port Mode Register 1 P5HC1(1) P5HC0(1) P5MC1(1) P5MC0(1) P5LC1 P5LC0 P4C1(1) P4C0(1)
37
AT8xC5122/23
4202E–SCR–06/06
Tab le 13. Timers SFRs
MnemonicAddName 76543210
TH0 8Ch Timer/Counter 0 High byte TH0
TL0 8Ah Timer/Coun ter 0 Low byte TL0
TH1 8Dh Timer/Counter 1 High byte TH1
TL1 8Bh Timer/Coun ter 1 Low byte TL1
TCON 88h Timer/Counter 0 and 1
control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h Timer/Coun ter 0 and 1
Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
Tab le 14. Wat chdog SFRs
MnemonicAddName 76543210
WDTR ST A6h Watchdog T imer Reset WD TRST
WDTPRG A7h Watchdog Timer Program S2-0
Tab le 15. Seri a l I/O Por ts SF Rs
MnemonicAddName 76543210
SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
S BU F 99 h Seri al D ata Buffer SBU F
SADEN B9h Slave Address Mask SADEN
SADDR A9h Slave Address SADDR
Tab le 16. Baud Rat e Generator SFRs
MnemonicAddName 76543210
BRL 9Ah Baud Rate Reload BRL
BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD M0SRC
Tab le 17. I n terru pt SFR s
MnemonicAddName 76543210
IEN0 A8h Interrupt Enable Control 0 EA ES ET1 EX1 ET0 EX0
IEN1 B1h Interrupt Enable Control 1 EUSB ESCI ESPI(1) EKB(1)
IPL0 B8h I nterru pt Priority Control
Low 0 PSL PT1L PX1L PT0L PX0L
38
AT8xC5122/23
4202E–SCR–06/06
Note: 1. Only for AT8 xC5122
IPH0 B7h Interru pt Priority Control
High 0 PSH PT1HPX1HPT0HPX0H
IPL1 B2h I nterru pt Priority Control
Low 1 PUSBL PSCIL PSPIL(1) PKBL(1)
IPH1 B3h Interru pt Priority Control
High 1 PUSBH PSCIH PSPIH(1) PKBH(1)
ISEL A1h Interrupt Enable Register CPLEV PRESIT RXIT OELEV OEEN PRESEN RXEN
Tab le 17. I n terru pt SFR s
MnemonicAddName 76543210
Tab le 18. SCIB SFRs
MnemonicAddName 76543210
SCGT0 B4h Smart Card Transmit Guard
Time Register 0 GT7 - 0
SCGT1 B5h Smart Card Transmit Guard
Time Register 1 GT8
SCWT0 B4h Smart Card Character/ Block
Waiting Time Register 0 WT7 - 0
SCWT1 B5h Smart Card Character/ Block
Waiting Time Register 1 WT15-8
SCWT2 B6h Smart Card Character/ Block
Waiting Time Register 2 WT23-16
SCWT3 C1h Smart Card Character/ Block
Waiting Time Register 3 WT31-24
SCICR B6h Smart Card Interface Control
Register RESET CARDDET VCARD1-0 UART WTEN CREP CONV
SCCON ACh Smart Card Interface
Contacts Register CLK CARDC8 CARDC4 CARDIO CARDCLK CARDRST CARDVCC
SCETU0 ACh Smart Card ETU Register 0 ETU7 - 0
SCETU1 ADh Smart Card ETU Register 1 COMP ETU10-8
SCISR ADh Smart Card UART Interface
Status Register (Read only) SCTBE CARDIN ICARDOVF VCARDOK SCWTO SCTC SCRC SCPE
SCIIR AEh Smart Card UART Interrupt
Identification Register (Read
only) SCTBI ICARDERR VCARDERR SCWTI SCTI SCRI SCPI
SCIER AEh Smart Card UART Interrupt
Enable Register ESCTBI ICARDER EVCARDER ESCWTI ESCTI ESCRI ESCPI
SCSR ABh Smart Card Selection
Register BGTEN CREPSEL ALTKPS1-0 SCCLK1 SCRS
SCIBUF AAh Smart Card Buffer Register
Can store a new byte to be transmitted on the I/O pin when SCTBE is set. Bit ordering on the I/O pin
depends on the convention
Prov ides the byte received from the I/O pin when SCRI is s et. Bit ordering on t he I/O pin depends on
th e co nv en t i on .
39
AT8xC5122/23
4202E–SCR–06/06
Note: 1. Only for AT8 xC5122
Note: 1. Only for AT8 xC5122
Notes: 1. Only for AT8xC5122
SCICLK C1h Smart Card F reque ncy
Pr escaler Register XTSCS(1) SCICLK5-0
Tab le 18. SCIB SFRs
MnemonicAddName 76543210
Tab le 19. DC/DC SFRs
MnemonicAddName 76543210
DCCKPS BFh DC/DC Converter Reload
Register MODE OVFADJ BOOST[1-0] DCCKPS3-0
Tab le 20. Keyboard S FRs
MnemonicAddName 76543210
KBF(1) 9Eh Keyboard Flag Register KBE7 - 0
KBE(1) 9Dh Keyboard Input Enable
Register KBF7 - 0
KBLS(1) 9Ch Keyboard Level Selecto r
Register KBLS7 - 0
Tab le 21. SPI SFRs
MnemonicAddName 76543210
SPCON(1) C3h Serial Peripheral Control SP R2 SP EN SSDIS MSTR CPOL CPHA SP R1 SP R0
SPSTA(1) C4h Serial Peripheral Status-
Control SPIF WCOL MODF
SPDAT(1) C5h S erial Peripheral Data R7 - 0
Tab le 22. USB SFRs
MnemonicAddName 76543210
USBC ON BCh U SB Globa l Control USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN
USBA DDR C6h USB Addre ss FEN UADD 6-0
USBI NT BDh USB Global Interru pt WUPCPU EORINT SOFINT SPINT
USBIEN BEh USB Global Interrupt
Enable EWUPCPU EEORINT ESOFINT ESPINT
UEPN UM C7 h USB Endpo int Number EPNUM3-0
UEPC ONX D 4h U SB Endpoin t X Control EPEN NA KIEN NA KOU T NAK IN DTGL EPDI R EPTYPE1 EPTYPE0
UEPS TAX CEh U SB Endpo int X Status DIR RXO UTB1 STALLRQ TXRDY STL/CRC RXS ETUP RX OUTB0 T XCMP
UEPR ST D5h USB Endpoin t Reset EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST
UEPI NT F8h USB Endpo int Inte rrupt EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
40
AT8xC5122/23
4202E–SCR–06/06
Note: 1. Only for AT8 xC5122
UEPIEN C2h USB Endpoint Interrupt
Enable EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE
UEPDATX CFh USB Endpoint X Fifo Data FDAT7 - 0
UBYCTX E2h USB Byte Cou nter Low
(EPX) BYCT6-0
UFNUML BAh USB Frame Numb er Low FNUM7 - 0
UFNUMH BBh USB Frame Number High CRCOK CRCERR FNUM10-8
Tab le 22. USB SFRs
MnemonicAddName 76543210
Tab le 23. LED SFRs
MnemonicAddName 76543210
LEDC ON0 F1h LED Control 0 L ED3 LED2 LED1 LED0
LEDCON1(1) E1h LED Contro l 1 LED6 LED5 LED4
41
AT8xC5122/23
4202E–SCR–06/06
Clock Co ntroller The clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock
Loop (PLL). All the int ernal clocks to t he CPU core and peripher als are generated by thi s
controller.
On-Chip Oscillator The on-chip oscillator is composed of a single-stage inverter and a parallel feedback
resistor. The XTAL1 and XTAL2 pins are respectively the input and the output of the
inverter, which can be configur ed with off-chip components as a Pierce oscillator (see
Figure 16).
The on-chip osc illator has been desi gned and optim ized to work with an external 8 MHz
crystal and very few load capacitance. Then external load capacitors are not needed
given that :
– the i nternal capacitance of the mic rocontroller and the stray capacit ance of
circuit board are enough to ensure a stable oscil lation
– a very high accuracy on the oscillation frequency is not n eeded
The circuit works on its funda men tal frequency at 8 MHz.
Fi gure 16. Oscillator Schematic
C1 and C2 rep resents the internal capacitance o f the microcontroller and the stray
capa citance of the circuit board. It is recommended to implement the crystal as close as
possi ble from the microcontroller pack age.
Quartz Specification T he equival ent circuit of a crys tal is repres ented on the figure below :
The Eq uivalent Serial Resistance R1 must be lower th an 100 Ohm.
Feedback
Resistor
XTAL1 XTAL2
8 MHz
GND GND
Microcontroller
C1 C2
To internal
clock circ uitry
L1 C1 R1
C0
42
AT8xC5122/23
4202E–SCR–06/06
Pha se Lock Loo p (P LL)
PLL D escript io n The AT8xC5122/23’s P LL is used to generate internal high frequency clock synchro-
nized with an external low-frequency. Figure 17 show s the internal structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. T his block
make s the com parison bet ween the ref erence c lock comi ng from the N divi der and th e
reverse clock coming from the R divider and generates so me pulses on the Up or Down
signal depending o n the edge po sition of the reverse c lock. The PLL EN bit in PLLCON
register is used to enable the clock gen eration. When the PLL is locked, the bi t PL OCK
in PLLCON register is set.
The CHP block i s t he Charge Pump that generates the voltage reference for the VCO by
injecting or e xtracting char ges from the extern al filter conne cted on PLLF pin (se e
Figure 18). Value of the filter components are detailed in the Section “DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF pro-
duced by the charge pump . It gene rates a square wa ve signal: the PLL clock. The
CK_PLL f requency is defined by the follw ing formula:
FCK_PLL = FCK_XTAL1 * (R+1) / (N+1)
Fi gure 17. PLL Block Diagram and Symbol
Fi gure 18. PLL Filte r Valu e
PLL P rogramm i ng The P LL m ust be prog ramm ed to work at 96 MH z freque ncy by mea ns of PL LCON a nd
PLLDIV registers. As soon as the PLL is enabled, the firmware must wait for the lo ck bit
status to ensure that the P LL is ready.
PLLEN
PLLCON.1
N3:0
N Divider
R divider
VCO CK_PLL
CK_XTAL1 PFLD
PLOCK
PLLCON.0
PLLF
CHP VREF
Up
Down
R3:0
VSS
PLLF
VSS
1,8
K
Ω
150 pF
33 pF
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Fi gure 19. PLL Program ming Flow
Clock Tree Architecture The clock controller outputs several different clocks as shown in Figure 20:
• a clock fo r the C PU core
• a clo ck for the p eripherals which is used to generate the timers, watchdog, SPI,
UART, and ports sampli ng cloc ks. This divided clock will be used to generate the
alternate card clock.
• a clock for the U SB
• a clock for the SCIB controller
• a clo ck for the DC/DC converter
These clocks are enab led or not dep ending on th e power redu ction mode as detailed in
Section “Power Management”, page 180.
These cloc ks are generated using four presacal ers defined in the table b elow:
PLL
Programming
Configure Divider s
N3:0= xxxxb
R3:0= xxxxb
Enable PLL
PLLEN= 1
PLL Locked?
PLOCK= 1?
Prescaler Register Rel oad Fact or Function
PR1 CKRL CKRL[0: 3] CPU & Peripheral clocks
PR2 SCICLK SCICLK[0:5] Smart card
PR3 SCSR ALTKPS[0:1] Alter nate card
PR4 DCCKPS DCCKPS[3:0] DC/DC
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Figu re 20. Clock Tree Diagram
CPU and Peripheral Clocks T wo clocks sourc es are available for CPU and peripherals:
– o n- c h ip o s c illat o r
– a derivative of the PLL c lock.
These clock sources are configured by the PR1 prescaler to generate the CPU core
CK_CPU and the peripheral clocks:
– CK_ IDLE for alternate card and peripherals registers access
–CK_T0 for Timer 0
–CK_T1 for Timer 1
– CK_SI fo r th e UA RT
– CK_ WD for the Watchdog Timer
– CK_SPI for SPI
Alternate
Card
XTAL1
XTAL2
PD
PCON.1
96 MHz
EXT48
PLLCON.2
0
1
0
1
CKS
CKSEL.0
0
1
X2
CKCON0.0
PR1
CKRL[3:0]
IDL
PCON.0
DC/DC
PR4
PR2
CK_IDLE
PR3
Converter
1/2 CK_USB
0
1
CK_ISO
CK_CPU
CK_XTAL1
CK_PLL
DCCKPS[3:0]
SCICLK[5:0]
SCSR[3:2]
1
0
PeriphX2
CKCON0.X or
1
0
X2
CKCON0.0
CK_T0
Peripherals
CK_T1
CK_SI
CK_WD
CK_SPI
CK_PERIPH
CK_IDLE
CK_IDLE
PLLEN
PLLCON.1
CK_XTAL1
CK_PLL
CK_PLL
CK_XTAL1
CK_XTAL1
PERIPH = T0, T1, SI, WD or SP
I
CKCON1.0
XTSCS
SCICLK.7
CPU
SCIB
USB
PLL
CK_DCDC
1/2
SCICLK[5:0]
=48
<48
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The CPU and peripherals clocks frequencies are defined in the table below.
X1 and X2 Modes Use of on-chip os cill ator
W hen th e CP U a nd P eri phe rals cl ock s are fe d b y th e on -chi p osci lla tor, the CP U an d
Peripherals can be configured independently in X1 or X2 mode depending on the fre-
quencies wanted by the user. There is however one exception : the periperals can be
configur ed in X2 mode while the CPU remains in X1 mode. This except ion is handled by
the hardware and the user does not need to take care of.
The X1 or X2 modes can be individually selected for the CPU and each peripheral by
me ans of CKC ON0 and CKCO N1 regist ers. At rese t, the C PU and Peri pherals a re set
all by default to X1 mode. In this m ode, changing any peripheral to X2 mode has no
ef fec t. Wh en X2 bit is se t i n CK CON 0 reg iste r, C PU an d Al l pe riph eral s are au toma ti-
cally switched to X2 mode. It is then possible for the user to individually switch any
peripheral back to X1 mode.
In X1 m ode (X2 bit cleare d in CKCON0 reg site r), the PR 1 prescale r is a ctive while it is
bypas sed in X2 mode (X2 bit set in CKCON0 r egister).
The X1 mode is true only when the prescaler PR1 is set to 1/2 (d efault condition at
reset).
CKS X2 FCK_IDLE
00F
CK_XTAL1/(2*(16-CKRL))
01F
CK_XTAL1
10F
CK_PLL/(2*(16-CKRL))
11Not allowed
Table 1. X1 and X2 Mode Selection
CPU Peripherals Status Frequenci
X1 mode X1 mode Allowed
(default configuration at reset) FCK_IDLE = FCK_PERIPH
X1 mode X2 mode Not Allowed by the hardware
X2 mode X1 mode
Allowed
On ce the CPU is swi t che d to X2
mode, the user is free to switch
any of the p eripherals to X1
mode
FCK_IDLE = 2*FCK_PERIPH
X2 mode X2 mode Allowed
Def aul t co nf igur a tion w hen C PU
is switched to X2 mode FCK_IDLE = FCK_PERIPH
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Fi gure 21. X1 mo de
When the X1 mode is selected, the CPU and Peripherals work at 8Mhz / X1
Fi gure 22. X2 mo de
When the X2 mode is selected, the CPU works at 8 MHz / X2. The Peripherals can work
at 8 MHz / X2 or 8 MHz / X1.
When the PR1 pres cal er is dif ferent from 1/2 , the usual X1 mode can not be defined. I n
this c ase, it is necess ary to define a X1 or X2 equivalent mode from equivalent clock
circuits.
Exam ple : PR1=1 /8, X2= 0.
In this configuration, the CPU works at 1 MHz. This frequency could also be obtained by
an equ ivalent cloc k circuit where t he on-chip o scillator woul d run at 2 MHz in X1 mod e
or at 1 MHz in X2 mode. So we can say that the CPU works at 2 MHz / X1 or 1MHz / X2.
As the X2 bit is cl eared in CKCON0 regist er, we have FCK_IDLE = FCK_PERIPH.
8 MHz 1/2
PR1 prescal er CPU frequency
4 MHz
4 MHz
Peripheral frequency
Crystal
8 MHz
CPU frequency (X2 Mode)
8 MHz
8 MHz
Peripheral frequency (X2 mode
)
4 MHz
1/2
Peripheral frequency (X1 mode
)
Internal Presca ler
Crystal
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Use of PL L Clock W hen the CPU clock is fed by the PLL, the X2 mode is forbidden. The bit X2 must
always rem ain c leared in CKCON0 register. As the PR1 prescaler is always different
from 1/2, the usual X1 mode c an not be defined. S o it is neces sary to defi ne an eq uiva-
lent X1 or X2 m ode from equivalent clock circuits , as in previous section.
Ex amp le: P R1= 1/4 , PL L feed s th e C PU. T he C PU work s in this c ase at 2 4 MH z. Thi s
frequen cy could also be ob tained by an equivalent c lock c ircuit whe re th e on-c hip osc il-
lator woul d run at 48 MHz in X1 m ode o r at 24 Mhz in X2 mod e. So we c an say that in
this configuration, the CPU works at 48 MHz / X1 or 24 M Hz / X2 (See figures below).
As the X2 bit is cl eared in CKCON0 regist er, we have always FCK_IDLE = FCK_PERIPH.
8 MHz
CPU freque ncy
1 MHz
1/8
PR1 Prescal er
(Equivalent to)
2 MHz 1/2
External Clock X1 mode selec te d
PERIPH frequency
1 MHz
CPU freque ncy
1 MHz
PERIPH frequency
1 MHz
(Equivalent to)
1 MH z X2 mode selected CPU frequency
1 MHz
PERIPH frequency
1 MHz
Crystal
External Clock
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SCIB Clock The Smart Card Interface Block (SCIB) uses two clocks :
– The first one, CK_IDLE, is the peripheral clock used for the interface with the
microcontroller.
– The second one, CK_ISO, is independan t from the CPU clock and is
generated from the PLL or XTAL1 output.
PR2, a 6-bit prescaler, will be us ed to generate:
12/9.6/8/6.85/6/5.33/4.8/4.36/ ..../1MHz frequencies.
SCIB clock frequency must be lower than CPU clock frequ ency.
During S CIB Re set, the CK _ISO input m ust be in the range 1 - 5 M H z acc ording to ISO
781 6. The SC IB clocks freq uency is defined in Figure 42 on page 74 and Table 42 on
page 74.
Two conditions must be met for a correct use of the SCIB:
• CK_CPU > 4/3 * CK_ISO and
• CK_CPU < 6 * CK_ ISO.
96 MHz
CPU frequency
24 MHz
PLL
1/4
Prescaler
48 MHz 1/2
External Clock CPU frequency
24 MHz
(Equivalent to)
X1 mode selected
24 MHz
CPU frequency
24 MHz
(Equivalent to)
X2 mode selected
PERIPH fr equency
24 MHz
PERIPH fr equency
24 MHz
P ERIPH fr equency
24 MHz
External Clock
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If the CK_CPU <= 4/3 * CK_ISO, the SCIB doesn’t work.
If the CK_CPU >= 6* CK_ISO, the programmer m ust take care in three cases:
• Read (or write) operation on a S CIB register f ollowed im mediatl y with an ot her Read
(or write) operation on the same register.
• Read (or write) operation on a S CIB register f ollowed im mediatl y with an ot her Read
(or write) operation on a linked register. The list of l inked regist ers is in the table
below.
• Write operation on a register of the list below followed immediatly with a read
operation on a SCIB register.
To avoid any trouble, a delay must be added between the tw o ac cesses on the SCIB
register. The S CIB must compl ete the first read (or write) operation before to receive the
second. A solut ion is to add NOP (no operation) instruct ions. The number of NOP to add
depends of the rate between CK_CPU and CK_IS O (see table below).
Alternate Card Clock The alternat e C ard uses the peripheral clock divided by the PR3 pr escaler. (1; 1/2; 1/4;
1/ 8 divisi on ratio ). See Section " Alterna te Ca rd", pa ge 78 for t he de finition of the alte r-
nate clock.
DC/DC Converter Clock The DC/DC block needs a clock with a 50% duty cycle. T he frequency must also be
included in t he ran ge 3. 68 M Hz an d 6 M H z. The P R4 presc aler is used t o configure the
DC/DC frequency.
Linked registers
Write in SCICR and after read of SCETU0-1
Writ e in SCI BUF and after read of SCISR
Wait af ter W rite operation on this regi sters
SCICR, SCIER, SCETU0-1,SCGT0-1,
SCWT0-3,SCCON
Min CLK_CPU Max CLK_CPU Number of
CPU cycles to add
CLK_CPU >= 6 * CLK_ISO CLK_CPU <= 12 * CLK_ISO 6 ( example1 NOP)
CLK_CPU >= 12* CLK_ISO CLK_CPU <= 16 * CLK_ISO 12 ( exa mp le 2 NOP)
XTAL1 (M Hz) DCCKPS3:0 value Prescale r Factor DC/DC converter CLK (MHz)
802 4
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USB Interface Cl ock The USB Interface uses two clocks :
– The first one is the CPU clock used for the interface with t he microcontroller,
CK_IDLE.
– The second one is the CK_US B supplied from the PLL through a divider by
2.
Registers
Reset Value = XXXX XXX0b
Reset Value = XXXX 1111b
Table 24. Clo ck Se lection Register - C KSEL (S:85h)
76543210
-------CKS
Bit Number Bit Mnemonic Description
7:1 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
0CKS
CPU Oscillator Select Bit
Set this bit to connect CPU and Peripherals to PLL output.
Clear this to to connect CPU and Peripherals to XTAL 1 cloc k input.
Table 25. Clock Reload Register - CKRL (S:97h)
76543210
- - - - CKRL3 CKRL2 CKRL1 CKRL0
Bit Number Bit Mnemonic Description
7 - 4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3:0 CKRL3:0 Clock Reload register
Pr esca le r 1 va lu e
Fck_cpu =[ 1 / 2* (16-CKRL)] * F ck_XTAL1
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Rese t Value = X0X0 X000b
Table 26. Clock Configuration Register 0 - CKCON0 (S:8F h)
76543210
-WDX2- SIX2 - T1X2T0X2X2
Bit Number Bit Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6WDX2
Watchdog clock
This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit ha s no effec t.
Cleared to bypass the PR1 prescaler.
Set to s e lec t the PR1 output for th is peripheral.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4SIX2
Enhance d UART clock (Mode 0 and 2)
This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit ha s no effec t.
Cleared to bypass the PR1 prescaler.
Set to s e lec t the PR1 output for th is peripheral.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2T1X2
Timer 1 cloc k
This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit ha s no effec t.
Cleared to bypass the PR1 prescaler.
Set to s e lec t the PR1 output for th is peripheral.
1T0X2
Timer 0 cloc k
This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit ha s no effec t.
Cleared to bypass the PR1 prescaler.
Set to s e lec t the PR1 output for th is peripheral.
0X2
System clock Control bit
Cleared to select the PR1 output for CPU and all the peripherals .
Set to by pa ss t he PR1 p resc al er an d t o en ab le th e in di vi dual pe ri pher a ls ‘X2’
bits.
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Reset Value = XXXX XXX0b
Rese t Value = 0000 0000b
Rese t Value = 0000 0000b
Table 27. Clock Configuration Register 1 - CKCON1 (S:A Fh) only for AT8xC5122
76543210
-------SPIX2
Bit Number Bit Mnemonic Description
7 - 4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 SPIX2
SPI clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit ha s no effec t.
Cleared to bypass the PR1 prescaler.
Set to s e lec t the PR1 output for th is peripheral.
Table 28. PLL Cont rol Register - PLLCON (S:A 3h)
76543210
- - - - - EXT48 PLLEN PLOCK
Bit Number Bit Mnemonic Description
7 - 3 - Reserved
The value read f rom th ese bits i s alway s 0. Do not set this bits.
2 EXT48
External 48 MHz Enable Bit
Set this bi t to select XTAL1 as USB clock.
Clear this bit to select PLL as USB clock.
SCIB clock is controlled by EXT48 bit and XTSCS bit.
1PLLEN
PLL Enable bit
Set to enable the PLL.
Clear to disable the PLL.
0PLOCK
PLL Lock Indicator
Set by hardware when PLL is locked
Clear by hardware when PLL i s unlocked
Table 29. PLL Divider R egister - PLLDIV (S:A4h)
76543210
R3 R2 R1 R0 N3 N2 N1 N0
Bit Number Bit Mnemonic Description
7 - 4 R3:0 PLL R Divider Bits
3 - 0 N3:0 PLL N Divider Bits
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I/O Port Definition
Ports vs Pa ckages Table 30. I/O Number vs P ackages
Port 0 Port 0 has the follo wing functions:
– Default function: Port 0 is an 8-bit I/ O port.
– Alternat e function: Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data Memory. In this
application, it uses strong internal pull-ups when emitting 1’s and it can drive
CMOS input s without ext ernal pull-ups.
Port 0 has the follo wing configurations:
– Default configuration: open drain bi-directional I/O port. Port 0 pins that have
1’s written to them float, and in this state th ey can be used as high-
impedance inpu ts.
– Configuration 2: Low speed output, “KB_OUT”
– Configuration 3: Push-pull output
P0 P1 P2 P3 P4 P5 Total
VQFP64
QFN64 88886846
VQFP32
QFN32 -8-8-117
PLCC28-6-6-113
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Port 1 Port 1 has the follo wing functions:
– Default function : Only Port 1.2, P1. 6 and P1.7 are standard I/ O’ s; the ot her
ports can be activated only with the SCIB function.
– Alterna te function and configu ration: see Ta ble 31.
Table 31. Port 1 Description .
Port 2 Port 2 has the follo wing functions:
– Default function: Port 2 is an 8-bit I/ O port.
– Alternat e function 1: Port 2 is also the multiplexed high-order address during
accesses to external Program and Data Mem ory. In this application, it uses
strong internal pull-ups when emitting 1’s a nd it can drive CMO S inpu ts
without external pull-ups.
Port 2 has the follo wing configurations:
– Default configuration: Pseudo bi-directional “Port51” digital input /output with
internal pull-ups.
– Configuration 1: Push-pull output
– Configuration 2: Low speed output, “KB_OUT
– Conf iguration 3: Input with weak pull-up, “WPU input”
Port
Alternate Function Configuration
Signal Description Mode Comments
CIO Smart card in terface function
Card I/O Qua s i-bi directional port s upplied by
DC/DC converter
Low level at reset .
Caution : if DPU bit is set in AUXR regis te r, the
weak-pull of the port is disabled
CC8 Smart ca rd interface function
Car d contact 8 Quasi-bidi rectional port supp lied by
DC/DC converter
Low level at reset
Caution : if DPU bit is set in AUXR regis te r, the
weak-pull of the port is disabled
P1.2 CPRES Smart card interface function
Card presence Quasi-bidi rectional port supp lied by VCC Weak & medium pull-up’s can be disconnected
by CPRESRES bit in PMOD0 regsiter
Hig h Leve l at res et
CC4 Smart ca rd interface function
Car d contact 4 Quasi-bidi rectional port supp lied by
DC/DC converter
Low level at reset
Caution : if DPU bit is set in AUXR regis te r, the
weak-pull of the port is disabled
CCLK Smart card interfa ce function
Card clock Push-Pull port supplied by DC/DC
converter Low level at reset
CRST Smart card interface function
Card re set Push-Pull port supplied by DC/DC
converter Low level at reset
P1.6 SS SS pin of the SPI function Quasi-bidirectional supplied by VCC
P1.7 CCLK1 Alternate Card Clock output
Qua s i-bi directional supplied by VCC Alternate C ard Clock function disabled
Quasi-bidirectional supplied by VCC Al ternat e Sm ar t C ard Cl oc k en able d
Switched automatically t o Push-pull (see Table
47 on page 82 )
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Port 3 Port 3 has the follo wing functions:
– Default function: Port 3 is an 8-bit I/ O port.
– Alterna te functions: see table below
Port 3 has the follo wing configurations:
– Default configuration: Pseudo bi-directional “Port51” digital input /output with
internal pull-ups.
– Alterna te configurations: See Table 32.
Table 32. Port 3 Description
Port
Alterna te Functions Configurations
S ign al De sc ripti on Mod e 1 M ode 2 Mod e 3 Mode 4
P3.0 RxD Receiver data input (asynchronous) or data input/output
(sync hronous) of the serial interface P us h-pu ll KB_ O U T I np ut W PU
P3.1 TxD Transmitter data output (asynchronous) or clock outpu t
(sync hronous) of the serial interface P us h-pu ll KB_ O U T I np ut W PU
P3.2 INT0 External interrupt 0 input/timer 0 gate control input LED0
P3.3 INT1 External interrupt 1input/timer 1 gate control input Push-pull KB_OUT Input WPU
P3.4 T0 Timer 0 counter input Push-pull KB_OUT Input WPU L ED1
P3.5 T1 Timer 1 counte r inpu t
P3.6 WR External Data Memory write strobe; latches the data byte
from port 0 into the external data memory LED2
P3.7 RD External Data Memory read strobe; Enables the external
dat a me mory. Por t 3 can dr i ve CMOS in pu ts w itho ut exte r na l
pull-ups LED3
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Port 4 Port 4 has the follo wing functions:
– Default function: Port 4 is an 6-bit I/ O port.
– Alterna te functions: see table below
Port 4 has the follo wing configurations:
– Default configuration: Pseudo bi-directional “Port51” digital input /output with
internal pull-ups.
– Alterna te configurations: See Table 33.
Table 33. Port 4 Description
Port 5 Port 5 has the follo wing functions:
– Default function: Port 5 is an 8-bit I/ O port.
– Alterna te function 1: Port 5 is an 8-bit keyboard port KB0 to KB7.
Port 5 has the follo wing configurations:
– Default configuration: Pseudo bi-directional “Port51” digital input /output with
internal pull-ups.
– Alternat e configuration: see Table 34.
Table 34. Port 5 Description
Port
Alternate Fun ctions Configurations
Signal Description Mode 1 Mode 2 Mode 3
P4.0 MISO SPI Master In Slave Out I/O
P4.1 MOSI SPI Master Out Slave In I/O
P4. 2 SCK SPI clock
P4 .3 Push-pull KB_OUT Input MPU
P4 .4 Push-pull KB_OUT Input MPU
P4 .5 Push-pull KB_OUT Input MPU
Port
Configurations
Mode 1 Mode 2 Mode 3 Comments
P5.0 Push-pull Input MPU Input WPU
First clusterP5.1 Push-pull Input MPU Input WPU
P5.2 Push-pull Input MPU Input WPU
P5.3 Push-pull I nput WPD Input WPU Second cluster
P5.4 Push-pull I nput WPD Input WPU
P5.5 Push-pull I nput WPD Input WPU
P5.6 Push-pull I nput WPD Input WPU Third cluster
P5.7 Push-pull I nput WPD Input WPU
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Port Configuration
Standard I/O P0 The P0 port is described in Figure 23.
Fi gure 23. Standard Input/Ou tput Port
Quasi Bi-directional Port The default port output configuration for standard I/O ports is the quasi-bi-directional
output that is common on the 80C51 and most of its derivatives. The “Port51” output
type can be us ed as bot h an inpu t and out put witho ut the nee d to recon figure th e port.
This is possible because when t he port outputs a logic high, it is weakly driven, allowing
an external device to pull the pin lo w.
When the port outputs a logic low state, it is driven strongly and is able to sink a fairly
large current.
These feat ures are s omewhat similar to an open-drain output except that there are three
pull-up transis tors in the quasi-bi-directional output that serve differe nt purposes.
One of these pull-ups, called the wea k pull-up, is t urned on whe never the port latch for
the pin contains a logic 1. The weak pull-up sources a very small current that will pull the
pin hi gh if it is left floatin g. The weak pull-up ca n be turned of f by the DPU b it in A UXR
register.
A second pull-up, called the medium pull-up , is turned on when t he port latch for the pin
contains a logic 1 and the pin itself is also at a logic 1 level. This pull- up provides the pri-
mary source current for a quasi-bi-directional pin that is out putting a 1. If a pin that has a
logic 1 on it is pulled low by an external device, the medium pull-up turns off, and only
the weak pull-up remains on. In order to pull the pin low under these conditions, the
ex ternal dev ice h as to sink eno ugh c urre nt to o ver power the medi um pull- up an d ta ke
the voltage on the port pin below its input thresh old.
Note: for CIO, CC4, CC8 ports of SCIB interface , in input mode when the ICC (sm art card) is
driving the port pin :
– if 0 < Vin < CVCC/2 : weak pull-up is active (~100K Ohm )
– if CVCC/2 < Vin < CVCC : weak (~100K Oh m) and me dium (~12KOhm ) pull-
up’s are active
MUX
Pin
ADDR/DATA CONTROL Vcc
1
0
Input
Data
Port latch
Data
PMOS
NMOS
Vss
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The “Port51” is des cribed in Figure 24.
Fi gure 24. Quasi Bi-directional Port
Pus h-pu ll Ou t p ut
Configuration The push-pull output configuration has the same pull-down structure as both the open
dr ain and the quas i-bi- direct ional out put mod es, bu t provid es a co ntin uous stro ng pul l-
up when the port latc h cont ains a logi c 1. The pus h-pull m ode m ay be used whe n m ore
source current is needed from a port output.
The Pu sh-pull port configuration is shown in Fig ure 25.
Fi gure 25. Push-pull Output
Input with Medium or Weak
Pull-up Configuration The input with pull-up (Input MPU and Input WPU) configuration is shown in Figure 26.
2 CPU
Input
Pi
n
Strong Weak Medium
N
PP
P
CLOCK DELAY
Port Latc h
Data
Data
DPU (AUXR.7)
Vss
vcc vcc vcc
Pin
Strong
N
P
Port latch
Data
PMOS
NMOS
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Fi gure 26. Input with Pull-up
Input with Weak Pu ll-down
Configuration The input with pull-down (input WPD) configuration is shown in Figure 27
Fi gure 27. Input with Pull -down
Low Speed Output
Configuration The low speed output with low speed tFALL and tRISE c an drive keyboard.
The current limit ation of the LED2CTRL block requires a polarisation current of about
250 µA. This block is automat ically disabled in power- down mode.
The low speed output configuration (K B_OUT ) is shown in Figure 28.
Fi gure 28. Low-speed Output
LED So ur c e Cu rrent The LE D configuration is shown in Figure 2 9.
Input
Pin
Data
Weak
P Medium
P
Stuck to 0 if Medium
Stuck to 0 if Weak
Input
Pin
Data
Weak
N
1
Pin
P
PWEAKCTRL
Port latch
Data N
N
NMOS
PCON.1
Weak
LED2CTRL
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Fi gure 29. LED Source Current
Notes: 1. When switching a low lev el, LEDCTRL devi ce has a perm anent current of about
N mA/15 (N is 2, 4 or 8).
2. The port must be configured as standard C51 port by means of PMOD 0 and PMOD1
regist er s and the level of cur rent must be programmed by means of LEDCON0 and
LEDCON1 register s before switching the led on.
Table 35. LED Source Current
LEDx.1 LEDx.0 Port Latch Data NMOS PIN Comments
00 0 10
LE D co ntrol di sa bled
00 1 01
01 0 00LED mode 2 mA
01 1 01
10 0 00LED mode 4 mA
10 1 01
11 0 00
LED mode 10 mA
11 1 01
Pin
Port Lat ch
Data
LEDx.0
LEDx.1
NMOS N
N
LEDCTRL
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Registers
Rese t Value = 0000 0x00b
Reset Value = 00xx 0xxxb
Table 36. Port Mode Register 0 - P M OD0 (91h) for AT8xC5122
7654 3 210
P3C1 P3C0 P2C1 P2C0 CPRESRES - P0C1 P0C0
Bit Number Bit Mn emonic Description
7 - 6 P 3 C 1-P3C0
Port 3 Configuration bits (Applicable to P3.0, P3.1, P3.3, P3.4 only)
00 Quasi bi-direc tional
01 Push-pull
10 Outp ut Low Spe ed
11 Input with weak pull-up
5-4 P2C1-P2C0
Port 2 Configuration bits
00 Quasi bi-direc tional
01 Push-pull
10 Outp ut Low Spe ed
11 Input with weak pull-down
3 CPRESRES Card Presence Pull-up resistor
Cleared to connect the internal 100K pull-up
Set to disconnect the internal pull-up
2-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1-0 P0C1-P0C0
Port 0 Configuration bits
00 C51 Standard P0
01 Reserved
10 Outp ut Low Spe ed
11 Push-pull
Table 37. Port Mode Register 0 - P M OD0 (91h) for AT83C5123
7654 3 210
P3C1 P3C0 - - CPRESRES - - -
Bit Number Bit Mn emonic Description
7 - 6 P 3 C 1-P3C0
Port 3 Configuration bits (Applicable to P3.0, P3.1, P3.3, P3.4 only)
00 Quasi bi-direc tional
01 Push-pull
10 Outp ut Low Spe ed
11 Input with weak pull-up
5-4 Reserved
The value read from these bits are indeterminate. Do not set these bit.
3 CPRESRES Card Presence Pull-up resistor
Cleared to connect the internal 100K pull-up
Set to disconnect the internal pull-up
2-0 - Reserved
The value read from these bits are indeterminate. Do not set these bit.
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Rese t Value = 0000 0000b
Reset Value = xxxx 00xxb
Table 38. Port Mode Register 1 - P M OD1 (84h) for AT8xC5122
76543210
P5HC1 P5HC0 P5MC1 P5MC0 P5LC1 P5LC0 P4C1 P4C0
Bit Number Bit Mnemonic Description
7 - 6 P5HC1-P5HC0
Port 5 High Configuration bits (Applicable from P5.6 to P5.7 only)
00 Quasi bi-direction al
01 Push-pull
10 Input with weak pull-down
11 Input with weak pull-up
5 - 4 P5 MC1-P5M C0
Port 5 Medium Configuration bits (Applicable from P5.3 to P5.5 only)
00 Quasi bi-direction al
01 Push-pull
10 Input with weak pull-down
11 Input with weak pull-up
3 - 2 P5L C1- P5 L C 0
Port 5 Low Configuration bits (Applicable from P5.0 to P5.2 only)
00 Quasi bi-direction al
01 Push-pull
10 Input with medium pull-up
11 Input with weak pull-up
1 - 0 P4C1-P 4 C 0
Port 4 Configuration bit s (Applicable from P4.3 to P4.5 only)
00 Quasi bi-direction al
01 Push-pull
10 Outp ut Low Spe ed
11 Input with medium pull-up
Table 39. Port Mode Register 1 - P M OD1 (84h) for AT83C5123
76543210
----P5LC1P5LC0--
Bit Number Bit Mnemonic Description
7 - 4 Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 - 2 P5L C1- P5 L C 0
Port 5 Low Configuration bits (Applicable from P5.0 to P5.2 only)
00 Quasi bi-direction al
01 Push-pull
10 Input with medium pull-up
11 Input with weak pull-up
1 - 0 Reserved
The value read from this bit is indeterminate. Do not set this bit.
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Rese t Value = 0000 0000b
Rese t Value = 0000 0000b
Table 40. LED Port Control Register 0 - LEDCON0 (F1h)
76543210
LED3.1 LED3.0 LED2.1 LED2.0 LED1.1 LED1.0 LED0.1 LED0.0
Bit Number Bit Mnemonic Description
7 - 6 LED3
Port LED3 Co nfig urat ion bit s
00 LED control disabled
01 2 mA current source when P3.7 is configured as Quasi-bi-directional mode
10 4 mA current source when P3.7 is configured as Quasi-bi-directional mode
11 10 mA current source when P3.7 is config ured as Quasi-bidirect. mode
5 - 4 LED2
Port LED2 Co nfig urat ion bit s
00 LED control disabled
01 2 mA current source when P3.6 is configured as Quasi-bi-directional mode
10 4 mA current source when P3.6 is configured as Quasi-bi-directional mode
11 10 mA current source when P3.6 is config ured as Quasi-bidirect. mode
3 - 2 LED1
Port LED1 Co nfig urat ion bit s
00 LED control disabled
01 2 mA current source when P3.4 is configured as Quasi-bi-directional mode
10 4 mA current source when P3.4 is configured as Quasi-bi-directional mode
11 10 mA current source when P3.4 is config ured as Quasi-bidirect. mode
1 - 0 LED0
Port LED0 Co nfig urat ion bit s
00 LED control disabled
01 2 mA current source when P3.2 is configured as Quasi-bi-directional mode
10 4 mA current source when P3.2 is configured as Quasi-bi-directional mode
11 10 mA current source when P3.2 is config ured as Quasi-bidirect. mode
Table 41. LED Port Control Register 1- LEDCON1 (F1h) only for AT8xC5122
76543210
- - LED6.1 LED6.0 LED5.1 LED5.0 LED4.1 LED4.0
Bit Number Bit Mnemonic Description
7 - 6 Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 - 4 LED6
Port LED6 Co nfig urat ion bit s
00 LED control disabled
01 2 mA current source when P4.5 is configured as Quasi-bi-directional mode
10 4 mA current source when P4.5 is configured as Quasi-bi-directional mode
11 10 mA current source when P4.5 is config ured as Quasi-bidirect. mode
3 - 2 LED5
Port LED5 Co nfig urat ion bit s
00 LED control disabled
01 2 mA current source when P4.4 is configured as Quasi-bi-directional mode
10 4 mA current source when P4.4 is configured as Quasi-bi-directional mode
11 10 mA current source when P4.4 is config ured as Quasi-bidirect. mode
1 - 0 LED4
Port LED0 Co nfig urat ion bit s
00 LED control disabled
01 2 mA current source when P4.3 is configured as Quasi-bi-directional mode
10 4 mA current source when P4.3 is configured as Quasi-bi-directional mode
11 10 mA current source when P4.3 is config ured as Quasi-bidirect. mode
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Smart Card Interface
Block (SCIB) The SCIB provides all signals to interface direct ly with a smart card. The compliance
with the ISO781 6, EMV’2 000, GSM and WHQL standards has been certified.
Both synchronous (e.g. memory card) and asynchronous smart c ards (e.g. micropro-
cessor card) are supported. The component suppli es the di fferent voltages requested by
the smart card. The power off sequence is directly manage d by the SCIB.
The card presence swi tch of the smart card connector is used to detect card insertion or
card remo val. In case of card removal, the SCIB de-activates the smart card using the
de-activation sequence. An interrupt can be generated when a card is inserted or
removed.
Any malfun ction is reported to th e microcontroller (interrupt + control register).
The differen t operating modes are configured by internal registers.
• Support of ISO/IEC 7816
• character mode
• one transmit/r ecei ve buffer
• 11 bits ETU counter
• 9 bits guard time counter
• 32 bits waiting time counter
• Auto character repetition on error sign al detection in transmit mode
• Auto error signal generation on parity error de tection in receive mode
• Power on and power off sequence generation
• Manual mode to drive directly the card I/O
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Block Diagram
The Smart Card Interface Block diagram is shown Figure 30:
Fi gure 30. SCIB Block Diagram
Definitions T his pa ra graph i ntrodu ces so me of the terms used in ISO 78 16-3 and EMV recom m en-
dations . Please refer to the full recommendat ion s for a complete list of terms.
Ter min al and ICC Terminal is the reader, ICC is the Integrated Circuit Card
ETU Elementary Timing Unit (Bit time)
T=0 Character oriented half d uplex protocol T=0
T=1 Block oriented half duplex protocol T=1
Activation: Cold Reset Re set initiated by the Term inal with Vcc power-up. Th e card will answer with ATR (see
below)
Activation: War m Reset Reset initiated by the Terminal with Vcc already powered-up, and after a prior ATR or
Warm Reset
De-Activation De activation by the Terminal as a result of : unresponsive ICC, or ICC remo val.
B arrel s hifter
Scart
fsm
Interrupt generator
Power on
Power off
fsm
I/O
mux
IO (in)
IO (out)
CLK
RST
C 4 (o u t)
Clk_iso
C8 (out)
C4 (in)
C8 (in)
W aiting tim e counter
Guard time counter
VCARD
INT
Clk_cpu
Etu counter
SCI R e gisters
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ATR A nswer To Reset . Response from the ICC to a Reset initiated by the Te rminal
F and D F = Clock Rate Conv ersi on F acto r, D = B it rat e ad justm ent fa ctor . ETU is de fined as :
ET U = F/(D*f) w ith f = Card Cloc k freque ncy. If f is i n Hertz, ETU is in second. F and D
are available in the ATR (byte TA1). The default values are F=372, D=1.
Gua rd Time Th e ti me betw een 2 lea din g edg es of th e sta rt b it o f 2 c onsec uti ve char act ers is com -
prised of the charac ter dura tion (10) plus the guard time. B e aware that the Guard Tim e
count er and t he Guard Time regi sters i n the AT8xC5122/23 consider the tim e between 2
con secutive charac ters. So the equation is Guard Tim e C ounter = Gu ard Time + 10 . In
ot her w or ds, the Gua rd Ti me is the n umb er of St op B its b etw ee n 2 ch ar acte rs s ent i n
the same direction.
Extra Gua rd Time ISO IEC 78 16-3 and EMV introduc e the E xtra Gua rd time to be adde d to the m inimum
Guard Time . Extra Gu ard Time onl y a pply to con secutive ch aracters s ent by the t ermi-
nal to th e ICC . The TC1 byte in the A TR def ine the num ber N. For N=0 the character to
character durati on is 12 E TUs. For N=254 the character to character duration is 266. For
N=255 (special case) The minimum character to character duration is to be used : 12 for
T=0 protoc ol and 11 for T=1 protocol.
Block Guard Time The time b etwee n the leadi ng edges of 2 cons ecutive characters s ent in op posit direc -
tion. ISO IEC 7816-3 and EMV recomme nd a fixed Block Guard Time of 22 ETUs.
Work Waiting Time (WWT) I n T=0 protocol WWT is the interval between the leading edge of any c haracter sent by
the ICC, and the leading edge of the previous c haracter sent either by the ICC or the
Term inal. If no char acter is r eceived b y the t erminal after W WTm ax time, t he Te rminal
initiates a De-Activation Sequen ce.
Character W aiting Ti me (CWT) In T=1 prot ocol CWT is the interval betwe en the leading edge o f 2 consec utive charac-
ters sent by the ICC. If the next character is not received by the Terminal after CWTmax
time, the Terminal initiates a De-Activation Sequence.
Block Waiting Ti me (BWT) In T =1 protoco l BWT is the interval betw een the leadi ng edge of th e start bit of the last
character sent by the Terminal that gives the right to sent to the ICC, and the leading
edge of the start bit of the first character sent by the ICC. If the first character from the
ICC is not received by the Terminal after BWTmax time, the Terminal initiates a De-Acti-
vation Sequence.
Waiting Time Extention (WTX) In T=1 p roto col th e ICC can req ues t a Wa iting Ti me Ex tens ion w ith a S (WTX requ est)
request. The Terminal should acknowlege it. The Waiting time between the leading
edge of the start bit of the last charact er sent by the Terminal that gives the right to sent
to the ICC, and the leading edge of the start bit of the first character sent by the ICC will
be BWT*WTX ETUs .
Parity error in T=0 protocol In T=0 protocol, a Term inal (respectively an ICC) det ecting a parity error while receiving
a character shall force the Card IO line at 0 starting at 10.5 ETUs, thus reducing the first
Gu ard bit by ha lf the t ime. Th e Ter min al (re spect ivel y an I CC) sh all mai ntain a 0 f or 1
ETU m in and 2 ETUs max (according to ISO IEC) or to 2 ETUs (according to EMV). The
ICC (respectively a Ter minal) shall monitor the Card IO to de te ct this error signal then
attemp t to repeat the character. Ac cordin g to EMV, following a parity e rro r th e character
can be repeated one time, if parity error is detected again this procedure can be
repeated 3 more times. The same character can be transmitted 5 times in total. ISO
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IEC7816-3 say s this procedure is mandatory in ATR for card su pporting T=0 while EMV
says this procedure is mandator y for T=0 but does not apply for ATR.
Functional Description The architecture of the Smart Card Interface Block can be detailed as follows:
Barrel Shifter The Barre l Shift er perform s the transl ation b etwee n 1 bit se rial da ta an d 8 bits pa ralle l
data
The barrel function is useful for character repetition since the character is still present in
the shifter at the end of the character transmission.
This shifter is able to shift the data in both directions and to invert the input or output
value in order to manage both direct and inverse ISO7816-3 conv ention.
Coupled with the barrel shifter is a parity checker and generator.
There are 2 regist ers conn ected to this barre l shifter, one for the tran smission a nd on e
for the reception. They act as buffers to rel ieve the CPU of timing co nstraints.
SCART FSM (Smart Card Asynchrono us Receiver Transmitter Finite State Machine)
This is the core of the block. It s purpose is to control the barrel shifter. To sequence cor-
rectly the barrel shi fter for a reception or a transmission, it uses the signals issued by the
different counters. One of the most important counters is the guard time counter that
gives time slots corresponding to the character frame.
The SCART FSM is enabled onl y in UART mode.
The transition from the receipt mode to the transmit mode is done automatically. Priori ty
is giv en to the tran smission. Transmi ssion refers to T erminal tr ansmission to the ICC.
Recept i on refers to reception by the Te rminal from the ICC.
ETU Counter T he ETU (Elementary Timing Unit) counter controls the working frequency o f the b arrel
shifter, in fact it generates the enable signal of the barrel shifter. It receives the Card
Clock, and generates the ETU cl ock. T he Card Clock frequenc y is called “f” below. The
ETU counter is 11 bit wide.
A special compensation mode can be activated. It accomodates situations where the
ETU i s not an inte ger number of Card Clock (CK_ISO). The compensation mode is con-
trolled by the COMP bit in SCETU1 register bit position 7. With COMP=1 the ETU of
ev ery c hara cter eve n bits i s redu ce d by 1 Car d C lock pe riod . As a resu lt, th e a verag e
ETU is : ETU_av er age = (ETU - 0.5). One should bear in mind that the ETU counter
should be programmed to deliver a faster ETU which will be reduced by the COMP
mechanism, not the other way around. This allows to reach the required precision of the
character duration specified by the ISO7816-3 standard.
Example1 : F=372 , D=32 => ETU= F /D = 11.625 clock cycles.
W e select ETU[10-0] = 12 , COMP=1. ET Uaverage= 12 - (0.5*COM P) = 11.5
The resul t will be a full charac ter duration (10 bit) = (10 - 0. 107)* ETU. The EMV spec ifi-
cation is (10 +/- 0.2 )*ETU
Gua rd Time C o unt er The minimum tim e between the l eading edge of the start bit of 2 consecutive characters
trans mitted by the Terminal is controlled by t he Guard Tim e count er, as described in
Figure 33.
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The Guard T ime counter is an 9 bit counter It is initialized at 001h at the start of a t rans -
mission by the Terminal. I t then increments itself at each ETU until it reach the 9 bit
value loaded into the SCGT 1[0] concatenated with SCGT 0[7:0]. At this time a new Ter-
mina l trans m ission i s enabled and the Gu ard T im e Counter stop increm enting. As so on
as a new transmission start, the Guard Time Counter is re-initialized at 1 decimal value .
It should be noted that the value of the Guard Time Count er c annot be red. Reading
SCGT1,0 only gives the minimum time between 2 characters that the Guard Time
Counter will allow.
C are mus t be ta ken w i th th e G uard T ime C o unter wh ich co unt s th e du rat ion betw ee n
th e lead ing ed ges of 2 cons ecut ive char acters. This corres pond to the ch ara cter dura-
tio n (10 ETU) pl us the Gu ard Time as d efine d by the IS O and E MV recom menda tions.
To program Guard Time = 2 : 2 s top bits between 2 characters which is equivalent to the
minimum delay of 12 ETUs between the leading edges of 2 consecutive characters,
SCGT1[0],SCGT0[7:0] should be loaded wit h the value 12 decimal. See Figure 31
Fi gure 31. Guard Time.
Bloc k Guard Time C o unt er The Bloc k Guard Time counter provides a way to program a min imum time between the
leading edge of the start bit of a character received from t he ICC and the leading edge of
the start bit of a character sent by the terminal. ISO IEC 7816-3 and EMV recomm end a
fix ed Blo ck Gu ard Ti me o f 22 ETUs . The AT 8xC512 2/23 offer th e po ssibil ity to exten d
this delay up to 512 ETUs.
The Bloc k Gu ard T ime is a 9 b it counter. When the Block Guard Time mode is enabl ed
(BGT EN =1 in SCS R registe r) The Block Guard Tim e count er is initialized at 000h at the
start of each character tra nsmi ssions from the ICC. It then increments at each ETU until
it reach the 9 bi t value loaded into shado w SCGT 1,0 registers, or until it is re-initialized
by the start of an ne w transmission from the ICC. If the Block Gua rd Time counter
reaches the 9 bit value loaded into shadow SCGT1,0 registers, a transmission by the
TERMINAL is enabled, and the Block Guard Time counter stop incrementing. The Block
Guard Time c ounter is re-initialized at the start of each TERMINAL transmission.
The SCGT1 SC GT 0 shadow registers are loaded with the cont ent of GT[8-0] c ontain ed
in the registers SCGT1[0),SCGT0(7:0] with the rising edge of the bit BGTEN in the
SCS R registe r. See Figure 33.
CHAR n+1 CHAR n+2 CHAR n+3
>= SCGT
TRANSMISSION to ICC
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Fi gure 32. Block Guard Time.
Fi gure 33. Guard Time and Block Gu ard Time counte rs
To illustrate the use of Guard Time and Block Guard Time, let us consider the
ISO/I EC7816-3 recommendation : Guard Time = 2 (minimum delay between 2 consecu-
tive characters sent by the Ter minal = 12 ETUs ), and Block Guar d Time = 22 ETUs.
After A smart Card Reset
– Write 00decimal in SCGT 1, Write 21decimal in SCGT 0
– Set BGTEN in SCSR (B GTEN was 0 before as a result of the smart card
reset)
– Write 12decimal in SCGT 0
Now the Guard Time and Block Guard Time are properly initialized . The TERMINAL will
insure a minimun 12 ETUs between 2 lea ding edges of 2 consecutive characters trans-
mitted. The TERMINAL will al so insure a minimum of 22 ETUs between the leading
edge of a character sent by the IC C, and the leading edge of a character sent by the
TE RMINA L. There is no need to write SCGT1,0 again and again.
Wai ting Time ( W T) Count er The WT counter is a 32 bits down count er which can be loaded with the value contained
in the SCWT3, SCWT2, SCWT1, SCWT0 registers. Its main purpose is timeout signal
generat ion. It is 32 bits wide and is decremented at the ETU rate. see Fig ure 34.
CHAR 1 CHAR 2 CHAR n CHAR n+1 CHAR n+2 CHAR n+3
>= Block Guard Time >= SCGT
RECEPTION from ICC TRAN SMISSION to ICC
Write “Block Guard Time” in SCGT1,0
Write SCGT 1,0 with
and set BGTEN to transfer the value to the
shadow SCGT1,0 registers
a value for Guard Time
ETU C ounter Block G uar d Time Coun ter
Enable
SCGT1 SCGT0
9 bits
Guard Time Count er
GT[8:0]
Shadow SCGT1 ,Shado w SCGT 0
9 bits
Comparator
transm
it
Comparator 9 bits
9 bits
Enable
transmit
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When the WT counter times out, an interrupt is generated and the SCIB function is
locked: reception and emission are disabled. It can be enabled by resetting the macro or
reloading the counter.
The Waiting Time Counter can be used in T=0 prot oc ol for the Work Waiting Time. It can
be us ed in T=1 protocol for the Ch arac ter Waiting T ime and f or t he Block Wai ting Time.
See the detailed explan ation below.
Figu re 34. Waiting Time Counter
In th e so c al led ma nuel mo de, t he co unt er is loa ded, if W TE N = 0, duri ng the w ri te of
SCWT2 register. The counter is loaded with a 32 bit word built with SCWT3 SCWT2
SCWT1 SCWT0 registers (SCWT0 contain WT[7-0] byte. WTEN is located in the
SCICR regi ster.
W hen WT EN=1 and in UART m ode, the counter is re-loaded at the occurenc e of a start
bit. This mode will be detailed below in T=0 protoc ol and T=1 protocol.
In manual mod e, the WTEN signal controls the start of the count er (rising edge) and the
stop of the counter (falling edge). After a timeout of the counter, a falling edge on
W TEN, a reload of SC WT 2 and a risin g edge of WTEN are necess ary to start aga in the
counter and to release the SCIB macro. The reload of SCWT2 transfers all SCWT0,
SCWT 1, SCWT 2 and SCW T3 registers to the WT counter.
In UART mo de t here is an aut oma tic load on the start bit det ection. This a utomatic lo ad
is v ery usef ul for cha nging o n-the -fly the timeou t valu e since t here i s a regist er to hol d
the load value. This is the case for T=1 protocol.
In T=0 protocol the maximun interval between the start leading edge of any character
sent by the ICC and the st art of the previous char acter sent by eit her the ICC or the Ter-
minal is the maximum Work Waiting Time. The Work Waiting Time shall not exceed
960 *D*WI ETUs with D and WI parameters are r eturned by the field TA1 and TC2
res pectively in the A nsw er To Reset (A TR). This is the val ue the u ser shall write in th e
SCWT0,1,2,3 register. This value will be reloaded in t he Waiting Time counter ev ery
start bit.
ETU Counter WT Counter Timeout
SCWT2 SCWT1 SCWT0
WT[31:0]
Load
WTEN
Start Bit
UART
Write_SCWT2
SCWT3
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Fi gure 35. T=0 mode
In T=1 protocol : The maximum interval between the leading edge of the start bit of 2
consecuti ve characters sent by the ICC is called maximum Character Waiting Time. The
Charact er Waiting Tim e shall not exceed (2**CWI + 11) ETUs with 0 =< BWI =< 5. Con-
sequ ently 12 ETUs =< CWT =< 43 ETUs.
T=1 pr otocol also specify the maximum Block Waiting Time. This is the time between
the leadi ng edge of the last character sent by the Terminal gi ving the right to send to the
ICC, and t he leading edge of the start bit of the first character sent by the I CC. T he
Block Waiting Time shall not exc eed (2**B WI*960 + 11) ETUs with 0 =< B WI =< 4. Con-
sequent ly 971 ETUs =< BWT =< 15371 ETUs.
In T=1 protoc ol it is possible to extend the Block Waiting Time with the Waiting Tim e
Exten sion (WTX). When selected th e waiting time b ecomes BW T*WTX ETUs. The
W aiting Time counter is 32 bit wide to accom odat e this feature.
It is possible to take advantage of the automatic reload of the Waiting Tim e counter with
a st art bit in UART mode (T=1 protocol use UART mode) . If the Termi nal sends a block
of N cha racters, and the I CC i s sup posed t o respond immediately afte r, then the follow-
ing sequence c an be used.
While sending the (N-1)th character of the block, the Terminal can write the
SCWT 0,1,2 ,3 with BWImax.
At the start bit of the Nt h character, the BWImax is loaded in the Waiting Time count er
During t he transmission of the Nth character, the Term inal c a n write SCWT0,1,2,3 with
the CWIma x.
At the start bit of the first character se nt by the IC C, the CWIm ax will be loa ded in the
W aiting Time counter.
Fi gure 36. T=1 Mode
CHAR 1 CHAR 2
< WT
> GT
BLOC 1
CHAR 1 CHAR 2 CHAR n
BLOC 2
CHAR n+1 CHAR n+2 CHAR n+3
< BWT < CWT
TRANSMISSION RECEPTION
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Power-on and Power-off FSM T he P ow er- on Po wer-o ff F inite Sta te Ma ch ine (FSM ) app lie s th e sig nals on t he sm art
card in accordance wit h ISO7816-3 standard. It conducts the Activation (Cold Reset and
Warm Reset as well as De-Activation) it also manages the exception conditions s uch as
overcurrent (see DC/DC Converter)
To be able to power on t he SCIB, the card presence is mandatory . Upon detectection of
a card presence, the Terminal initiate a Cold Reset Activ ation.
The Cold Reset Activation Terminal procedure is as follow and the Figure 37. Timing
indications are given according t o ISO IEC 7816
– RESET= Low , I/O in the receive state
– Power Vcc (see DC/DC Converter)
– Once V cc is esta blished, apply Clock at time Ta
– Maintain Reset Low unti l time Ta+tb (tb< 400 clocks)
– Monitor The I/O line for the Answer To Reset (ATR) between 400 and 40000
clock cycles after Tb. ( 400 clocks < tc < 4000 0clocks)
Fi gure 37. SCIB Activation Cold Reset Se quence after a Card Insertion
The Warm Reset Activation Terminal procedure is as follow and the Figure 38
– Vcc active, Reset = High, CLK active
– Term inal dr iv e Re se t low a t time T to init ia t e th e w ar m Rese t. Reset=0
maintained for at least 400 clo cks until time Td = T+te (400 clocks < te)
– Terminal keep the IO line in receive sta te
– Terminal drive Re set high after at least 400 clocks at time Td
– ICC shall respond with an ATR wit h in 40000 clocks (t f<40000 clocks)
Fi gure 38. SCIB Activation Warm Reset Sequen ce
CVCC
CRST
CCLK
CIO DataUndefined
Ta Ta+tb Tb+tc
CVCC
CRST
CCLK
CIO Data
T Td=T + te Td + tf
Undefined
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Removal o f the smart card will automatically start the power off sequenc e as de scribed
in Figure 39.
The SCIB deactivation sequence after a reset of the CPU or after a lost of power supply
is ISO7 816-3 co mpliant. The s witching ord er of the signal s is the sam e as in Figure 3 9
but the delay between signals is analog and not cloc k dependant.
Fi gure 39. SCIB Deactivation Sequenc e after a Card Extraction
In t erru pt Gen erat or There are several sources of interruption but the SCIB m acro-cell issues onl y one inter-
rupt signal: SCIBIT.
Fi gure 40. SCIB Interrupt Sources
This signal is high level active. Each of the sources is able to activate the SCIB interrup-
tion which is cleared when the Smart Card Interrupt register is read by the
microcontroller.
If during the read of the Sma rt Card In terrup t register another interrupt occurs, t he acti-
v ation of th e c orres po nding b it in the S mar t Ca rd Interru p t regi ste r and the ne w SC IB
interruption is delayed until the interrupt register is read by the microcontroller.
Warning : Each bit of t he S CIIR regi ster is irrele vant while the corresp onding interrup-
tion is disabled in SCIER register. When the interruption mode is not used, the bits of
the SCISR registe r must be used instead of the bits of the SCIIR register.
CVCC
CRST
CCLK
CIO
8 Clock Cycles
ESCTBI
ICARDER
ESCWTI
ESCRI
ESCPI
EVCARDER
Tra nsm it bu ffe r
copied to shift register
Output current
out of range
Output voltage
out of range
Timeout on WT
counter
Complete
transmission
Complete
reception
Parity error
detected
SCIB IT
ESCTI
SCTBI
ICARDERR
VCARDERR
SCWTI
SCTI
SCRI
SCPI
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Additional Features
Clock The CK_ISO input mus t be in the range 1 - 5 M Hz accordin g to ISO 7816.
The CK _IS O can be programm ed up t o 1 2 M Hz. In t his cas e, the timing s pecification of
the output buffer will not c om ply to ISO 7816.
Fi gure 41. Clock Diagram of the SCIB Blo ck
Fi gure 42. Prescaler 2 De scription
Th e divi sion f act or SC ICLK m ust be sm all er than 4 9. If it is g rea ter or eq ua l to 49, the
PR2 prescaler is locked.
See Figure 17 clock tree diagram in the clock controller chapter.
Table 42. Examples of Clock settings
Card Presence Input The internal pull-up (weak pull-up) on Card Presence input can be disconnected in order
to reduce the consum pt ion (CPRESRE S, bit 3 in PMOD0).
In this case, an external resistor (ty pical ly 1 M
Ω
) must be ex ternal ly tied t o Vcc.
CPRES input can generate an interrupt (see Interrupt syste m section).
The detecti on level can be selected.
PR2
Ck_cpu
Ck_ISO
SCIB
CK _PLL or
CK_IDLE
CK_XTAL1
PR2
1/(2*(48 - SCICLK[5-0])) CK_ISO
EXT48
PLLCON.2
0
1
CK_PLL
CK_XTAL1
XTSCS
SCICLK.7
SCICLK[5:0]
<48
=48
XTAL1 (MHz) EXT4 8 SCICLK CK_ ISO
80 36 4
80 44 12
80 42 8
80 40 6
80 24 2
80 0 1
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Transmit / Receive Buf fer The contents of the SCIBUF Transmit / Receive Buffer is tr ansferred or received into /
from t he Shift Register . The Shift Register is not accessible by microcontroller. Its role is
to prepare the byte to be copied on the I/O pin for a tran smission or in the SCIBUF
buffer after a reception.
During a charac ter tran smission proc ess, as soon as the contents of the SCIB UF b uffer
is transferred to the shift register, the SCTBE bit is set in SCISR register to indicate that
the SCIB UF buffer i s em pty a nd ready to acce pt a new byte. This m echani s m a voids t o
wait for the compl ete t ransmission of the prev ious byte before writing a new byte in the
buffer and enables to speed up the transmission.
– If the Character repetition mode is not selected (b it CREP=0 in SCICR), as
soon as the contents of the Shif t Register is t ransferred to I/O pin, the SCTC
bit is set in SCISR register to indicate that the byte has been transm itted.
– If the Character repet i tion mode is selected (bi t CREP=1 in SCICR) The
TERMINAL will be able to repeat characters as requested by the ICC (See
the Parity Error in T=0 protocol descripti on in the definition paragraph
above). The SCTC bit in SCISR register will be set after a su ccessful
transmission (no retry or no further retry requested by the ICC). If the
number of retr ies is exhausted (up to 4 retries depending on CREPSEL bi t in
SCSR) and the last retry is still unsuccessful, the SCTC bit in SCISR will not
be set and the SCPE bit in SCISR register will be set instead.
During a charac ter reception proce ss, the conten ts of the Shift Registe r is transferred in
the SCIBUF buffer.
– If the Character repetition mode is not selected (b it CREP=0 in SCICR), as
soon as the contents of t he Shift Register is transfe rred to the SCIBUF the
SCRC bit is set in SCISR register to indicate that the byte has been
received, and the SCIBUF contains a valid character ready to be red by the
microcontroller.
– If the Character repet i tion mode is selected (bi t CREP=1 in SCICR) The
TERMINAL will be able to request repeti t ion if the received c haracter exhibit
a parity error. Up to 4 retries can be requested dependi ng on CREPSEL bit
in SCSR. The SCRC bit will be set in SCISR register aft er a successful
reception, first reception or after retry(ies). If the number of retries i s
exhausted (up to 4 retries depending on CREPSEL bit in SCSR) and the last
retry is still unsuccessful, the SCRC bit and the SCPE bit in SCISR regis ter
will be set. It wi ll be poss ible t o read the erroneous character.
Warning : the SCTBI, SCTI S CRI and SCPI bits have the same function as SCTBE,
SCTC, SCRC and SCPE bits. The first ones are able to generate interruptions if the
interruptions are enabled in SCIER register while the second ones are only status bits to
be used in pulling mode. If the interruption mode is not used, the status bits must be
used. The SCTBI, SCTI and SCRI bits do not contain valid information while their
respective interrupt enable bits ESCTBI, EXCTI, ESCRI are cleared.
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Fi gure 43. C har acterTransmis sion Di agra m
SCIBUF
Transmitted
Character
Shift Register I/ O pin
SCTBE SCTC
SCISR regi ster
SCTBI SCTI
SCIIR register
ESCTBI
ESCTI
SCIER Register
Parity error
SCPE
SCPI
Parity error
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Fi gure 44. Character Reception Diagram
SCIB Reset The SCICR regi ster contains a reset bit. If set, this bit generates a reset of the SCIB and
its r egisters. Table 43 defines the SCIB registers that are reset and their reset values.
Table 43. Reset Values for SCI Registers
SCIBUF Received
Characte
r
Shift Register
I/O pin
SCTBE SCTC
SCISR register
SCRC
SCTBI SCTI
SCIIR register
SCRI
ESCTBI
ESCTI
SCIER Register
ESCRI
SCPE
Register Name SCIB Reset Value (Binary)
SCICR 0000 0000
SCCON 0X00 0000
SCISR 1000 0000
SCIIR 0X00 0000
SCIER 0X00 0000
SCSR X000 1000
SCIBUF 0000 0000
SCETU1, SCETU0 XXXX X001, 0111 0100 (372)
SCGT1, SCGT0 0000 0000, 0000 1100 (12)
SCWT3, SCWT2, SCWT1, SCWT0 0000 0000, 0000 0000, 0010 0101, 1000 0000 (9600)
SCICLK 0X10 1111
Parity error
SCPI
Parity error
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Alternate Card A second card named ‘Alternate Card’ can be controlled.
The Clock signal CCLK1 can be adapted to the XTAL frequency. Thanks to the clock
prescaler which can divide the frequency by 1, 2, 4 or 8. The bits ALTKPS0 and
ALTKPS1 in SCSR Register are used to set this factor.
Fi gure 45. Alternate Card
Registers
There are fifteen registers to control the SCIB macro-cell. They are de scribed from
Table 58 to Table 45.
Some of the register widths are grea ter than a byte. Despite the 8 bits access provided
by the BIU, the address mapping of this kind of register respects the following rule :
The Low significant byte register is implemented at the higher address.
This implem entation makes access to these registers easier when using hi gh level pro-
gramm ing languages (C,C+ +).
SIM, SAM
CARD
Alternate
card
CVCC
CRST
CIO
CCLK
CK_IDLE 1
0CCLK1
SCSR Reg.
PR3
SCCLK1
1, 1/2, 1/4 or 1/8
P1.7
Main
card
CPRES
SMART
CARD
SCSR Reg.
ALTKPS0,1
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Reset Value = 0000 0000b
Tab le 44. Sm art Card Interfa ce Control Register - SCICR (S:B6h, SCRS = 1)
76543210
RESET CARDDET VCARD1 VCARD0 UART WTEN CREP CONV
Bit Number Bit Mnemonic Description
7 RESET
Reset
Set this bit to reset and deactivate the Smart Card Interface.
Clear this bit to activate the Smart Card Interface.
This bit acts as an active high software reset.
6 CARDDET Card Presence Detector Sense
Clear this bit to indicate the card presence detector is open when no card is inserted (CPRES is high).
Set this bit to indicate the card presence detector is closed when no card is inserted (CPRES is low).
5-4 VCARD[1:0]
Card Voltage Sel ection:
VCARD[1] VCARD[0] CVCC
00 0 V
01 1.8 V
10 3.0 V
1 1 5.0 V
3UART
Card UART Selection
Clear this bit to use the CARDIO bit (P1.0) bit to drive the Card I/O (P1.0) pin.
Set this bit to use the Smart Card UART to drive the Card I/O pin (P1.0 pin).
Controls al so the Waiting Time Counter as described i n Section “Waiting Time (WT) Counter”, page 69
2WTEN
Wa iting Time Counter Enable
Clear this bit to stop the counter and enable the load of the Waiting Time co unter hold re gisters.
The hold registers a re loa ded with SCWT0 , SCWT1, SCWT2 and SCWT3 values when SC WT2 is written.
Set this bit to start the Waiting T i me Counter. The counters stop when it reaches the timeout value.
If the UART bit is set, the W aiting T i me Counter automatically reloads with the hold registers whenever a start bit is
sent or received.
1 CREP
Character Repetition
Clear this bit to disable parity error detection and indication on the Car d I/O pin in receive mode and to disable
c haract er repetition in transmit mode.
Set this bit to enable parity error indication on the Card I/O pin in receive mode and to set automatic character
repetition when a parity error is indicated in transmit mode.
Depending upon CREPSET bit is SCSR register, the receiver can indicate parity error up to 4times (3 repetitions) or
up to 5times (4 repetitions) after which it will raise the parity error bit SCPE bit in the SCISR register. If parity interrupt
is enabled, the SCPI bit in SCIIR register will be set too.
Alternately, the transmitter will detect ICC character repetition request. After 3 or 4 unsuccessful repetitions
(depending on CREPSEL bit in SCSR register), the transmitter will raise the parity error bit SCPE bit in the SCISR
register. If parity interrupt is enabled, the SCP I bit in SC IIR re gister will be set too.
Note : Charact er repetition mode is sp ecified for T=0 protoc ol only and should not be used in T=1 protocol (block
orient ed protocol)
0CONV
ISO Convention
Clear this bit to use the direct convention: b0 bit (LSB) is sent first, the parity bit is added after b7 bit and a low level
on the Card I/O pin represents a’0’.
Set this bit to use the inverse convention: b7 bit (LSB) is sent first, the parity bit is added after b0 bit and a low level on
the Card I/O pin rep resents a’1’.
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Reset Value = 0X00 0000b
Tab le 45. Sm art Card Contacts R egister - SCCON (S:ACh, SCRS=0)
76543210
CLK - CARDC8 CARDC4 CARDIO CARDCLK CARDRST CARDVCC
Bit Number Bit Mnemonic Description
7CLK
Card Clock Selection
Clear this bit to us e the Card CLK bit (CARDCLK bit below) to drive Card CLK (P1.4) pin.
Set this bit to use CK_XTAL1 or CK_PLL signals for CK_ISO to drive the Card CLK pin (CCLK = P1.4 pin)
Note: internal synchronization avo ids glitches on the CLK pin when switching this bit.
6-
Reserved
This bit can be changed by software but the read value is indeterminate.
5 CARDC8
Card C8
Clear this bit to drive a low level on the Card C8 pin (CC8 = P1.1 pin).
Set this bit to s et a high level on the Car d C8 pin (CC8 = P1.1 pin)..
The CC8 pin can be used as a pseudo bi-directional I/O when this bit is s et.
Warning : VCAR DOK=1 (SCI SR.4 bit) condition must be true to change th e stat e of CC8 pin
4 CARDC4
Card C4
Clear this bit to drive a low level on the Card C4 pin (CC4 = P1.3 pin).
Set this bit to s et a high level on the Car d C4 pin (CC4 = P1.3 pin).
The CC4 pin can be used as a pseudo bi-directional I/O when this bit is s et.
Warning : VCAR DOK=1 (SCI SR.4 bit) condition must be true to change th e stat e of CC4 pin
3 CARDIO
Card I/O
If UART bit is cleared in SCICR register , this bit enables the use of the Card IO pin (CIO = P1.0) as a C51
pseudo bi-directional port :
To read from CIO (P1.0) port pin : set CARDIO (P1.0) bit then read CARDIO (P1.0) bit to have the CIO port
value
To wr i te in CIO (P1. 0) po rt pi n : set C ARDI O (P1 .0 ) bit to writ e a 1 in CI O (P 1. 0) po rt pin , clear CARD I O (P1. 0)
bit to write a 0 in CIO (P1.0) port pin.
Warning : VCAR DOK=1 (SCI SR.4 bit) co ndition must be true to change the stat e of CIO pin
2 CARDCLK Card CLK
When the CLK bit is cleared in SCCON Register, the value of this bit is driven to the Card CLK pin.
Warning : VCAR DOK=1 (SCI SR.4 bit) co ndition must be true to change the stat e of Card CLK pin
1 CARDRST
Card RST
Clear this bit to drive a low level on the Card RST pin.
Set this bit to s et a high level on the Car d RST pin.
Warning : VCAR DOK=1 (SCI SR.4 bit) co ndition must be true to change the stat e of Card RS T pin
0 CARDVCC
Card VCC Control
Clear this bit to desactivate the Card interface and set its power-off. The other bits of SCCON register have no
effec t whil e thi s bi t is clea red .
Set this bit to power-on the Card interface. The activa tion sequence should be handled by sof tware.
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Reset Value = 1000 0000b
Tab le 46. Sm art Card UART Interface Status Register -
SCISR (S:ADh, SCRS=0)
76 5 4 3210
SCTBE CARDIN ICARDOVF VCARDOK SCWTO SCTC SCRC SCPE
Bit Number Bit Mnemoni c Description
7SCTBE
UART Transmit Buffer Empty Statu s
This bit is set by hardware when the Transmit Buffer is copied to the transmit shift register of the Smart Card
UART.
It is cleared by hardware when SCIBUF register is written.
6 CARDIN Card Presence Status
This bit is set by hardware if there is a card presence (debouncing filter has to be done by software).
This bit is cleared by hardware if there is no card presence.
5 ICARDOVF
Card Current Overflow Status
This bit is set when the current on card is above the limit specified by bit OVFADJ in DCCKPS register (Table 61
on page 94)
It is cleared by hardware.
4 VCARDOK Card Voltage Correct Status
This bit is set when the output voltage is within the voltage range specified by VCARD[1:0] in SCICR register .
It i s cleared otherwise.
3SCWTO
Waiting Time Counter Timeout Status
This bit is set by hardware when the Waiting Time Counter has expired.
It is cleared by the reload of the counter or by the reset of the SCIB.
2SCTC
UART Transmitted Character Status
Thi s bi t is s et by har dw are when th e Sma r t Ca rd U AR T ha s t ran smi t ted a cha ract e r . I f cha r acte r repe ti tio n mo de is
selected, this bit will be set only after a successful transmission. If the last allowed repetition in not successful, this
bit w ill not be set.
It is clea red by so ftwar e when this register is read.
1SCRC
UART Received Character Status
This bit is set by hardware when the Smart Card UART has received a character
It is cleared by hardware when SCIBUF register is read. If character repetition mode is selected, this bit will be set
only after a successful reception. If the last allowed repetition is still unsuccessful, this bit will be set to let the user
re ad the er rone ou s valu e if ne cessa r y.
0SCPE
Character Reception Parity Error Status
Th is bit is set w hen a pari ty er ro r is de tec ted on the rec eive d ch ar acter.
It is cleared by software when this register is read. If character repetition mode is selected, this bit will be set only
if the ICC report an error on the last allowed repetition of a TERMINAL transmission, or if a reception parity error
is found on the last allowed IC C character repetition.
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Reset Value = 0X00 0000b Note: 1) In case of mult iple i nterrupts occuring at the same time (sampled by the sam e edge of
the internal clock), the interrupts wil l be servic ed in the fol lowing order from the highest to
the lowest priority :
- UART Transmit Buffer Empty
- Card Current Overflow
- Card Voltage Error
- Waiting Time Counter Timeout
- UART Tran sm i t te d C ha r ac te r
- UART Received Character
- Character Reception Parity Error
2) It is recommended that the application saves the SCIIR register after reading it in
order t o avoid the loss of pending inter rupti ons as the SCII R regi ster is cleared when it is
r e ad by th e MCU .
Tab le 47. Sm art Card UART Interrupt Identification Register (Read Only)
SCIIR (S:A Eh, SCRS=0)
765 4 3 2 1 0
SCTBI - ICARDERR VCARDERR SCWTI SCTI SCRI SCPI
Bit Number Bit Mnemonic Description
7SCTBI
UART Tra nsmit Buffer Empty Interrupt
This bit is set by hardware when the Transmit Buffer is copied into the transmit shift register of the Smart
Card UART. It generates an inter rupt if ESCTBI bit is se t in SC IER register other wise this bit is irrelevant .
It is cleared by hardware when this register is read.
6-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
5 ICARDERR
Card Current Overflow Interrupt
This bit is set when the current on card is above the limit specified by bit OVFADJ in DCCKPS register (Table
61 on page 94). It generates an interrupt if ICARDER bit is set in SCIER register otherwise this bit is
irrelevant.
It is cleared by hardware when this register is read.
4 VCARDERR
Card Voltage Error Interrupt
This bit i s set when the outp ut volt age goes out of the voltage range specified by VCARD field. It g enera tes
an interrupt if EVCARDER bit is set in SCIER register otherwise this bit is irrelevant.
It is cleared by hardware when this register is read.
3SCWTI
Wa iting Time Counter Timeout Interrupt
This bit is set by hardware when the Waiting T ime Counter has expired. It generates an interrupt if ESCWTI
bit is set in SCIER register otherwise this bit is irrelevant.
It is cleared by hardware when this register is read.
2SCTI
UART Transmitted Character Interrupt
This bit is set by hardware when the Smart Card UART has completed the character transmission. It
generates an interrupt if ESCTI bit is set in SCIER register otherwise this bit is irrelevant.
It is cleared by hardware when this register is read.
1 SCRI
UART Received Character Interrupt
This bit is set by hardwar e when the Smart C ard UART has comple ted the character reception. It generates
an interrupt if ESCRI bit is set in SCIER register otherwise this bit is irrelevant.
It is cleared by hardware when this register is read.
0SCPI
Character Reception Parity Error Interrupt
This bit is set at the same time as SCTI or SCRI if a parity error is detected on the received character. It
generates an interrupt if ESCPI bit is set in SCIER register otherwise this bit is irrelevant.
It is cleared by hardware when this register is read.
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Reset Value = 0X00 0000b
Tab le 48. Sm art Card UART Interrupt Enabling Register - SCIER (S:AEh, SCRS=1)
765 4 3210
ESCTBI - ICARDER EVCARDER ESCWTI ESCTI ESCRI ESCPI
Bit Number Bit Mnemonic Description
7 ESCTBI UART Transmit Buffer Empty Interrupt Enabled
Clear this bit to disable the Smart Card UART Transmit Buffer Empty interrupt.
Set this bit to enable the Smart Card UART Transmit Buffer Empty interrupt.
6-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
5 ICARDER Card Current Overflow Interrupt Enabled
Clear this bit to disable the Card Current Overflow interrupt.
Set this bit to enable the Card Current Overflow interrupt.
4 EVCARDER Card Voltage Error Interrupt Enabled
Clear this bit to disable the Card Voltage Error interrupt.
Set this bit to enable the Card Voltage Error interrupt.
3ESCWTI
Wa itingTime Counter T im eout Interrupt Enabled
Clear this bit to disable the Waiting Time Counter timeout interrupt.
Set this bit to enable the W aiting Time Counter timeout interrupt.
2 ESCTI UART Transmitted Character Interrupt Enabled
Clear this bit to disable the Smart Card UART Transmitted Character interrupt.
Set this bit to enable the Smart C ard UART Transmi tted Character in terrupt.
1 ESCRI UART Rec eived Character Interrupt Enabled
Clear this bit to disable the Smart Card UART Received Character interrupt.
Set this bit to enable the Smart Card UART Received Character interrupt.
0ESCPI
Character Recepti on Pa rity Error Interrupt Enabled
Clear this bit to disable the Smart Card Character Reception Parity Error interrupt.
Set this bit to enable the Smart Card Character Reception Parity Error interrupt.
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Reset Value = X000 1000b
Reset Value = 0000 0000b
Tab le 49. Sm art Card Selection Register - SCSR (S:AB h)
76543210
- BGTEN - CREPSEL ALTKPS1 ALTKPS0 SCCLK1 SCRS
Bit Number B it Mn em on i c Des cr iption
7-
Reserved
The value read from this bit is inde termi nate. Do not change th is bit.
6BGTEN
Block G uard Time Enable
Set this bit to s elect the minimum interval bet ween the leading edge of the start bits of the las t char acter
received from the ICC and the first charac ter sent by the Terminal. The transfer of GT[8-0] value to the BGT
counter is done on the rising edge of the BGTEN.
Clear this bit to suppress the minimum time between reception and transmission.
5-
Reserved
The value read from this bit is inde termi nate. Do not change th is bit.
4 CREPSEL
Character repetition selection
Clear this bit to select 5 times transmission (1 original + 4 repetitions) before parity error indication (conform to
EMV)
Set this bit to select 4 times transmission (1 original + 3 repetitions) before parity error indication
3-2 ALTKPS1:0
Alternate Card Clock prescaler factor
00 ALTKP S = 0: prescaler facto r equal s 1
01 ALTKPS = 1: prescaler factor equals 2
10 ALTKPS = 2: prescaler factor equals 4 (reset value)
11 ALTKPS = 3: prescaler factor equals 8
1 SCCLK1 Alte rnate ca r d clock se lec ti o n
Set to select the prescaled PR3 clock for CCLK1 (P1.7) pin
Clear to select P1.7 port bi t
0 SCRS Smart Car d R eg i st er Selecti o n
The SC RS bit selects which set of the SCIB r egisters is accessed.
Tab le 50. Smart Card T r a n smi t / Re ceive Buffer - SCIBUF (S:AA)
76543210
--------
Bit Number Bit Mnemonic Description
--
Smar t Card Transmit / Receive Bu ffer
- A new byte can b e written in the buffer to be transmitted on the I/O pin when SCTBE bit is set.
The bits are sorted and copied on the I/O pin versus the active convention.
- A new byte received from I/O pin is ready to be read when SCRI bit is set.
The bits are sorted versus the active conv ention .
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Reset Val u e = 0XXX X001b
Reset Value = 0111 0100b
Tab le 51. Sm art Card ETU Register 1 - SCETU1 (S:ADh, SCRS=1)
76543210
COMP----ETU10ETU9ETU8
Bit Number Bit Mnemonic Description
7COMP
Compensation
Clear this bit when no time compensation is needed (i.e. when the ETU to Card CLK period ratio is close to an
integer with an error less than 1/4 of Card CLK period).
Set this bit otherwise and reduce the ETU period by 1 Card CLK cycle for even bits.
6-3 - Reserved
The value read from these bits is i ndeterm inate. Do not change thes e bits.
2-0 ETU[10:8]
ETU MSB
Used together with the ETU LSB in SCETU0 (Table 52)
Warning : the ETU counter is reloaded at each register’s write operation.
Do not change this register during character reception or transmission or while Guard Time or Waiting Time
Counters are runnin g.
Tab le 52. Sm art Card ETU Register 0 - SCETU0 (S:ACh, SCRS=1)
76543210
ETU7 ETU6 ETU5 ETU4 ETU3 ETU2 ETU1 ETU0
Bit Number Bit Mnemonic Description
7 - 0 ETU[7:0]
ETU LSB
The Elementary Time Unit is (ETU[10:0] - 0.5*COMP)/f, where f is the Card CLK frequency.
According to ISO 7816, ETU[10:0] can be set between 11 and 2048 (2047 ?)
The default reset value of ETU[10:0] is 372 (F=372, D=1).
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Reset Value = 0000 1100b
Rese t Val u e = XXXX XXX0 b
Reset Value = 0000 0000b
Tab le 53. Sm art Card Transmit Guard Time Register 0 - S CGT0 (S:B4h, SCRS=1)
76543210
GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0
Bit Number Bit Mnemonic Description
7 - 0 GT[7:0]
Transmit Gu ard Time LSB
The minimum time between two consecutive start bits in transmit mode is G T[8:0] * ETU. This is equal to ISO IEC
Guard Time +10 (see Guard Time Counter description.
According to ISO IEC 7816,the time between 2 consecutive leading edge start bits ca n be set betw een 11 and
266 ( 11 t o 25 4+ 12 ET Us) .
Tab le 54. Sm art Card Transmit Guard Time Register 1 - S CGT1 (S:B5h, SCRS=1)
76543210
-------GT8
Bit Number Bit Mnemonic Description
7 - 1 - Reserved
The value read from these bits is i ndeterm inate. Do not change thes e bits.
0GT8
Transmit Guard T ime MSB
Used together with the Transmit Guard T ime LSB in SCGT0 register (Table 53).
Tab le 55. Sm art Card Character/Block Waiting Time Register 3
SC WT3 (S: C1h, SCRS=0)
76543210
WT31 WT30 WT29 WT28 WT27 WT26 WT25 WT24
Bit Number Bit Mnemonic Description
7 - 0 WT[ 31:24] Waiting Time B y te3
Used together with WT[ 23:0] in registers SCW T2,SCW T1, SCWT0 (see Table 56).
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Reset Value = 0000 0000b
Reset Value = 0010 0101b
Reset Value = 1000 0000b
Tab le 56. Sm art Card Character/Block Waiting Time Register 2
SCWT2 (S:B6h, SCRS =0)
76543210
WT23 WT22 WT21 WT20 WT19 WT18 WT17 WT16
Bit Number Bit Mnemonic Description
7 - 0 WT[ 23:16] Waiting Time B y te2
Used together with WT[ 31:24] and WT[15:0] in register s SCWT3,SCWT1, SCWT0 (see Ta ble 58) .
Tab le 57. Sm art Card Character/Block Waiting Time Register 1
SCWT1 (S:B5h, SCRS =0)
76543210
WT15 WT14 WT13 WT12 WT11 WT10 WT9 WT8
Bit Number Bit Mnemonic Description
7 - 0 WT[15:8] Waiting Time Byte 1
Used together with WT[31:16] and WT[ 7:0] in registers SCWT 3,SCWT2, SCWT0 (see Ta ble 55).
Tab le 58. Sm art Card Character/Block Waiting Time Register 0
SCWT0 (S: B4h, SCRS=0)
76543210
WT7 WT6 WT5 WT4 WT3 WT2 WT1 WT0
Bit Number Bit Mnemonic Description
7 - 0 WT[7:0]
Waiting Time Byte 0
WT[31:0] is th e reload value of the Waiting Time Counter (WT C) .
The WTC is a general-purpose timer. It is using the ETU clock and is controlled by the WTEN bit (see Table 44 on
page 79 and Section “Waiting Time (WT) Counter”, page 69).
When UART bit of Registers is set, the WTC is auto matica lly reloaded at each start bit of the UART. It is used to
check the maximum time between to consecutive start bits.
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Reset Value = 0X10 1111b (default value for a divider by two)
DC/DC Converter The Smart Card voltage (CVCC) is supplied by the integrated DC/DC converter which is
controlled by several registers:
• The SCICR register (Table 44 on page 79 ) cont rols the CVCC level by means of bit s
VCARD[1:0].
• The SCCON register (Table 45 on page 80 ) enabl es to switch the DC/DC converter
on or off by means of bit CARDVCC.
• The DCCKPS register (Table 61 on page 94) controls the DC/DC clock and current.
The DC/DC co nverter ca nnot be s witched o n while t he CPRE S pin rem ains inac tive. If
CPRES pin becomes inactive while the DC/DC converter is operating an aut omatic shut
down seq uence of the DC/DC converter is initiated by the electronics.
It is mandatory to switch off the DC/DC Converter before entering in P ower-down mode.
Configuration The DC/DC Conv erter can work in two different modes which are selected by bit MODE
in DC CKPS r e gister:
• Pump Mode: an external inductance of 10 µ H mus t be connected betwe en pins LI
and VCC. VCC can be higher or lower than CVCC.
• Regulator mode : no external inductance is requir ed but VCC must be always higher
than CVCC+0.3V. The Regulation mod e will work even if an external ind uctance of
10 µH is connected between pins LI and VCC
The DC/DC clock prescaler which is controlled by bits DCCKPS[3:0], in DCCKPS regis-
te r must be confi gured to set t he DC/DC clo ck to a w orking frequenc y of 4 MHz w hich
depends upon the value of the crystal. There is no need to change the default configura-
tion set by the reset sequence if an 8 MHz crystal is used by the application.
The DC/DC Convert er i mplements a current overflow controller which avoids permanent
damag e of the DC/DC conv erter in case of short circuit between CVCC and CVSS. The
maxim um limi t i s around 100 mA. It i s possible to increase this limit in normal op erating
Tab le 59. Sm art Card Clock Reload Register - SCICLK (S:C1h, SCR S=1)
7 6 543210
XTSCS - SCICLK5 SCICLK4 SCICLK3 SCICLK2 SCICLK1 SCICLK0
Bit Number Bit Mnemonic Description
7XTSCS
Smart Card Clock Selection Bit
If XTSCS bit is set OR EXT48 bit is set (in PLLCON register) , CK_PLL is used to generate CK_ISO.
Otherwise, CK_XTAL1 is used to generate CK_ISO.
See the Clock Tree diagram figure 17.
6-
Reserved
The value read from t his bit is indeterminate. Do not change these bits.
5 - 0 S CICLK[5: 0]
SCIB clock reload register
Prescaler 2 reload v alue is used to defines the c ard clo ck frequency.
If SCICLK[5:0] is smaller than 48 :
Fck_iso = F ck_pll or Fck_XTAL1/ (2 * (48 - SCICLK[5:0]))
If SCICLK[5:0] is equal to 48 :
Fck_iso = Fck_XTAL1
SCICLK[5:0] must be smaller than 49.
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mode by 20% by means of bit O VFADJ in DCCKPS register. When the current overflow
controller is operating, the ICARDOV F is set by the hardware in SCISR register.
The cu rrent dra wn fr om po wer s uppl y by th e DC/ DC c onverte r is c ontro lled du ring t he
startup phas e in order to avoid hig h transient curren t mainly in P um p Mo de which coul d
ca use the power s upply vo ltage to drop dram atical ly. Th is cont rol is don e by mea ns of
bits BOOS T[1:0] , which increases progres sively the startup current level.
Initi alizati on P rocedu r e The initialization procedure is different depending upon the required Card Vcc. One pro-
cedu re apply for Card Vcc =< 3 volts and one procedure for Card Vcc = 5 volts.
The initialization proce dure involves :
• Select the CVCC level by means of bits V CARD[ 1:0] in SCICR register,
• Set bits BOOST[1:0] in DCCKPS regi st er following the current level control wanted.
• Switch th e DC/DC on by means of bit CARDVCC in SCCON register,
• Monitor bit V CARDOK in SCIS R register in order to know when the DC/ DC
Converter is ready (CVCC voltage has reached the expected level)
Procedu re for CVcc =< 3 volts The DC/DC regulation mode m ust be selected for Card Vcc = 1.8 vo lts and Card Vcc =
3 vo lts (MO DE = 1 in DCC KPS regi ster) The detailed procedur es is d escribed i n flow
ch art of Figure 46. for Card Vcc = 1.8 v olts and i n the flo w chart o f Figure 47 . fo r C ard
Vcc = 3 volts
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Fi gure 46. Card Vcc = 1.8V Initialization Procedure
Mode Regulation
DCCKPS[7]=1
VCARDOK=1
Set Timeout to 3 ms
Timeout
Expired
DC/DC Initialization
Failure
DC/DC Initialization
successful
BOOST[1:0]=01
SCICR.7=Reset=0
SCICR.7=Reset=1
SCCON CardVcc=1
VCARD[1:0] = 01
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Fi gure 47. Card Vcc = 3V Initialization Procedure
Mode Regulation
DCCKPS[7]=1
VCARDOK=1
Set Timeout to 3 ms
Timeout
Expired
DC/DC Initialization
Failure
DC/DC Initialization
successful
BOOST[1:0]=01
SCICR.7=Reset=0
SCICR.7=Reset=1
SCCON CardVcc=1
VCARD[1:0] = 10
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Procedu re for CVcc = 5volts The DC/DC pump mode must be selected (MODE = 0 in DCCKPS register). The
detailed procedure is des cribed in flow chart of Figure 48.
Fi gure 48. Card Vcc = 5V Initialization Procedure
W hile VCC rem ains highe r than 4.0V and startup current lower than 30 mA (dependi ng
on the load type), the DC/DC converter should be ready without having to increm ent
BOOST[1:0] bits beyond [0:0] level. If VCC > 4.0V and startup current > 30 mA, it will be
nece ssary to increment the BOOST [1:0] bits until the DC/DC con verter is ready.
Incrementation of BOOST[1: 0] bits increases at the s ame time the current overflow level
in the same proportion as the s tartup curr ent. So once the DC/DC converter is ready it is
SCCON CardVcc=1
VCARDOK=1
Set Tim eo ut to 3 ms
Timeout
Expired
Increment
BOOST [1 :0]
BOOST[1:0]
= max = 3?
DC/DC Initialization
Failure
DC/DC Initialization
Successful
Decrement
BOOST[1:0]
to adjust the
current overflow
Mode Pump
DCCKPS[7]=0
BOOST[1:0]=[0:0]
SCICR.7=Reset=0
SCICR.7=Reset=1
VCARD[1: 0] = 11
BOOST[1:0]
= [0:0]
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adv ised to dec reme nt the BOO ST[1:0] bits to restore the overflo w current t o its norma l
or desired value.
Moni t ori ng Proce dure Onc e the DC/DC has b een suc cess fuly in itialized, it is necess ary t o moni tor the DC/ DC
converter by means of bits VCARDOK and ICARDO V F in the SCISR register.
Tab le 60. DC/DC converter status
VCARDOK ICARDOVF DC/DC Sta t us
00
- No t Started or switched off by application.
The current overflow sensor is dis abled du ring the DC/DC co nverter startup. Then if a current
ov erflow condition is applied durin g the DC /DC co nverter startup, the DC/DC co nvert er is u nable
to start and both bits VCARDOK and ICARDOVF remains at 0.
DC/DC converter correctly started then the output voltage is out of ISO/IEC 7816-3
specifications. In this case the firmware must take appropriate actions like deactivating the
DC/DC converter in co mpliance with ISO/IEC 7816.
0 1 Started and automatically switched of f by a current overflow condition
1 0 Operating properly accord ing to ISO/IEC 781 6-3 and EMV recommendations
11 Not applicable
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DC/DC Converter register
Reset Value = 0000 0000b
Tab le 61. DC/DC Converter Control Register - DCCKPS (S:BFh)
76543210
MODE OVFADJ BOOST1 BOOST0 DCCKPS3 DCCKPS2 DCCKPS1 DCCKPS0
Bit Number Bit Mnemonic Des cription
7MODE
Regulation mode
0 : Pump mode (External Inductance r equired)
1 : Regulator mode ( No External inductance required if VC C > CVCC +0.3V)
6 OVFADJ Cur re nt Ove rfl ow Adju stm en t on Sm art Card term in al
0 : norma l: 100 mA avera ge
1 : normal + 20%
5 - 4 BOO ST [ 1: 0]
VCARDOK=0 VCARDOK=1
Maximum Startup Current drawn from power supply
00 : Normal: 30 mA average
01 : Normal + 30%
10 : Normal + 50%
11 : Normal + 80%
Current Ov e rfl ow Level on Smar t Card termina l
00 : Normal = OVFADJ
01 : Normal + 30%
10 : Normal + 50%
11 : Normal + 80%
3 - 0 DCCKP S[3:0]
DC/DC Clock Prescaler Va lue
0000 : Division factor: 2 (reset value)
0001 : Division factor: 3
0010 : Division factor: 4
0011 : Division factor: 5
0100 : Division factor: 6
0101 : Division factor: 8
0110 : Division factor: 10
0111 : Division factor: 12
1000 : Division factor: 24
Ot her val ues are reserv ed
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USB Controller The AT8xC5122D implements a USB device controller supporting Full Speed data
transfer. I n addition to the default control endpoint 0, it provides 6 other endpoints, which
can be configured in Control, Bulk, Interrupt or Isochronous modes:
• Endpoint 0: 32-byte FIFO, defau lt control endpoint
• Endpoint 1,2,3: 8-byte FIFO
• Endpoint 4,5: 64-byte F IFO
• Endpoint 6: 2 x 64-byte Ping-pong FIFO
This allows the firmware to be developed conforming to most USB device classes, for
example:
• USB Mass Storage Class Control/Bulk/Interrupt (CBI) Trans port, Revision 1.0 -
December 14, 1998.
• USB Mass Storag e Class Bulk-Only Transport , Revision 1.0 - September 31, 1999.
• USB Human Interface Device Class, Version 1.1 - April 7, 1999.
• USB Device Firmware Upgrade Class, Revision 1.0 - M ay 13, 1999.
USB Mass Storage Classes
USB Mass Storage Class CBI
Transport Wit hin the CBI framework, the Control endpoin t is used to transport command blocks as
well as to t rans port s tandard US B reque sts. One Bulk -Out endpo int is us ed to transport
data from the host to the device. One Bulk-In endpoint is used to transport data from the
device to the host. And one interrupt endpoint may also be used to signal command
comple tion (protocol 0); it i s optiona l and may not be used (protocol 1).
The following configurati on adheres to these requirement s:
• Endpoint 0: 8 bytes, Control In-Out
• Endpoint 4: 64 bytes, Bulk-Out
• Endpoint 5: 64 bytes, Bulk-In
• Endpoint 1: 8 bytes , Interrupt In
USB Mass Storage Class Bulk-
Only Tran sp ort Within the Bulk-Only framework, the Control endpoint is only us ed to transport class-
sp ecific and s tandard US B req uests for dev ice set -up and con figura tion. On e Bulk-Out
endpoint is used t o transport commands and data from the host to the device. One Bulk-
In endpoi nt is used to transport status and data from the devic e to the host. No in terrupt
endpoint is needed.
The following configurati on adheres to these requirement s:
• Endpoint 0: 8 bytes, Control In-Out
• Endpoint 4: 64 bytes, Bulk-Out
• Endpoint 5: 64 bytes, Bulk-In
USB Devi ce Firmware
Upgrade (DFU) The US B Device Firmwa re Upda te (DFU ) protocol can be us ed to upgrad e the on-chi p
program memory of the AT8xC5122D. This allows the implementation of product
enhanc em ent s and patches to devices that are already in the field. Two diffe rent config-
urations and description sets are used to support DFU functions. The Run-Time
con figurat ion co-exists with the usual fun ctio ns of the device, which ma y be USB Mass
Storage for the AT8xC5122D. It is used to initiate DF U from the normal operating mode.
The DFU configuration is used to perform the firmware update after device re-configura-
tion and USB reset. It excludes any other function. Only the default control pipe
(endpoint 0) is used to support DFU services in both c on figurations .
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The only p ossi ble va lue for t he wMa xPac ketSi ze in th e DFU co nfi gurat ion is 32 bytes ,
which is the siz e of the FIFO implemented for endpoint 0.
Description The USB device controller provides the hardware that the AT8xC5122D and the
AT 83C5123 need to inte rface a USB link to a data f low stored in a double port memory
(DPRAM).
Th e USB contr oller requi res a 48 MHz r eference clock, which is th e output of th e
AT8xC5122D/23 PLL (see Section "Phase Lock Loop (PLL)", page 42) divided by a
clock prescaler. This clock is used to generate a 12 MHz full speed bit clock from the
rece ived US B differential data and to tran smit data according t o fu ll speed USB device
toleranc e. Clock recovery is done by a Digital Phase Loc ked Loop (DP LL) block, which
is compliant with the jitte r specification of the USB bus.
The Interface Engine (SIE) block performs NRZI encoding and decoding, bit s tuffing,
CRC generation and checking, and the serial-parallel data conversion. The Universal
Function In terface (UFI) performs the interface between the dat a flow and the Dual Port
Ram
Fi gure 49. USB Dev ice Controller Block Diagram
Serial Interface Eng ine (SIE) The SIE perf orms the f ollowing functions:
• NRZI dat a encoding and decoding.
• Bit stuffing and unstuffing.
• CRC generation and checking.
• Handshakes.
• TOKEN type identifying.
• Address checking.
• Clock generation (via DPLL).
SIE
DPLL
USB
D+/D-
Buffer UFI
12MHz
48 MHz +/- 0.25%
D+
Up to 48 MHz
UC_SYSCLK
C51
Microcontrolle
r
Interface
D-
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Fi gure 50. SIE Block Diagram
Function Interface Unit (UFI) The Function Interface Unit provides the interface between the AT8xC5122D (or
AT83C5123) and the SIE. It m anages transactions at the packet l evel with minimal inter-
vention from the device firmware, which reads and wri tes the endpoint FI FOs.
Fi gure 51. UFI Block Diagram
En d of Pac ket
Detection
Sta rt of Packet
Detection
D+
D-
Clock
Recovery
SYNC detection
PID decoder
Address Decoder
Serial to Parallel
Conversion
CRC5 & CRC16
Generation/Check
US B Pattern Generator
Parallel to Serial Converter
Bit St uffin g
NRZI Converter
CRC16 Generator
NRZI ‘ NRZ
Bit Unstuffing
Packet bit counter
Clk48
(48 MHz)
SysClk
(12 MHz)
DataIn [7:0]
DataOut
8
8
Transfer
Control
FSM
DPR Control
USB side
CSREG 0 to 7
Registers
Bank
DPR Control
mP side
UFI
User DPRAM
Up to 48 MHz
UC_SYSCLK
C51
Microcontrolle
r
Interface
Asynchronous Information
Transfer
Endpoint 0
Endpoint 1
Endpoint 2
Endpoint 3
SIE
DPLL
Endpoint 4
Endpoint 5
Endpoint 6
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Fi gure 52. Minimum Intervention from the USB Device Firmw are
OU T Transac tions:
HOST
UFI
C51
OUT DATA0 (n Bytes )
ACK Endpoint FIFO read (n bytes)
OUT DATA1
NACK
OUT DATA1
ACK
IN Transacti ons:
HOST
UFI
C51
IN ACK
En dp oi nt F IF O w rit e
IN
DATA1
NACK
interrupt C51
IN
DATA1 interru pt C51
Endpoint FIFO write
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Configuration
General Co n f igur a tion • USB controller enable
Before any USB transaction, the 48 MHz required by the USB controller must be cor-
rectly generated (Section "Clock Cont roller", page 41).
The USB controller should be then enabled by setting the USBE bit in the USBCON
register.
• Set address
After a Reset or a USB reset, the s oftware has to s et th e FEN (Function Enable) bit in
the USBADDR register. This action will allow the USB controller to answer to the
reques ts sent at the address 0.
When a SET_ADDRESS re quest has be en received, the USB controller must only
answ er to the address defined by th e request. The new address should be st ored in the
USBADD R register. The FEN bit and the FADDEN b it in the USBCON register should
be set to allow the USB controller to answer only to requests sent at th e new address.
• Set configuration
The CON FG bit in the USBC ON register should b e set after a SET_CONFIGUR ATION
reques t with a non -zero value. Otherwise, this bit should be cle ared.
Endpoint Con figuration • Selection of an Endpoint
The endpoint register access is performed using the UEPNUM register. The following
registers
correspon d to the endpoi nt whose number is stored in the UEPNUM registe r. To select
an Endpoint, the firmware has to write the endpoint number in the UEPNUM register.
– UEPSTAX,
– UEPCONX,
–UEPDATX,
–UBYCTX,
Fi gure 53. Endpoint Selection
UEPNUM
Endpoint 0
Endpoint 6
UEPSTA0 UEPCON0 UEPDAT0
UEPSTA6 UEPCON6 UEPDAT6
0
1
2
3
4
5
6
SFR Registers
UEPSTAX UEPCONX UEPDATX
X
UBYCT0
UBYCT6
UBYCTX
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• Endpoint enable
Before using an endpoint, this one should be enabled by setting the EPEN bit in the
UEPCONX register.
An endpoint which is not enabled won’t answer to any USB request. The Default Contr ol
Endpoint (Endpoint 0) should always be enabled in order to answer to USB standard
requests.
• Endpoint type configuration
All Standard Endpoints can be configured in Contro l, Bulk, Interrupt or Isochronous
mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous
mode. The configuration of an endpoint is performed by setting the field EPTYPE with
the following values:
– Cont rol: EPTYPE = 00b
– Isochronous: EPTY PE = 01b
– Bulk: EPTYPE = 10b
– Interrupt: EPTYPE = 11b
The Endpoint 0 is the Default Control Endpoint and should always be configured in Con-
trol type.
• Endpoint direction configuration
For B ulk, Int errup t and Isochro nous endpo ints, th e direct ion i s define d wit h the E PDIR
bit of the UEPCONX register with the followin g values:
– IN:E PDIR = 1b
– OUT:EPDIR = 0b
For Control endpoints, the EPDIR bit has no ef fect.
• Summary of Endpoint Configuration:
Make sure to select the correct endpoint number in the UEPNUM register before
access ing to endpoin t specific registers.
Table 62. Summary of Endpoint Conf iguration
Endpoint con figu r ation EPEN E PDIR EPTY PE UEPC ONX
Disabled 0b Xb XXb 0XXX XXXb
Control 1b Xb 00b 80h
Bulk-In 1b 1b 10b 86h
Bulk-Out 1b 0b 10b 82h
Interrupt-In 1b 1b 11b 87h
Interrupt-Out 1b 0b 11b 83h
Isochronous-In 1b 1b 01b 85h
Isochronous-Out 1b 0b 01b 81h
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• Endpoint FIFO reset
Before us ing an endpoint, its FIFO should be reset. This action resets the FIFO p ointer
to its original value, resets the byte counter of the endpoint (UBYCTX register), and
resets the data toggle bit (DTGL bit in UEPCONX).
The reset of an endpoint FIFO is performed by s etting to 1 and resetting to 0 the corre-
sponding bit in the UEPRS T register.
For example, i n order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000
0000b in the UEPRS T register.
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Read/Write Data FIFO
Read Data FIFO T he read acce ss for each OUT endpoint is performed using the UEPDA TX register.
After a ne w valid pa cket has been received on an Endp oint, the dat a are st ored into the
FIFO and t he byte count er of t he endpoint is updated (UBY CTX register). The firmware
has to store the endpoint byte counter before any access to the endpoint FIFO. The byte
coun ter is n ot updated when reading the FIFO.
To read data from an endpoint, select the correct endpoint number in UEPNUM and
read the UEPDATX register. This action automatically decreases the corresponding
addres s vector, and the next data is the n available in the UEPDATX register.
Write Data FIFO T he write access for each IN endpoint is performed using the UEPDATX register.
To write a byte into an IN endpoint FIFO, select the correct endpoint number in UEP-
NUM and write into the UEPDATX register. The corresponding address vector is
automat ically increased, and anot her write can be carrie d out.
W arning 1: The byte counter is not u pdat ed.
W arning 2: Do not write more bytes than supported by the corresponding endpoin t.
Fi gure 54. Endpoint FIFO Configuration
Endpoi nt 0 - bank 0
Endpoint 1 - bank 0
Endpoint 2 - bank 0
Endpoint 3 - bank 0
Endpoint 4 - bank 0
Endpoi nt 5 - bank 0
Endpoi nt 6 - bank 0
Endpoi nt 6 - bank 1
8 Bytes
32 Bytes
8 Bytes
8 Bytes
64 Bytes
2 x 64 Byte
s
Base Addresses
00H
20H
28H
30H
38H
78H
B8H
F8H
138H
64 Bytes
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Bulk / Interrupt
Transactions Bulk and Interrupt transact ions are mana ged in the same way.
Bulk/Interrupt OUT
Transactions in S tandard
Mode
Fi gure 55. Bulk/Interrupt OUT transactions in Standard Mode
An en dpoint s houl d be f irst enabled an d c onfigured be fore be ing abl e to re ceive B ulk or
Interrupt packets.
When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabl ed. T he firm ware has to s el ect the cor-
responding endpoint, store the number of data bytes by reading the UBYCTX register. If
the received pac ket is a ZLP (Zero Length P acke t), the UBYCT X register value is equa l
to 0 and no data has to be read.
When all the endpoint FIFO bytes have been read, the firmware should clear the
RXOUTB0 bit to allow the USB controller to accept the next OUT packet on this end-
point. Until the RXOUT B0 bit has bee n cleared by the firmware, t he USB controll er will
answ er a NAK handshake for each OUT requests .
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct and the endpoint byte coun ter contains the number of bytes sent by the Host.
OUT DATA0 (n bytes)
ACK
HOST UFI C51
Endpoint FIFO read byte 1
OUT DATA1
NAK
RXOUTB0
Endpoint FIFO read byte 2
Endpoint FIFO read byte n
Clear RXOUTB0
OUT DATA1
NAK
OUT DATA1
ACK RXOUTB0 Endpoint FIFO read byte 1
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Bulk/Interrupt OUT
Transactions in Ping-Pong
Mode (End point s 6)
Fi gure 56. Bulk / Interrupt OUT Transac tions in Ping-Pong Mode
An en dpoint s houl d be f irst enabled an d c onfigured be fore be ing abl e to re ceive B ulk or
Interrupt packets.
When a valid OUT packet is received on t he endpoint bank 0, the RXOUTB0 bit is set by
the U SB controlle r. Thi s triggers an interrup t if enabl ed. The firm ware has to s elect the
correspo nding endpo int, store the number of d ata bytes by readi ng the UBYCTX re gis-
ter. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is
equal to 0 and no data has to be read.
When all the endpoint FIFO bytes have been read, the firmware should clear the
RXO UB0 bit t o al low the USB controller to ac cept t he next O UT packet on t he end point
bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has
been cleared by the firmware, t he USB controller will answer a NAK handshake for each
OUT requests on the bank 0 endpoint FIFO.
W hen a new valid OUT packet is received on the endpoint bank 1, the RXOUT B1 bit is
set by the USB controller. This triggers an interrupt if enabled. The firmware empties the
bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has
been cleared by the firmware, t he USB controller will answer a NAK handshake for each
OUT requests on the bank 1 endpoint FIFO.
The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each
new valid packet recei pt.
The firmware has to clear one of these two bits after having read all the data FIFO to
allow a new valid packet to be stored in the corresponding bank.
A NAK han dshake is sent by the USB controller only if the ba nks 0 and 1 has not been
released by the firmware.
OUT DATA0 (n bytes)
ACK
HOST UFI C51
Endpoint FIFO bank 0 - r ead byte 1
RXOUTB0
Endpoint FIFO bank 0 - r ead byte 2
Endpoint FIFO bank 0 - r ead byte n
Clear RXOUTB0
OUT DATA1 (m bytes)
ACK
RXOUTB1 Endpoint FIFO bank 1 - r ead byte 1
Endpoint FIFO bank 1 - r ead byte 2
Endpoint FIFO bank 1 - r ead byte m
Clear RXOUTB1
OUT DATA0 (p bytes)
ACK
RXOUTB0 Endpoint FIFO bank 0 - r ead byte 1
Endpoint FIFO bank 0 - r ead byte 2
Endpoint FIFO bank 0 - r ead byte p
Clear RXOUTB0
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If the Host sends more bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
Bulk/I nterrupt IN T ransactions
In Standard Mode Figure 57. Bulk/Interrupt IN Transactions in Standa rd Mode
An endpoint should be first enabled and configured before being able to send Bulk or
Interrupt packets.
The firm ware should fill the FIFO wi th t he data to be se nt an d set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data s tored in FIFO at the
nex t IN req uest con cerning this en dpoin t. To sen d a Zero Length P ack et, the firm ware
shou ld set the TXRDY bit w ithout writing any data into th e endpoin t FIFO.
Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK
hands hake for each IN requests.
To canc el the sending of this packet, the firmware has to reset the TXRDY bit. T he
packet stored in the endpoint FIFO is then cleared and a new packet can b e written and
sent.
W hen the I N pack et has b een sent and ack nowle dged by the Hos t, the T XCMP L bit in
the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with
new data.
The firmware should never write more bytes th an supporte d by the endpoint FIFO.
All USB retry mechanisms are automat ically managed by the USB controller.
IN DATA0 (n bytes)
ACK
HOST UFI C51
Endpoint FIFO write byte 1
IN
NAK
TXCMPL
Endpoint FIFO write byte 2
Endpoint FIFO write byte n
Set TXRDY
Clear TXCMPL
Endpoint FIFO write byte 1
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Bulk/I nterrupt IN T ransactions
i n P i ng-P ong Mode Fi gure 58. Bulk / Interrupt IN transaction s in Ping-Pong mode
An en dpoint wil l be first enabled an d c onfigured before being able to sen d Bulk or Inter-
rupt packets.
The f irmw are will fill the FIFO ban k 0 with the data to be sent and set the TXRDY bit i n
the UEPSTAX registe r to allow the US B con tr o ller to se nd the data st o re d i n FI FO at th e
nex t IN reque st concer ni ng the en dpoin t. T he FIF O ba nks a re auto mati call y swi tche d,
and the firmware can imme diately write into the endpoint FIFO bank 1.
When the IN packet concerning the bank 0 has been sent and ack nowledged by the
Host, the TXC MPL bit is set by the U SB controller. This triggers a U SB interrupt if
en abled. The firmwar e will c lear t he TX CMPL bit before filling the endpo int F IFO bank 0
with new data. The FIFO banks are then autom atically switched .
When the IN packet concerning the bank 1 has been sent and ack nowledged by the
Host, the TXC MPL bit is set by the U SB controller. This triggers a U SB interrupt if
en abled. The firmwar e will c lear t he TX CMPL bit before filling the endpo int F IFO bank 1
with new data.
The b ank swi tch is perform ed by the USB controll er each tim e the TXR DY bit is set by
the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,
th e USB co ntrol ler will a nswer a NAK hands hake fo r each IN req uests co nce rning th is
bank.
Note that in the example above, the firmware clears the Transmit Complete bit (TXC-
MPL) bef ore set t ing the Transm it Ready bit (TX RDY). This is done in order t o avoi d t he
firmware to clear at the s am e time the TXCM PL bit for bank 0 and the bank 1.
The firmware will never write m ore by tes than support ed by the endpoint FIFO.
IN DATA0 (n Bytes)
ACK
HOST UFI C51
Endpoint FIFO Bank 0 - Write Byte 1
IN
NACK
TXCMPL
Endpoint FIFO Bank 0 - Write Byte 2
Endpoint FIFO Bank 0 - Write Byte n
Set TXRDY
Endpoint FIFO Bank 1 - Write Byte 1
Endpoint FIFO Bank 1 - Write Byte 2
Endpoint FIFO Bank 1 - Write Byte m
Set TXRDY
IN DATA1 (m Byte s)
ACK
Endpoint FIFO Bank 0 - Write Byte 1
Endpoint FIFO Bank 0 - Write Byte 2
Endpoint FIFO Bank 0 - Write Byte p
Set TXRDY
Clear TXCMPL
IN
DATA0 (p Bytes)
ACK
TXCMPL Clear T X CMPL
Endpoint FIFO Bank 1 - Write Byte 1
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Control Transactions
Set up Stage The DIR bit in the UEP STA X register should be a t 0.
Receiving Setup packets is the same as receiving Bulk Out packets, except that the
Rxsetup bit in the UEPSTAX register is set by the USB controller instead of the
RXO UTB0 bit to indicate t hat an Out pack et with a Setup PID has been recei ve d on the
Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEP-
ST AX register are cleared and an interrupt is triggered if enabled.
The firmware has to read the Setup request stored in the Control endpoint FIFO before
clearing the RXSETUP bit to free the endpoint FIFO for the next transaction.
Data Stage: Control Endpoint
Direction The dat a stage managem ent is similar to Bulk managem ent .
A Co ntrol endpoi nt is mana ged b y the U SB cont roller as a full -duplex en dpoint: I N and
OUT. All other endpoint types ar e managed as half-duplex endpoint: IN or OUT. The
firmware has to specify the control endpoint direction for the data stage using the DIR bi t
in the UEPSTAX register.
• If the data stage consists of INs,
th e fi rmwar e h as to set the DIR bit in th e UEPSTAX reg ister before writing into th e
FIFO and sending the data by se tting to 1 th e TXRDY bit in the UEPSTA X register.
The IN transaction is complete when the TXCMPL has been set by the hardware.
The fi rm ware should clear the TXCMPL bit before any other t ransaction.
• If the data stage consists of OUTs,
the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware
when a new valid p acket has been received on the endpoint. The firmware must
read the data stored into the FIFO and then clear the RXOUTB0 bit to reset the
FIFO and to all ow the nex t transaction.
The bit DIR is used to send the correct dat a toggle i n the data stage.
To send a STALL handshake, see “STALL Handshake” on page 110.
Statu s Stag e The DIR bit in the UEP STA X register should be reset at 0 for IN and OUT status stage.
The status stage managem ent is similar to Bulk managem ent .
• For a Co ntrol Write transaction or a No-Data Cont rol transaction, the status stage
consists of a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions In
Standard Mode” on page 105 ). To s end a STALL handshak e, see “STALL
Handshake” on page 110 .
• For a Co ntrol Read transaction, the status stage cons ists of a OU T Zero Length
Packet (see “B ulk/Interrupt OUT Transac tions in Standa rd Mode” on page 103).
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Isochronous
Transactions
Isochronous OUT
Transactions in S tandard
Mode
An endpoint should be fir st enabled and configured before being able to receive Isochro-
nous packets.
W hen a n OUT pack et is rec eived on an e ndpoi nt, t he RXO UTB 0 bit is se t by t he USB
controller. This triggers an interrupt if enabled. The firmware has to select the corre-
sp ondin g endpo int, st ore the nu mber of data by tes b y readin g the U BYCTX re gi ster. If
the received pac ket is a ZLP (Zero Length P acke t), the UBYCT X register value is equa l
to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register i s set by the USB controller if the packet
stored in FIFO has a corrupted CRC. T his bit is updated after each new packet receipt.
When all the endpoint FIFO bytes have been read, the firmware should clear the
RXOUTB0 bit to allow the USB controller to store the next OUT pac ket data into the
endpoint FI FO. Until th e RXOUTB0 bit has been cleared by t he firmware, the data sent
by the Host at eac h OUT trans ac ti o n w ill be los t .
If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will
store only the remaining bytes into the FIFO.
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
Isochronous OUT
Transactions in Ping-pong
Mode
An endpoint should be fir st enabled and configured before being able to receive Isochro-
nous packets.
W hen a OUT pac ket is received on the end point bank 0, the RXOUTB 0 bit is s et by the
USB controller. This triggers an interrupt if enabl ed. T he firm ware has to s el ect the cor-
responding endpoint, store the number of data bytes by reading the UBYCTX register. If
the received pac ket is a ZLP (Zero Length P acke t), the UBYCT X register value is equa l
to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register i s set by the USB controller if the packet
stored in FIFO has a corrupted CRC. T his bit is updated after each new packet receipt.
When all the endpoint FIFO bytes have been read, the firmware should clear the
RXO UB0 bit to allow the USB controller to store the next OUT pac ket data into the end-
point FIFO b ank 0. This ac t ion switches the endpoint bank 0 and 1. Unt il the RXOUTB0
bit has been cleared by t he firmware, the data sent by the Host on the bank 0 end point
F IF O w ill be lo s t .
If the RXOUTB 0 bit is c leared while the Host is sending data on the endpoint bank 0, the
USB controller will store only the remaining bytes into the FIFO.
When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by
the USB controller. This trigg ers an interrupt if enabled. The firmware emp ties the
bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has
bee n c leare d by the f irmw are , the dat a sen t by the Host on t he ba nk 1 end poin t FI FO
wi ll b e lo s t.
The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each
new packet receip t.
The firmware has to clear one of these two bits after having read all the data FIFO to
allow a new packet to be stored in the co rresponding bank.
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If the Host sends more bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
Isochronous IN Transactions
in Standard Mode An endp oint shoul d be firs t enable d and c onfigured before being a ble to s end Iso chro-
nous packets.
The firm ware should fill the FIFO wi th t he data to be se nt an d set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data s tored in FIFO at the
next IN request concerni ng this endpoint.
If th e T XR DY bit is not set when t he IN req ues t oc curs, n othing wi ll be sent by the US B
controller.
W hen the IN packet ha s be en sent, the TXCMP L bit in the UEPSTAX regist er is set by
the USB controller. This triggers a USB interrupt if enabled. The firmware should clear
the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should
neve r write more bytes than supported by the endpoint FIFO.
Isochronous IN Transactions
i n P i ng-P ong Mode An e ndpoi nt should be first enable d and conf igured before bei ng a ble to send Isoch ro-
nous packets.
The firmware shou ld fill the FIFO bank 0 with the data to be sent and s et the TXRDY bit
in the UEPSTA X register to allow the USB controller to send the data stored in FIFO at
the next IN request concerning the endpoint. The FIFO banks are automatically
switched, and the firmware can immediately write into the endpoint FIFO bank 1.
If th e T XR DY bit is not set when t he IN req ues t oc curs, n othing wi ll be sent by the US B
controller.
W hen the IN packet concerning the bank 0 has been s ent, the TXCMPL bit is set by the
U SB control ler. Thi s triggers a U SB interr upt if en abled . The firm ware s hould c lea r th e
TX CMPL bi t before filling the endpoint FIFO bank 0 with new data. The FIFO banks are
then autom atica lly switched .
W hen the IN packet concerning the bank 1 has been s ent, the TXCMPL bit is set by the
U SB control ler. Thi s triggers a U SB interr upt if en abled . The firm ware s hould c lea r th e
TX C MPL bit before f illing the endpoint FIFO bank 1 with new data.
The b ank swi tch is perform ed by the USB controll er each tim e the TXR DY bit is set by
the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,
the USB controller won’t send anything at each IN requests concerning this bank.
The firmware should never write more bytes th an supporte d by the endpoint FIFO.
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Miscellaneous
USB Reset The EORINT bit in the USBINT register is set by hardware when a End of Reset has
been det ected on the USB bus . This triggers a USB interrupt if enab led. The USB con-
troller is still enabled, but all the USB registers are reset by hardware. The firmware
shou ld clear the EORINT bit to allow the next USB reset detection.
STALL Handshake T his function is only available for Control, Bulk, and Interru pt endpoints.
The firmware has to set the STALLRQ bit in the UEPSTA X register to send a STALL
hands hake at the nex t req uest of the Hos t on the endpoin t sel ected with th e UEPNUM
register. The RXSETUP, T XRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be fir st
r eset to 0. The b it STL CR C is s et at 1 by t he U SB c ontro ller whe n a ST AL L has b ee n
sent. This triggers an interrupt if e nabled .
The firmware should clear the ST ALLRQ and S TLCRC bits after each STALL sent.
The STALLRQ bit is cleared automatically by hardware when a va lid SETUP PID is
received on a CONTROL ty pe endpoint.
Start of Frame Detection The SOFINT bit i n the USBINT register is set when the USB controller detects a Start Of
Frame PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT
bit to allow the next Start of Frame detection.
Frame Number W hen re ceiving a Start of Frame, the frame n umb er is autom atically stored in the
UFNUML and UFNUMH registers. The CRCOK and CRCERR bit s indic ate if the CRC of
the last Start Of Frame is valid (CRCOK set at 1) or corrupt (CRCERR set at 1). The
UFNUML and UFNUMH registers are automatically updat ed when receiving a new Start
of Frame.
Data Toggle Bi t The Data Toggle bit is set by hardware when a DATA 0 packet is received and accepted
by the USB con troller and cleared by hardware whe n a D ATA 1 p acket is received and
accep ted by the USB controller. This bit is reset w hen the firmware resets the endpoint
FIFO using the UEPRS T register.
For Con trol endpoints, each S ETUP trans action s tarts with a DATA 0 and data toggli ng
is then used as for Bulk endpoints until the end of the Data stage (for a control write
transfer). The St atus stage completes the data transfer with a DATA 1 (for a control read
transfer).
For Isochronous endpoints, the device firmwa re should ignore the data-toggle.
NAK Handshakes When a NAK h andshake is sent by the USB c ontroller to a IN or OUT request from the
Host, the NAKIN or NAKOUT bit is set by hardware. This information can be used to
determine the direction of the comm unication during a Control transfer.
These bit s are cleared by soft ware.
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Suspend/Resume Management
Suspend T he S uspend stat e can be d etect ed by t he US B co ntroller if all the cloc ks are e nable d
and if the USB controller is enabled. The bit SPINT is set by hardware when an idle
state is detected for more t han 3 ms. This tr iggers a USB interrupt if enabled.
In order to reduce current consumption, the firmware can put t he USB PAD in idle mode,
stop the clocks a nd p ut the C51 in Idle or Power-down m ode. The Resume detection is
st ill ac tive.
The USB PAD is put in idle mode when the firm ware clear the SPINT bit. In order to
avoid a new suspend detection 3ms later, the firmware has to disable the USB clock
input using the SUSPCLK bit in the USBCON Register. The USB PAD autom atically
exits of idle mode when a wake-up event is detected.
The stop of the 48 MHz clock from the PLL should be done in the following order:
1. Disable of the 48 MHz clock input of the USB controller by s etting to 1 the SUS-
PCLK bit in the USBCON register.
2. Disable the PLL by clearing the PLLEN bit in the PLLCON register.
Resume When the US B cont roller is in Sus pend s tate, t he Res ume detec tion i s act ive even if all
the clocks are disabled and if the C51 is in Idle or Power-down mo de. The WUPC PU bit
is set by hardw are when a non-idle state occurs on the USB bus. Th is t riggers an inter-
rupt if en abled. This interrupt wakes up the CPU f rom its Idle or Power-dow n state an d
the interrupt function is t hen executed. The firmware will first enable the 48 MHz gener-
ation and then reset to 0 the SUSPCLK bit in the USBCO N register if needed.
The firmware has to clear the SPINT bit in the USBINT register before any other USB
operation in order to wake up the USB controller from its Suspend mo de.
The USB cont roller is then re-activated.
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Fi gure 59. Example of a Suspend/ Resum e Mana gem ent
Up stream Resume A USB device can be allowed by the Host to send an upstream resu me for Remote
W ake-up purpose.
When the USB controller receives the SET_FEATURE request:
DEVICE_REMOTE_WAKEUP, the firmware should set to 1 the RM WUPE bit in the
USBCO N register to enable this function. RMWUPE value should be 0 in the other
cases.
If the device i s in SUSPEND mode, the USB controller can send an upstream resume by
clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRM-
WUP bit in the USBCON register. The USB controller sets to 1 the UPRS M bit in the
USBCON register. All cloc ks must be enabled first . The Remote Wake is sent only if the
USB bus was in Suspend state for at least 5 ms. When the upstream resume is com-
pleted, the UPRSM bit is reset to 0 by hardware. The firmware should then clear the
SDRMWUP bit.
USB Controller Init
D
etection of a SUSPEND State SPINT
Set SUSPCLK
Disable PLL
microcontroller in power-down
Detection of a RESUME State WUPCPU
Enable PLL
C lear SUSPCLK
Clea r WUPCPU bit
Clear SPINT
Note :
WUPCPU bit must be
Cleared before enabling
the PLL
Put the USB pads
in power down mod
e
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Fi gure 60. Example of REMOTE WA K EU P Managem ent
USB Controller Init
Detection of a SUSPEN D stat e SPINT
Set RMWUPE
Suspend man agem ent
Enable Clocks
upstream RESUM E sent UPRSM
Clear SPI NT
Se t SDMWU P
Clear SD RMWUP
SET_FEATURE: DEVICE_REMOTE_WAKEUP
Need USB Resum
e
UPRSM = 1
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Detach Simulation In order to be r e-enum erate d by t he Host, the AT8xC5122/23 has the possibilit y t o s im -
ulate a DETACH-ATTA CH of the USB bus.
The VREF output voltage is bet ween 3.0V and 3.6V. This output can be connec ted to the
D + pull-up as sho wn in F igure 6 1. This ou tput c an be p ut in hig h-im pedanc e whe n the
D ETACH bit is set to 1 in the USBCON register. M aintain ing this outpu t in high im ped-
ance for more than 3 µ s will simulate the disconnection of the device. When resetting
the DETACH bi t, an ATTACH i s then simulated. The US B controller should be enabl ed
to use this feature.
Fi gure 61. Example of VREF Connection
Fi gure 62. Disconnect Timing
D-
D+ D-
D+
GND
VCC
VREF
R1
USB-B Connector
1
2
3
4
R2
R3
D+
D-
VSS
VIL
VIHZ(min)
Device
Disconnected Disconnect
Detected
>= 2,5 μs
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USB Interrupt System
Interrupt Sy stem Priorities
Figu re 63. USB Interrupt Control S ys tem
Interrupt Con trol System As shown in Figure 64, many events can produce a USB interrupt:
• TXCMPL: T ransmitted I n Data (Table 70 on page 121). This bit is set by hardwar e
when the Host accept a In packet.
• RXOUTB0: R eceived Out Data Bank 0 (Table 70 on page 121). This bit is set by
hardware when an Out packet is accepted by the end point and stored in bank 0.
• RXOUTB1: Received Out Data Bank 1 (only for Ping-Pong endpoints) (Table 70 on
page 121). This bit is set by hardware when an Out packet is accepted by the
endpoint and stored in bank 1.
• RXSETU P: Rec eived Setup ( Tab le 70 on page 121). This bit is se t by hardware
when an SETUP packet is accepted by the endpoint.
• NAKIN and NAKO UT: These bits are set by hardware when a Nak Handshake has
been received on the corresponding endpoint. These bits are cleared by s oftware.
• STLCRC: STALLE D (onl y for Control , Bulk and Interrupt endpoint s) (Table on page
122). This bit is set by har dware when a STALL handshake has been sent as
requested by STALLRQ, and is reset by hardware when a SETUP packet is
received.
• SOFINT: S tart Of Frame Interrupt (Table 65 on page 118). This bit is set by
hardware when a USB start of frame packet has been received.
• WUPCPU: Wake-Up CPU In terrupt (Table 65 on page 118). This bit is set by
hardware when a USB resume is detected on the USB bus, after a SUSPEND state .
• SPINT: Suspend Interrupt (Table 65 on page 118). This bit is set by hardware when
a USB suspend is detected on the USB bus.
EUSB
IEN1.6 EA
IEN0.7
USB
Controller
IPH/L
Interrupt Enable Lowest Priority Interrupts
Priority Enable
00
01
10
11
D+
D-
Table 63. Priority Levels
IPHUSB IPLUSB USB Priority Level
00 0 Lowest
01 1
10 2
1 1 3 Highest
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Figu re 64. USB Interrupt Control B lo ck Diagram
TXCMP
UEPSTAX.0
RXOUTB0
UEPSTAX.1
RXSETUP
UEPSTAX.2
STLCRC
UEPSTAX.3
EPXIE
UEPIEN.X
EPXINT
UEPINT.X
SOFINT
USBINT.3
ESOFINT
USBIEN.3
SPINT
USBINT.0 ESPINT
USBIEN.0
EUSB
IE1.6
Endpoint X (X = 0..6)
EORINT
USBINT.4
WUPCPU
USBINT.5
EWUPCPU
USBIEN.5
RXOUTB1
UEPSTAX.6
EEORINT
USBIEN.4
NAKOUT
UEPCONX.5
NAKIN
UEPCONX.4 NAKIEN
UEPCONX.6
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Registers
Rese t Value = 0000 0000b
Table 64. USB Global Control Register - USB CO N (S:BCh)
76 5 43210
USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN
Bit
Number Bit
Mnemonic Description
7 USBE
USB Ena b le
Set this bit to enable the USB controller.
Clear this bit to disable and reset the USB controller, to disable the USB
transceiver and to disable the USB controller clock inputs.
6 SUSPCLK Su spend USB Clock
Set this bit to disable the 48MHz clock input (Resume Detection is still active).
Clear this bit to enable the 48MHz clock input.
5 SDRMWUP
Send Remote Wake-up
Set this bit to force an external interrupt on the USB controller for Remote Wake
UP purpose.
An upstream resume is send only if the bit RMWUPE is set, all USB clocks are
enabl e d A ND the USB bu s w as in SUS P END st at e f or at le as t 5 ms. Se e UPR SM
below. This bit is cleared by software.
4 DETACH
Detach Command
Set this bit to simulate a Detach on the USB line. The VREF pin is then in a
floating state.
Clear this bit to maintain VREF at 3. 3V.
3UPRSM
Upstream R esume (read only)
T hi s bi t is se t by ha r dw a re w he n S DR M WU P ha s been set an d if RM W U PE is
enabled.
This bit is cleared by hardw are after the upstream resume has been sent.
2RMWUPE
Remote Wake-Up Enable
Set this bit to enabled request an upstream resume signaling to the host.
Clear this bit otherwise.
Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP
feature for t he device.
1CONFG
Configured
This bit should be set by the device firmware after a SET_CONFIGURATION
request with a non-zero val ue h as been correctly processed.
It should be cleared by the device fir mware when a SET_CONF IGURATION
requ est with a zero value is received. It is cleared by hardware on hardware reset
or w hen an USB rese t i s de tect ed on t he bus (S E0 state f or at le as t 32 Full S pe ed
bit times: typically 2.7 μs).
0FADDEN
Function Address Enable
This b it shou ld be set by the device fir m ware after a successful status phase of a
SET_ADDRESS t r ansaction.
It should not be cleared afterwards by the device firmware. It is cleared by
hard ware on hardware reset or whe n an USB res et is recei ved (see above).
When this bit is cleared, the default function address is used (0).
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Rese t Value = 0000 0000b
Table 65. USB Global Interrupt Register - USBINT (S:BDh)
76543210
- - WUPCPU EORINT SOFINT - - SPINT
Bit Number Bit
Mnemonic Description
7 - 6 - Reserved
The value read from these bits is always 0. Do not change these bits.
5 WUPCPU
Wake-up CPU Interrupt
This bit is set by hardware when the USB co ntro ller is in SUSPEND state and is
re-activated by a non-idle signal FROM USB line (not by an upstream resume).
This triggers a USB interrupt when EWUPCPU is set in the Table on page 119.
When receiving this interrupt, user has to en able all USB clock inputs.
This bit should be cleared by software (USB clocks must be enabled before).
4 EEORINT
End of Reset Interrupt
This bit is set by hardware when a End of Reset has be en detected by the USB
controller. This triggers a USB interrupt when EEORINT is set in the Table on
page 119.
This bit should be c leare d by software.
3SOFINT
Start Of Frame Interrupt
This bit is set by hardware when an USB Start Of Frame PID (SOF) has bee n
detected. This triggers a USB interrupt when ESOFINT is set in the Table on
page 119.
This bit should be c leare d by software.
2-1 - Reserved
The value read from these bits is always 0. Do not change these bits.
0SPINT
Suspend Interrupt
This bit is set by hardware when a USB Suspen d (Idle bus for three frame
periods: a J state for 3 ms) is detected. This triggers a USB interrupt when
ESPINT is set in USBIEN register (Table 66 on page 119).
This b it must be cleared by softw are before powering the microcontroller down
as it disables the USB pads to reduce the power consumption.
119
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Rese t Value = 0001 0000b
Rese t Value = 1000 0000b
Table 66. USB Global Interrupt Ena ble Register - USBIEN (S:BEh)
76543210
- - EWUPCPU EEORINT ESOFINT - - ESPINT
Bit Number Bit
Mnemonic Description
7 - 6 - Reserved
The value read from these bits i s always 0. Do not change these bits.
5EWUPCPU
Enab le Wake -up CPU Interru pt
Set this bit to enable Wa ke-up CPU Interrupt.
Clear this bit to disable Wake-up CPU Interrupt.
4 EEORINT Enab le End of Reset Inte r rupt
Set this bit to enable End of Reset Interrupt. This bit is set after reset.
Clear this bit to disable End of Reset Interrupt.
3 ESOFINT Enab le SOF Inte r rupt
Set this bit to enable SOF Interrupt.
Clear this bit to disable SOF Interrupt.
2-1 - Reserved
The value read from these bits i s always 0. Do not change these bits.
0 ESPINT En ab le Suspe nd Inte rr up t
Set this bit to enable Suspend Interrupts (See Table 65 on page 118 ).
Clear this bit to disable Suspend Interrupts.
Table 67. USB Address Regist er - USBADDR (S:C6h)
76543210
FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
Bit
Number Bit
Mnemonic Description
7FEN
Function Enable
Set this bit to enable the function. FADD is reset to 1.
Cleared this bit to disable the function.
6-0 UADD[6:0]
USB Address
This field contains the default address (0) after power-up or USB bus reset.
It should be written with the va lue set by a SET_ADDRESS request received by
the device firmware.
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Rese t Value = 0000 0000b
R eset Value = 1000 0000b when UEPNUM = 0
Reset Value = 0000 0000b otherwise
Tab le 68. USB Endpoint Number - UEPNUM (S:C7h)
76543210
- - - - EPNUM3 EPNUM2 EPNUM1 EPNUM0
Bit Number Bit Mnemonic Description
7 - 4 - Reserved
The value read from these bits is always 0. Do not change these bits.
3 - 0 EPNUM[3:0]
Endpoint Num be r
Set this field with the number of the endpoint which should be accessed when reading or writing to, USB Byte
Count Register X (X=EPNUM set in UEPNUM Register) - UBYCTX (S:E2h) or USB E ndpoint X Control Register -
UEPCONX (S:D4h). This value can be 0, 1, 2, 3, 4, 5 or 6.
Tab le 69. USB Endpoint X Control Regi st er - UEPCONX (S: D4h)
76543210
EPEN NAKIEN NAKOUT NAKIN DTGL EPDIR EPTYPE1 EPTYPE0
Bit Number Bit Mnemonic Description
7 EPEN
Endpoint Enable
Se t t his bi t to enab le t he en dpo in t acc ord in g t o th e d ev ic e co nfi gu r atio n. E ndp oi nt 0 wil l alw ay s b e e nabl ed af t er
a hardware or USB bus reset and participate in the device configuration.
Clear this bit to disable t he endpoint according to the device configuration.
6 NAKIEN NAK Interrupt Enable
Set this bit to enable NAKIN and NAKOUT Interrupt.
Clear this bit to disable NAKIN and NAKOUT Interrupt.
5NAKOUT
NAK OUT Sent
This bit is set by hardware when the a NAK handshake is sent by the USB controller to an OUT request from
the Host. This genera tes an interrupt if the NAKIEN bit is set.
This bit shall be cleared by software.
4 NAKIN
NAK IN Sent
This bit is set by hardware when the a NAK handshake is sent by the USB controller to an IN request from the
Host. This generates an interrupt if the NAKIEN bit is set.
This bit shall be cleared by software.
3DTGL
Data Toggle (Read-only)
This bit is set by hardware when a valid DATA0 packet is received and accepted.
This bit is cleared by hardware when a valid DATA1 packet is received and ac cepted.
2 EPDIR
Endpoint Direction
Set this bit to configure IN direction fo r Bulk, Interrupt and Isochr onous endpoints.
Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
This bit has no effect for Control endpoints.
1-0 EPTYPE[1:0]
Endpoint Type
Set this field according to the endpoint configuration (Endpoint 0 will always be configured as control):
00Control endpoint
01Isochronous endpoint
10B ul k en dpo int
11 In t e rr u pt en dpo int
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Reset Value = 0000 0000b
Tab le 70. USB Endpoint Status and Control Register X - UEPSTAX (S:CEh) X=EPNUM set in UEPNUM Register)
76543210
DIR RXOUTB1 STALLRQ TXRDY STL/CRC RXSETUP RXOUTB0 TXCMP
Bit
Number Bit
Mnemonic Description
7DIR
Control End point Direction
This bit is used only if the endpoint is configured in the control type (see“USB Endpoint X Control Register - UEPCONX (S:D4h)”
on page 120).
This bit determines the Control data and status direction.
The device firmware should set this bit ONL Y for the IN data stage, before any other USB operation. Otherwise, the device
firmware should clear this bit.
6 RXOUTB1
Received OUT Data Bank 1 for Endpoint 6 (Ping-pong Mode)
This bit i s set by hardware after a n ew pac ket has been stored in the end point FIFO Data bank 1 (only in Ping-pong mo de).
Then, the endpoint interrupt is triggered if enabled (see “USB Global Interrupt Register - USBINT (S:BDh)” on page 118) and all
the following OUT packets to the endpoint bank 1 are rejected (NAK’ed) until this bit has been cleared, excepted for Isochronous
Endpoints.
This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO.
5STALLRQ
Stall Handshake Request
Set this bit to request a STALL answer to the host for the next handshake.
Clear this bit otherwise.
F or C ON TR O L en dpo ints: cl ea r ed by ha rdw a r e whe n a va lid SE TU P PI D is r ec ei v ed .
4 TXRDY
TX Packet Ready
Set this bit after a packet has been written into the endpoint FIFO for IN data transfers. Data should be written into the endpoint
FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet.
This bit is cleared by hardware, as soon as the packet has been sent for Isochronous endpoints, or after the host has
acknowledged the packet for Control, Bulk and Interrupt endpoints. When this bit is cleared, the endpoint interrupt is triggered if
enabled (se e Table 65 on page 118).
3 STLCRC
Stall Sent / CRC error flag
- For Control, Bulk and Interrup t Endpoints:
This bit is set by hard ware after a STALL handshake has been sent as reques ted by STALLRQ. Then, the endpoint interrupt is
triggered if enabled (see“” on page 118)
It should be clear ed by the device firmware.
- Fo r Isoc hr onou s Endp oints (Read-Only):
This bit is set by ha rdware if the l ast received dat a is corrupted (CRC error on data).
This bit is up dated by ha rdware when a new data is received.
2 RXSETUP
Received SETUP
This bit i s set by hardware when a valid SETUP packet has been received from the host . Then, al l t he other bits of the register
are cleared by hardware and the endpoint interrupt is triggered if enabled (see Table 65 on page 118).
It should be cleared by the device firmware after reading the SETUP data from the endpoint FIFO.
1 RXOUTB0
Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints)
This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the endpoint interrupt is
triggered if enabled (see“” on page 118) and all the following OUT packets to the endpoint bank 0 are rejected (NAK’ed) until this
bit has been cleared, excepted for Isochronous Endpoints. Ho wever, for control endpoint s, an early SETUP transaction may
overwrite the content of the endpoint FIFO, even if its Data packet is received while this bit is set.
This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO.
0TXCMPL
Transmitted IN Dat a Complete
This bit is set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been accepted
(ACK’ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled (see Table
65).
This bit sh ould be cleare d by the device firmwar e before setting TXRDY.
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Reset Value = XXXX XXXXb
Rese t Value = 0000 0000b
Table 71. USB FIFO Data Endpoint X (X=EPNUM set in UEPNUM Register) -
UEPDATX (S:CFh)
76543210
FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0
Bit
Number Bit
Mnemonic Description
7 - 0 FDAT[7:0] Endpoint X FIFO data
Data byte to be written to FIFO or data byte to be read from the FIFO, for the
Endpoin t X (see EPNUM ).
Table 72. USB Byt e Count Register X (X=EPNUM set i n UEP NUM Register) - UBYCTX
(S:E2h)
76543210
- BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from these bits is always 0. Do not change this bit.
6 - 0 BYCT[6:0] Byte Count LSB
Least Significant Byte of the byte count of a received data packet. This byte count
is equal to the number of data bytes received after the Data PID.
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Rese t Value = 0000 0000b
Table 73. USB Endpoint FIFO Reset Register - UEPRST (S:D5h)
76543210
- EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from these bits is al ways 0. Do not change this bi t.
6EP6RST
Endpoint 6 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
5EP5RST
Endpoint 5 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
4EP4RST
Endpoint 4 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
3EP3RST
Endpoint 3 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
2EP2RST
Endpoint 2 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
1EP1RST
Endpoint 1 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
0EP0RST
Endpoint 0 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
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Rese t Value = 0000 0000b
Table 74. USB Endpoint Interrupt R egister - UEPINT (S:F8 h read-only)
76543210
- EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from t hese bits is always 0. Do not change th is bit.
6 EP6INT
En dpoint 6 I nterrupt
This bit is set by hardware when an interrupt has been det ected on the endpoint 6.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP6INTE bit in the U EPIEN register is set.
This bit is clea red by hardware when all the interrupt sources are cleared.
5 EP5INT
En dpoint 5 I nterrupt
This bit is set by hardware when an interrupt has been det ected on the endpoint 5.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP5INTE bit in the U EPIEN register is set.
This bit is clea red by hardware when all the interrupt sources are cleared.
4 EP4INT
En dpoint 4 I nterrupt
This bit is set by hardware when an interrupt has been det ected on the endpoint 4.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP4INTE bit in the U EPIEN register is set.
This bit is clea red by hardware when all the interrupt sources are cleared.
3 EP3INT
En dpoint 3 I nterrupt
This bit is set by hardware when an interrupt has been det ected on the endpoint 3.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP3INTE bit in the U EPIEN register is set.
This bit is clea red by hardware when all the interrupt sources are cleared.
2 EP2INT
En dpoint 2 I nterrupt
This bit is set by hardware when an interrupt has been det ected on the endpoint 2.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP2INTE bit in the U EPIEN register is set.
This bit is clea red by hardware when all the interrupt sources are cleared.
1 EP1INT
En dpoint 1 I nterrupt
This bit is set by hardware when an interrupt has been det ected on the endpoint 1.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP1INTE bit in the U EPIEN register is set.
This bit is clea red by hardware when all the interrupt sources are cleared.
0 EP0INT
En dpoint 0 I nterrupt
This bit is set by hardware when an interrupt has been det ected on the endpoint 0.
The interrupt sources are part of UEPSTAX register and can be : TXCMP,
RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when
the EP0INTE bit in the U EPIEN register is set.
This bit is clea red by hardware when all the interrupt sources are cleared.
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Rese t Value = 0000 0000b
Table 75. USB Endpoint Interrupt Ena ble Register - UEPIEN (S:C2h)
76543210
- EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE
Bit Number Bit Mnemonic Descriptio n
7-
Reserved
The value read from t hese bits is always 0. Do not change th is bit.
6EP6INTE
Endpoint 6 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
5EP5INTE
Endpoint 5 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
4EP4INTE
Endpoint 4 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
3EP3INTE
Endpoint 3 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
2EP2INTE
Endpoint 2 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
1EP1INTE
Endpoint 1 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
0EP0INTE
Endpoint 0 Interrupt Enable
Set this bit to enable the interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
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Serial I/O Port The serial I/O port in the AT8xC5122/23 is compatible with the serial I/O port in the
80C52.
The I/O port pr ovides both synchronous and asynchronous communication modes. It
operat es a s an Un iversal Async hronous Receiver and Tran smitter (UART ) in th ree full-
duplex m odes (Mod es 1, 2 an d 3). Asy nchronous transmiss ion and recept ion can occ ur
simultane ous ly and at different baud rates
Serial I/O port includes the f ollowin g enhancements:
• Framing error detection
• Automatic address recogniti on
Framing Error Detection Fra ming bi t erro r detec tion is provid ed fo r the th ree asyn chro nous modes (Mo des 1, 2
and 3). T o enable the framing bit error de tection feat ure, set SMOD0 bit in PCON regis-
ter (See Figure 65).
Fi gure 65. Framing Error Block Diagram
W hen this feature is enabl ed, the receiver chec ks each incom ing data frame for a valid
stop bit. An invalid stop bit may result f rom noise on the serial l ines or f rom simultaneous
tran smissio n by two C PUs . If a valid st op bit is n ot found, t he Fram ing Error bit (FE) i n
SCO N register (See Figure 70 on page 130) bit is set.
Softwa re may exa mine FE b it after each reception to ch eck for data erro rs. Once set,
only s oftware or a reset can clear FE bi t. Subsequ ently received fram es with valid stop
bits cannot clear FE bit. Whe n FE f eature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 66 and Figure 67).
Fi gure 66. UART Timings in Mode 1
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART Framing Error Control
SM0 to UART Mode Control (SMOD0 = 0)
Set FE Bit if Stop Bit is 0 (Framing Error) (SMOD0 = 1
)
SCON (98h)
PCON (87h)
Data Byte
RI
SMOD0=X
Stop
Bit
Start
Bit
RXD D7D6D5D4D3D2D1D0
FE
SMOD0=1
127
AT8xC5122/23
4202E–SCR–06/06
Fi gure 67. UART Timings in Modes 2 and 3
Automatic Address
Recognition The automatic address rec og nition f eature is enabled when the multiprocessor com m u-
nication feature is enabled (SM2 bit in SCO N register is set).
Impl ement ed in hard ware, auto matic add ress recog nition enh ances t he mult iprocessor
communication feature by allowing the serial port to examine the address of each
incoming c ommand frame. Only when the serial port recognizes its own address, the
receiver sets RI bit i n SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command f rames address ed to other devices.
If desired, y ou may enabl e the automatic address rec ognition feature in mode 1. In this
configur ation, the stop bit takes the place of t he ninth data bit. Bit RI is set only when the
receive d comm and frame add re ss matche s the device’s address and is terminated by a
valid stop bit.
To support aut om atic addres s rec ognition, a device is identified by a given ad dres s and
a broadca st address.
Note: The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCO N regist er i n mode 0 has no effect).
Given Address E ach device has an individual address that is specified in SADDR regi ster; the SADEN
regi ster is a mask byte that contai ns don’t care bits (define d by zero s) to form the
dev ice’s given address. The don’t care bits pr ovide the flexibility to ad dres s one or more
sla ve s at a time. The follow ing ex am ple illu str at es how a given address is form ed.
To address a device by its individual address, the SADEN m ask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XX b
The following is an example of how to use given addresses to address different slaves:
Sl av e A: SADD R1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SA DD R1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0011b
SADEN1111 1101b
Given1111 00X1b
RI
SMOD0=0
Data byte Ninth
bit Stop
bit
Start
bit
RXD D8D7D6D5D4D3D2D1D0
RI
SMOD0=1
FE
SMOD0=1
128
AT8xC5122/23
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The SADEN by te is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LS B) is a don’t care bit; for slaves B and C, bit 0 is a 1. To commu-
nicate with slave A only, the master must send an address where bit 0 is clear (e.g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bi t 1 is a don’t care bi t. To c ommunicate with
slaves B and C, but not slave A, the master must send an address wit h bits 0 and 1 both
set (e.g . 1111 0011b).
To communicate wit h slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcas t Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t care bits, e.g.:
SADDR0101 0110b
SADEN 1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’ t care bits provides flexibility in defining the broadcast add ress, however
in m ost applicat ions, a broa dcast addre ss is FFh. The f ollowing is an e xample of us ing
broadc ast addresses :
Sl av e A: SADD R1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SA DD R1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR =1111 0010b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 i s a don’t care bit; for slave C, bit 2 is set. To communicate with
all o f the s laves, the m as ter must send an addres s FF h. To com mu nicat e with slaves A
and B, but not slave C, the m aster can send and address FBh.
Reset Addresse s On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and
broadc ast addresses are XXXX XXXXb (al l don’t care bits). This en su res that the s erial
port will reply to any address, and so, that it is bac kwards compatible with the 80C51
microcont rollers that does not support automatic address recognition.
Tim er 1 When using the Timer 1, the Baud Rate is derived from the overf low of the timer. As
shown in Figure 68 t he Timer 1 is used in its 8-bit auto-rel oad mode). SMOD1 bit in
PCO N register allows doubling of the generated baud rate.
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Fi gure 68. Timer 1 Baud Rate Generator Bl ock Diagram
Internal Baud Rate Generato r When us ing the Internal Baud Rat e Generator, the Baud Rate is derived from the over-
flow of the timer. As shown in Figure 69 the Internal Baud Rate Generator is an 8-bit
auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6
depending on the SPD bit in BDRCON register (see Table 82 on page 136). The Int ernal
Baud Rate Generator is enabled by setting BRR bit in B DRCON register. SM OD1 bit i n
PCO N register allows doubling of the generated baud rate.
Fi gure 69. Internal Baud Rate Generator Block Diagram
Sync h r on ous Mo de ( Mo de 0) M ode 0 is a half-duplex, sy nchronous m ode, which is co mmonly used to e xp and the I/0
cap ab ilities of a dev ice wit h sh ift reg iste rs. The tr an smit d ata (T XD) pin outp uts a set o f
eight clock pulses while the receive data (RXD ) pin transmits or receives a byte of da ta.
The 8 -bit data are transm itted and rec eived lea st-sig nificant bit (LS B) first. Shift s occur
at a fixed Baud Rate (see Section “Baud Rate Selection (Mode 0)”). Figure 70 shows
the serial port block diagram in Mode 0.
TR1
TCON.6
0
1
GATE1
TMOD.7
Overflow
C/T1#
TMOD.6
TL1
(8 bi ts )
TH1
(8 bi ts )
INT1#
T1
CK_
T1 / 6 0
1
SMOD1
PCON.7
/ 2
T1
CLOCK
To serial Port
0
1
Overflow
SPD
BDRCON.1
BRG
(8 bits)
BRL
(8 bits)
CK_
SI / 6
IBRG
CLOCK
BRR
BDRCON.4
0
1
SMOD1
PCON.7
/ 2 To serial Port
130
AT8xC5122/23
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Fi gure 70. Serial I/O Port Block Di agram (Mode 0)
Transmis sion (Mode 0) To start a tran smission mode 0, write to SCON register clearing bits SM0, SM1.
As shown in Figure 71, writing the byte to tra nsmit to SBUF register starts the transm is-
sion. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle
composed of a high level then low level signal on TXD. During the eighth clock cycle the
MSB (D7) is on the RX D pi n. Then, hardwa re drives th e RX D pin h igh and asserts TI to
indicat e the end of the transmission.
Fi gure 71. Transmission Waveforms (Mode 0)
Reception (Mode 0) To start a re ceptio n in m ode 0, w rite to S CO N re gister cleari ng S M0, SM1 a nd RI bits
and setting the REN bit.
As sho wn i n Fi gure 72 , Clo ck i s pu lsed and t he L SB ( D0 ) is sam pl ed on the RXD pin .
The D0 bit is th en shifte d into the shift registe r. After ei ght samp ling, the M SB (D7) is
shifted into the shift register, and hardware asserts RI bit to indicate a completed recep-
tion. Software can then read the received byte from SBUF register.
Fi gure 72. Reception Waveforms (Mode 0)
IBRG
CLOCK
TXD
RXDSBUF Tx SR
SBUF Rx SR
SM1
SCON.6 SM0
SCON.7
Mode Decoder
M3 M2 M1 M0
Mode
Controller
RI
SCON.0
TI
SCON.1
CK_
T1 Baud Rate
Controller
Wr ite to SBU F
TXD
RXD
TI
D0 D1 D2 D3 D4 D5 D6 D7
Wr ite to SCO N
TXD
RXD
RI
D0 D1 D2 D3 D4 D5 D6 D7
Set REN, Clear RI
131
AT8xC5122/23
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Baud Rate Selection (Mode 0) I n mod e 0, baud rate can be either fixed or variable.
As show n in Figure 73, the selection is done using M0SRC bit in BD RCON register.
Figure 74 gives the bau d rate calculation formulas for each baud rate source.
Fi gure 73. Baud Rate Source Selection (Mode 0)
Fi gure 74. Baud Rate Formulas (Mod e 0)
Asyn chronous Modes
(Modes 1, 2 and 3) The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 75
shows the Serial Port block diagram in such asy nchronous modes.
Fi gure 75. Serial I/O Port Block Diagram (Modes 1, 2 and 3)
Mode 1 Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 76) consists of
10 bit s: o ne sta rt, eigh t d ata bits and one stop bit. Se rial da ta is tran smitted on t he TXD
pin and received on the RXD pin. When a data is received, the stop bit is read in the
RB8 bit in SCON register.
0
1
M0SRC
BDRCON.0
CK_
SI / 6
To Serial Por t
IBRG
CLOCK
Baud_Rate
=
6(1-SPD) ⋅ 32
⋅ (256 -BRL)
2SMOD1
⋅ FCK_SI
BRL = 256
-
6(1-SPD) ⋅ 32
⋅ Baud_Rate
2SMOD1
⋅ FCK_SI
a. Fixed Formula b. Variable Formula
Baud_Rate = 6
FCK_SI
TB8
SCON.3
IBRG
CLOCK
RX
D
TXDSBUF Tx SR
Rx SR
SM1
SCON.6 SM0
SCON.7
Mode Decod er
M3 M2 M1 M0
RI
SCON.0
TI
SCON.1
Mode & Clock
Controller
SBUF Rx RB8
SCON.2
SM2
SCON.4
T1
CLOCK
CK_
SI
132
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Fi gure 76. Data Frame Format (Mode 1)
Modes 2 and 3 Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 77)
consi sts of 11 bits: one start bit, eigh t data bits (transmitted and received LS B first), one
programm able ninth data bit a nd one stop bit. Serial data is transmitted on the TXD pin
an d rece iv ed o n th e RXD pi n. O n rece ive, t he n int h b it i s re ad f rom RB 8 bit i n S CO N
regi ster . On tran smit, t he ni nth dat a bi t is w ritten t o TB8 bit in SCO N re gister. Alt erna-
tively, you can use the ninth bit as a co mmand/ dat a flag.
Fi gure 77. Data Frame Format (Modes 2 and 3)
Transm ission
(Modes 1, 2 and 3) To ini tiate a transm ission, write to SCO N register, se ttin g SM0 and S M1 bits accordin g
to Fi gure 70 on page 130, and setti ng the ninth bit by writing to TB8 bit. Then, writing the
byte to be transmitted to SBUF register starts the transm ission.
Reception
(Modes 1, 2 and 3) To prepare fo r a reception, write to SCON register, setting SM 0 and SM1 bits accordi ng
to Fi gure 70 on page 130, and setting REN bit. T he actual reception is then initiated by a
detected high-to-low transition on the RXD pin.
Fra m in g Er ror De te ct i on
(Modes 1, 2 and 3) Fr ami ng er ror det ect ion is pro vide d fo r th e th ree a syn chron ou s mo des. To enab le t he
framing bit error detection feature, set SMOD0 bit in PCON register as shown in
Figure 78.
W hen this feature is enabl ed, the receiver chec ks each incom ing data frame for a valid
stop bit. An invalid stop bit may result f rom noise on the serial l ines or f rom simultaneous
tra nsmis sion by two device s. If a v alid s top bi t is no t foun d, the so ftw are set s FE bit in
SCON register.
Softwa re may exa mine FE b it after each reception to ch eck for data erro rs. Once set,
only s oftwa re or a chip reset cle ar FE bit. S ubsequently rec eived frames with valid st op
bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on
stop bit instead of the last data bit as detaile d in Figure 76 and Fi gure 77.
Fi gure 78. Framing Error Block Diagram
Mode 1 D0 D1 D2 D3 D4 D5 D6 D7
Start bit 8-bit data Stop bit
Mod e s 2 and 3 D0 D1 D2 D3 D4 D5 D6 D8
Start bit 9- bit data Stop bi t
D7
SM0
1
0
SMOD0
PCON.6
SM0/FE
SCON.7
Framing Error
Controller FE
133
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Baud Rate Selection
(Modes 1 and 3) In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud
Rate Gen erator and allows different baud rate in reception and transm ission.
As shown in Figure 79 the selection is done us ing RBCK and TBCK bits in BDRCON
register.
Figure 80 gives the baud rate calculation formulas for each baud rate source while
Table 76 details Internal Baud Rate Generator configuration for different peripheral
clock freq uencies and giving baud rates closer to the standard baud rates.
Fi gure 79. Baud Rate Source Selection (Modes 1 and 3)
Fi gure 80. Baud Rate Formulas (Mod es 1 and 3)
0
1
RBCK
BDRCON.2
T1
CLOCK To ser ial
IBRG
CLOCK
recepti on Port 0
1
TBCK
BDRCON.3
T1
CLOCK To serial
IBRG
CLOCK
transmissi on Po
rt
/ 16/ 16
Baud_Rate
=6
(1-SPD)
⋅ 32
⋅ (256 -BRL)
2
SMOD1
⋅ FCK_SI
BRL = 256
-
6(1-SPD
)
⋅ 32 ⋅ Baud_Rate
2SMOD1 ⋅ FCK_SI
Baud_Rate
=
6
⋅ 32
⋅ (256 -TH1)
2SMOD1
⋅ FCK_T1
TH1 = 256
-
192
⋅ Baud_Rate
2
SMOD1
⋅ FCK_T1
a. IBRG Formula b. T1 Formula
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AT8xC5122/23
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Baud Rate Selection (Mode 2) I n mo de 2, the bau d ra te can only b e pr ogram med to two fi xed v alues: 1 /16 o r 1/32 of
the peripheral clock frequency .
As shown in Figure 81 the selecti on is done using SMOD1 bit in PCON regist er.
Figure 82 gives the bau d rate calculation formula dependin g on the selection.
Fi gure 81. Baud Rate Generator Se lection (Mode 2)
Fi gure 82. Baud Rate Formula (Mode 2)
For mode 0 for UART, thanks t o the bit M0SRC located in BDRCON register (Table 82)
Tab le 76. I n ternal Bau d Rate G e nerator V al u e
Baud Rate
FCK_IDLE= 4 MHz FCK_IDLE= 8 MHz F CK_IDLE= 9.6 MHz
SPD SMOD1 BRL Error% SPD SMOD1 BRL Error% SPD SMOD1 BRL Error%
115200 1 1 254 8.51 1 1 252 8.51 1 1 251 4.17
57600 1 1 252 8.51 1 1 247 3.55 1 1 246 4.17
38400 1 1 249 6.99 1 1 243 0.16 1 1 240 2.34
19200 1 1 243 0.16 1 1 230 0.16 1 1 225 0.81
9600 1 1 230 0.16 1 1 204 0.16 1 1 194 0.81
4800 1 1 204 0.16 1 1 152 0.16 1 1 131 0.00
Baud Rate
FCK_IDLE= 12 MHz FCK_IDLE= 16 MHz FCK_IDLE= 24 M Hz
SPD SMOD1 BRL Error% SPD SMOD1 BRL Error% SPD SMOD1 BRL Error%
115200 1 1 249 6.99 1 1 247 3.55 1 1 243 0.16
57600 1 1 243 0.16 1 1 239 2.12 1 1 230 0.16
38400 1 1 236 2.34 1 1 230 0.16 1 1 217 0.16
19200 1 1 217 0.16 1 1 204 0.16 1 1 178 0.16
9600 1 1 178 0.16 1 1 152 0.16 1 1 100 0.16
4800 1 1 100 0.16 1 1 48 0.16 1 1 N/A N/A
0
1
SMOD1
PCON.7
CK_
SI / 2 ³ 16 To Serial Por
t
Baud_Rate = 32
2
SMOD1
⋅ FCK_SI
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AT8xC5122/23
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Registers
Rese t Value = 0000 0000b (Bit addressable)
Table 77. Serial Control Register - SCON (98h)
76543210
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number Bit
Mnemonic Description
7
FE
Framing Error bit (SM OD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Se t by ha r dware w he n an invali d sto p bi t is de tec ted.
SMOD0 in PCON register must be set to enable acc ess to the FE bit
SM0 Serial port Mode bit 0 (SMOD0=1)
Refer to SM1 for serial port mode selection.
SMOD0 in PCON register must be cleared to enable access to the SM0 bit
6SM1
Serial port Mode bit 1
SM0 SM1 Mode DescriptionB aud Rate
0 0 0 Shift Register FCk_IDLE/6
0 1 1 8-bit UARTVariable
1 0 2 9-bit UART FCK_IDLE /3 2 or /16
1 1 3 9-bit UARTVariable
5SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable mul tiprocessor communication feature in mode 2 and 3, and
eventually mode 1.
This bit should be cleared in mode 0.
4REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
Clear to tr ansmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2RB8
Receiver Bit 8/Nint h bit re ceived in modes 2 and 3
Cleared by hardware if 9th bit received is a logi c 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1TI
Transmit Interrupt flag
Cle ar to ac k no w le dg e int er rupt .
Set by hardware at the end of the 8th bit ti me in mode 0 or at the beginning o f the
s top bit in t he other modes.
0RI
Receive Interrup t flag
Cle ar to ac k no w le dg e int er rupt .
Set by hardware at the end of the 8th bit ti me in mode 0, see Figure 66 a nd Figure
67 in the other modes.
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AT8xC5122/23
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Rese t Value = 0000 0000b
Rese t Value = 0000 0000b
Reset Value = XXXX XXXXb
Rese t Value = 0000 0000b
Table 82. Baud Rate Control Register - BDRCON - (9Bh)
Rese t Va lue = XXX0 0000b (Not bit addressable)
Table 78. Slave Address Mask Register for UART - S AD EN (B9h)
76543210
Table 79. Slave Address Register for UART - SADDR (A9h)
76543210
Table 80. Serial Buffer Register for UART - SBUF (99h)
76543210
Table 81. Baud Rate Reload Register for the internal baud rate generator,
UART - BRL (9Ah)
76543210
7 6 5 4 3 2 1 0
---BRR TBCK RBCK SPD M0SRC
Bit
Number Bit
Mnemonic Description
7 - 5 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
4BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to s tart the internal Baud Rate Generator.
3TBCK
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 for the Baud Rate Generator.
S et to sele ct inte rna l Bau d Rate Ge ne rat or.
2RBCK
Re cept i on Bau d Rate G ener at or Sele cti on bit for UART
Cleared to select Timer 1 for the Baud Rate Generator.
S et to sele ct inte rna l Bau d Rate Ge ne rat or.
1 SPD Baud Rate Speed Control b it for UART
Cleared to select t he SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
0M0SRC
Baud Rate Source select bit in Mode 0 for UART
Cleared to select FCK_SI /6 as the Baud Rate Generator.
Set to s elect the internal Baud Rate Generator for UART in mode 0.
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Serial Po rt Interface
(SPI) O nly for AT8xC5122 .
The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous,
serial communicat ion between the MCU and peripheral devices, including other MCUs.
Features F eat ures of the SPI module include the following:
• Full-duplex, three-wir e synchronous transfers
• Master or Slave operation
• Eight programmable Mast er clock rates
• Serial clock with program ma ble polarity and phase
• Master Mode fault error flag with MCU interrupt capabil ity
• Write co llis ion flag pr ot e c ti o n
Signal Description F igure 83 sh ows a t ypical SP I bus co nfigurat ion usin g one Ma ster control ler and m any
Slave peripherals. The bus is made of three wires connecting all the devices:
Fi gure 83. Typical SPI Bus
The Mast er de vi ce se lects the ind ivid ual S lave dev ices by usin g fo ur pin s of a paral lel
port to control the four SS pins of t he Slave devices.
Master Output Slave Inp ut
(MOSI) Thi s 1-bit s igna l is direct ly conne cted b etwe en the Mast er Devi ce an d a Slave Devi ce.
The MOSI line is us ed to trans fer data in series from the Mast er to the Slave. Therefore,
it is an out put si gnal from the Master, a nd an i nput s ignal to a Sl ave . A byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
Master Inpu t Slave Output
(MISO) Thi s 1-bit sig nal i s direct ly conne cted b etwe en the Slave De vice and a M aste r Device.
The MISO line is us ed to trans fer data in series from the Slave to the Mas ter. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit
word) is transmitted most significant bit (MS B) first, least significant bit (LSB) last.
SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out the devices
through their MOSI and MISO lines. It is driven by the Master for eight cl ock cycles
which allows to exchange one byte on the serial lines.
Sl av e 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
0
1
2
3
Slave 3Slave 4
MISO
MOSI
SCK
SS
Sl av e 2
VDD
Master
PORT
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
138
AT8xC5122/23
4202E–SCR–06/06
Slave Select (SS)Each Slave peripheral is selected by one Slave Select pin (SS). Thi s sign al m ust stay
low for any message for a Slave. Only one Master ( SS high level) can drive the network.
The M aste r may sele ct each S la ve dev ice by s oftware throug h port pins (Figure 8 3). To
pr event bus co nflict s on the MISO li ne, o nly one sl ave should be se lecte d at a time by
the Master for a transmission.
In a M aster confi guration, t he S S l ine can be used i n c onj unction wi th the M ODF f lag in
the SPI Status register (SPSTA) to prevent m ultiple masters from driving MOSI and
SCK (see Section “Error Conditions”, page 1 42).
A high level on the SS pin puts the MIS O line of a Slave SPI in a high-impedanc e sta te.
The SS pin could be used as a general-purpose if the followin g conditions are met:
• The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Mast er i s driving the network
and there is no way that the S S pin will be pulled low. Therefore, the MODF flag in
the SPSTA will never be set (1).
• The Device is conf i gured as a Slave with CPHA and SSDIS control bit s set (2). This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, t he device s hould always be selected and there is no reason
that the Master uses the S S pin to select the communicat ing Slave dev ice.
Baud Rate In Mast er mode, the baud rate can be selected from a baud rate generator which is con-
troled by three bits in the SPCON regist er: SPR2, SPR1 and SPR0. The Master cloc k is
chosen from one of six cl ock rates res ulting from the division of the i nt ernal clock by 4, 8,
16, 32, 64 or 128.
Table 83 gives the different clock rates selected b y SPR2:SP R1: SPR0
Table 83. SPI Master Baud Rate Selection
1. Clearing SSDIS co ntr ol bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in
this mode, the SS is used to start the tr ansmi ssion.
SPR2:SPR1:SPR0 Clock Ra te Baud Rate Divisor (BD)
000 Reserved N/A
001 FCK_SPI /4 4
010 FCK_SPI / 8 8
011 FCK_SPI /16 16
100 FCK_SPI /32 32
101 FCK_SPI /64 64
110 FCK_SPI /128 12 8
111 Reserved N/A
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AT8xC5122/23
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Functional Description Figure 84 shows a detai led structur e of the SPI m odule.
Fi gure 84. SPI Module Block Diagram
Operati ng Mod es The Serial Peripheral In terface can be configured as one of the two modes: Master
mode or Salve mode. The configuration and initialization of the SPI module is made
through one register:
• The Serial Peripheral Co ntrol register (SP CON)
Onc e the SPI is configured, the data exchange is made using:
•SPCON
• The Serial Peripheral Status register (SPSTA)
• The Serial Peripheral Data register (SPDAT)
During an S PI trans mis sion, data is simul taneous ly transmitte d (shifted ou t serially) and
received (shifted in serially). A serial clock line (SCK) s ynchronizes shifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) a llows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activ i ties.
W hen the Mast er device transm its data to the Slave device via the MOS I line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission wi th both data out and data in synchronized with the same clock
(Figure 85).
Shift Register01
234567
In te rnal B u s
Pin
Control
Logic MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Request
8-bit bus
1-bit s ignal
SS
IntClk
/32
/8
/16 Receive Dat a Register
SPDAT
SPI
Control
SPSTA
CPHA SPR0SPR1CPOLMSTRSSDISSPENSPR2 SPCON
WCOL MODFSPIF -----
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AT8xC5122/23
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Fi gure 85. Full-duplex Master-Slave Interconnection
Ma st er Mo de The SPI operates in Master mode when the Master bit, MSTR (3), in the SPCON register
is set. Only one Master SPI device can initiate transmissions. Software begins the trans-
mission from a Master SPI module by writing to the Serial Peripheral Data Register
(SPDAT). If the shift register is empty, the byte is immediately trans ferred to the shift
regist er. The byt e begin s sh ifting out on M OSI pin under the c ontrol of the serial clock,
SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin.
The transm ission ends w hen the Se rial Periphera l transfer da ta flag, SPIF, i n SPSTA
becomes set. At the s ame time that SPIF bec omes set, the received byt e fr om the Slave
is t ran sfe rred t o th e recei ve data re giste r in S P DAT. Soft war e c lear s SP IF by r eadi ng
the Serial P eripheral Status register (SPSTA) with the SPIF bit se t, and then reading the
SPDAT.
When the pin SS is pulled down during a transmission, the data is interrupted and when
the transmiss ion is established agai n, the data present in the SPDAT is resent.
Slave Mod e The SPI operates in Slave mode when the Master bit , MSTR (4 ), in the SPCON register is
cleare d. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to ’0’ . SS must remain low until the transm ission is complete.
In a Sl ave SPI mod ule, da ta enters t he shift regis te r under th e control of the SC K from
the Master SPI module. After a byte enters the shi ft regi ster, i t is imm ediately transferred
to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow
condition, Slave software must then read the SPDAT before another byte enters the
shift register (5). A Slave S PI must complete the write to the SPDAT (shift register) at
least one bus cycle before the Master SPI sta rts a transmission. If the write to the data
register is late, the SPI transmits the data alread y in t he shift register from the previous
transmission.
Transm is sion Form ats S oft ware c an selec t any of f our c omb inati ons of se rial c lock ( SCK) ph ase an d p olar ity
using two bits in the SPCON: the Clock Polarity (CPOL (6)) and the Clock Phase
(CPHA(4)). CPOL defines the default SCK line level in idle state. It has no significant
effect on the tran smissio n format. CPHA defines the ed ges on which the input dat a are
sample d an d the edges on which the output data are s hifted (Figure 86 and Figu re 87).
The clock phase and polarit y should be identical for the Master SPI device and the com-
munic ating Slave device.
8- bit Shift Register
SPI
Clock Ge nerator
Master MCU
8- bit Shift Register
MISOMISO
MOSI MOSI
SCK SCK
VSS
VDD SSSS Slave MCU
3. The SPI module should be configured as a Master before it is enabl ed (SPEN set). Also
the Master SPI shoul d be configured befo re the Slave SPI.
4. The SPI module shou ld be confi gured as a Slave before it is enabled (SPEN set ).
5. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
6. Before writin g to the CPOL and CPHA bit s, t he SPI should be di sabled (SPEN = ’ 0’).
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AT8xC5122/23
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Fi gure 86. Data Transmission Format (CPHA = 0)
Fi gure 87. Data Transmission Format (CPHA = 1)
As shown in Figure 86, the first SCK edge is the MSB capture strobe. Therefore the
Slave must begin driving its data before the f i rst SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each byte transmi tted (Figure 88).
Fi gure 88. CPHA/SS Timing
Figure 87 shows an SPI transmission in which CPHA is “1”. In this case, the Master
begins driving its MOSI pin on the firs t SCK edge. Therefore, the Slave uses the first
SCK edge as a start transmis sion signal. The SS pin can remain low between t ransmis-
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1MSB LSB
132 45678
Capture Point
SS (to Slave)
MISO (from Slave)
MOS I (from Master)
SCK (CP OL = 1)
SCK (CPOL = 0)
SPEN (internal)
SCK Cycle Nu mber
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1
MSB LSB
132 45678
Capture point
SS (to Slave)
MISO (from Slave)
MOS I (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (internal)
SCK Cycle Number
Byte 1 Byte 2 Byte 3
MISO/MOSI
Master SS
Sl ave SS
(CPHA = 1)
Sla ve S S
(CPHA = 0)
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AT8xC5122/23
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sions (Figure 88). This format m ay be preferable in systems having only one Master and
only one Slave driving the MISO data line.
Error Conditions The following flags in the SPSTA sig nal SPI error conditions.
Mode Fault (MODF) MODF error bit in Master mode SPI indicates that the level on the Slave Select (SS) pin
is incon sistent with t he actu al mode of the device. MO DF is set to wa rn that there m ay
have a multi- master co nfli ct for syst em c ontro l. In this case , the SPI sys tem is affe cted in
the following ways:
• An SPI receiver/error CPU interrupt request is generated.
• The SPEN bit in SPCON is cleared. This disable the SPI.
• The MSTR bit in SPCON is cleared.
When SS Disable (S SDIS) bit in the SPCON register is cleared, the MODF flag is set
when the SS signal b ecomes ’0’.
However, as stated before, for a system with one Master, if the S S pin of the Master
dev ice is pulled l ow, there is no way that anot her Ma ster is attemp ting to driv e th e net-
work. In this c ase, to prevent the MODF flag from bei ng set, software can set the SSDIS
bit in the SPCON register and therefore making the SS pin as a general-purpose I/O pin.
Clearing the M ODF bit is accom plished b y a read of SPSTA regi s ter with MODF bit s et,
followed by a write to the SPCON registe r. SPEN Control bit may be restored to its orig-
inal set state after the MODF bit has been cleared.
Writ e C ollis ion (W C OL ) A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is
done during a transm it sequenc e.
W COL does not cause an interruption, and the transfer continues uninterrupte d.
Clearing t he WCOL bit is done through a software sequence of an access to SPSTA
and an access to SPDAT.
Overrun Condition An overrun condition occurs when the Master device tries to send several data bytes
and the Sla ve dev ice has not c leare d th e SPIF bit is sui ng fr om th e prev iou s dat a by te
transmit ted. In this c ase, the receiver buffer contains the byte sent aft er the SPIF bit was
last cleared. A read of the SPD AT return s this byte. All others bytes are lost.
This condition is not detecte d by the SPI peripheral.
SS Error Flag ( SSERR ) A Synchronous Serial Slave Error occurs when SS goes high before the end of a
rec eived data in slave mode . SSERR d oes n ot cau se in i nterrupt ion, thi s bit is cleare d
by writing 0 to SPEN bit ( reset of the SPI state machin e ).
Interrupts Two SPI status flags can generate a CPU interrupt requests:
Table 84. SPI In te r ru p ts
S erial Perip heral d ata transf er fl ag, SPIF : This b it is set b y ha rdwar e when a transfe r
has been completed. SPIF bit generates transmitter CPU interrupt requests.
Flag Request
S PIF (SP da ta tran sfer) SP I Tra nsm it ter Int erru p t requ es t
MODF (Mode Fa ult) SPI Recei v er/Error Interrupt Request (i f SSDIS = ’0’)
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Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsi st ent with the mode of t he SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests.
Figure 89 gives a logical view of the above statements.
Fi gure 89. SPI Interrupt Requests Generat ion
Registers There are three registers in the module that provide control, status and data storage
functions. These regist ers are describes in the following par agraphs.
Serial Peripheral Control
Register (SPCON) The Serial Peripheral Control Register does the following:
• Selects one of the Master clock rates
• Configures the SPI module as Master or Slave
• Selects serial clock polarity and phase
• Enables the SPI module
• Frees the SS pin for a general-purpose
SSDIS
MODF
CPU Interrupt Request
SPI Receiver/error
CPU Interrupt Request
SPI Transmitter SPI
CPU Interrupt Request
SPIF
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Rese t Value = 000101 00b
Table 85. Serial Peripheral Control Register - S PC ON (C3h)
76543210
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
Bit
Number Bit
Mnemonic R/W
Mode Description
7 SPR2 RW Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate
6 SPEN RW Serial Peri pheral Enable
Clear to disable the SP I inte rfac e (internal reset of the SPI )
Set to enable the SPI interface
5SSDISRW
SS Disable
Clear to enabl e SS i n both Ma s ter and Slave mode s
Se t to di sa bl e SS i n bo th Mast e r and Slave mod es. In Sl ave mo de, t his
bit has no effect if CPHA = ’0’
4MSTRRW
Serial Peri pheral Master
Clear to configure the SPI as a Slave
Set to configure the SPI as a Master
3CPOLRW
Clock Polarity
Clear to have the SCK set to ’0’ in idle state
Set to have the SCK set to ’1’ in idle low
2CPHARW
Clock Phase
Clear to have the data sampled when the SPSCK leaves the idle state
(see CPOL)
Set to have the data sampled when the SPSCK returns to idle state
(see CPOL)
1 SPR1 RW
Serial Peripheral Rate (SPR2:SPR1:SPR0)
000: Res er v e d
001: F CK_SPI /4
010: F CK_SPI/8
011: FCK_SPI/16
0 SPR0 RW
100: F CK_SPI/32
101: F CK_SPI/64
110: FCK_SPI/128
111: Reserved
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Serial Peripheral Status Register
(SPSTA) The Serial Peripheral Status Register contains flags to signal the following
conditions:
• Data transfer comple te
• Write co llis ion
• Inconsistent logic level on SS pin (mode fault error)
Rese t Value = 00X0X XXXb
Table 86. Serial Peripheral Status and Control R egist er - SPSTA (C4h)
76543210
SPIF WCOL SSERR MODF - - - -
Bit
Number Bit
Mnemonic R/W
Mode Description
7 SPIF R
Ser ial Peripheral da ta transfer flag
Clear by hardware to indicate data transfer is in progress or has been
approved by a clearing s equence.
Set by hardware to indicate that the data transfer has been completed.
6WCOLR
Write Collision flag
Cleared by hardware to indicate that no collision has occurred or has
been approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
5 SSERR R Synchronou s Serial Sla ve Error flag
Set by hardware when SS is modi fied before the e nd of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
4MODFR
Mod e Fa ult
Cleared by hardware to indicate that the SS pin is at appropriate logic
level, or has been approved by a clear ing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level
3 - 0 - RW Reserved
The value read from this bit is indeterminate. Do not change these bits.
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Serial Peripheral DATa Register
(SPDAT) The Serial Peripheral Dat a Register (Table 87) is a read/write buf fer for the receive data
register. A write to SPDAT plac es d ata directly into the shift register. No transmit buffer
is available in this model.
A rea d of the S P DAT ret urns t he value locat ed i n t he receive buffer and not t he cont ent
of the shift register.
Reset Value = XXXX XXXXb
Table 87. Serial Peripheral Data Register - SPDAT (C5h)
76543210
R7 R6 R5 R4 R3 R2 R1 R0
Bit Number Bit
Mnemonic Description
7-0 R7:0
Receive dat a bit s
SPCON, SPSTA and SPDAT registers may be read and written at any time while
there is no on-going exchange. H owever, special care should be t aken when
writing to them while a transmission is on-going:
Do not change SPR2, SPR1 and S PR0
Do not change CPHA and CPOL
Do not change MSTR
Clea ring SPEN w ould immediatel y disable the periphera l
Wri ting to the SP D AT wil l ca us e an ove r flo w
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Timers/Counters T he A T8xC5 122D i mpl eme nts two ge neral- purpose , 16 -bit Ti mers/ Coun ters. A lthou gh
they are identified as Timer 0, Timer 1, y ou can independently configure each to operate
in a vari ety o f modes as a Timer or as an e vent Count er. When operating as a T im er, a
Time r/Cou nter ru ns for a prog ramm ed len gth of ti me, then i ssues an interru pt req uest.
W hen ope rating as a Counter, a Timer/Cou nter cou nts ne gative tran sitions on an exter-
nal pin. After a preset number of counts , the Counter issues an interrupt request.
Th e Time r re gisters and ass ociat ed co ntrol regi sters are imp lem ente d as ad dr essa ble
Sp ecial Fun ction Regist ers (SFRs ). Two o f the S FRs pro vide prog ramm able contro l of
the Timers as follows:
• Timer/Counter mode control register (TMO D) and Ti mer/Counter co ntrol register
(TCON) control respectively Timer 0 and Timer 1.
The various operat ing modes of each Timer/Counter are described belo w.
Timer/Counter
Operations For example, a basic operation is Timer registers THx and TLx (x= 0, 1) connected in
casc ade to fo rm a 16-bi t Timer. S etting the r un control b it (TRx) in th e TCON register
(se e Table 88 on pa ge 152) turn s the T imer on by allowin g the sel ected inp ut to incre -
me nt TLx. Whe n TLx overflows, it increments THx and when THx o verflows i t se ts the
Timer overflow flag (TFx) in th e T CON register. Setting the TRx does not clear the THx
and TLx Ti mer registers. Tim er registers can be acc essed t o obt ain the current count or
to e nter preset values. The y c an be read at any time but the T R x bit m us t be c le ared to
preset their values, otherwise the behavior of the Timer/Counter is u npredictable.
The C/ Tx# control bit selects T imer operation or Cou nter operation by s electing the
divided-down system clock or the external pin Tx as the source for the counted signal.
The TRx bit m us t be cleared when changing the operating mode, otherwise the behavior
of the Timer/Coun ter is unpredict able.
For Timer operation (C/Tx#= 0), the Timer register counts the divided-down system
clock. The Timer register is incremented once every peripheral cycle.
Exceptions are the Timer 2 Baud Rate and Clock-Out mode s in which the Timer register
is increment ed by the system clock divided by two.
For Counter operat ion (C/Tx #= 1), the Timer regi ster counts the negative transitions on
the Tx external input pin. The external input is sampled during every S5P2 state. The
Pr ogram m er’s G uide des crib es the no tat ion for th e st ates in a perip hera l cy cle. W he n
the sample is high in one cycle and low in the next one, the Counter is incremented. The
new c oun t val ue app ears in the re gister d uring t he n ext S3P 1 st ate af ter the transit ion
has be en detected. Since it takes 12 states (24 osc illator periods) to recognize a nega-
tive transition, the maximum count rate is 1 /24 of the oscillato r f requency. There are no
restrictions on the duty cycle of the ext ernal input signal, but to ensure t hat a giv en level
is sampled at least once before it changes, it should be held for at leas t one full periph-
eral cycle .
Timer 0 Timer 0 functions as either a Timer or an event Counter in four operating modes.
Figure 90 th rough Figure 96 show the logic configuration of each mode.
Timer 0 is controlled by the f our lower bits of the TM OD register (see T able 89 on page
153) and bits 0, 1, 4 and 5 of the TCON register (see Table 88 on page 152). The TMOD
register selects the method of Timer gating (GATE0), Timer or Counter operation
(T/ C0#) and the op erating m ode (M 10 and M 00). Th e TCON regis te r provide s Time r 0
control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE 0) and inter-
rupt type control bit (IT 0).
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For no rmal Tim er operatio n (GAT E0= 0), sett ing TR0 allows TL0 t o be increm ented by
th e select ed in put. Set ting G ATE0 and T R0 all ows ex te rnal p in INT0 # to con trol Ti mer
operation.
Timer 0 ov erflow (count rolls over from all 1 s to all 0s ) s ets the TF0 flag and ge nerates
an interrupt request.
It is important to stop the Timer/Count er befor e changing modes .
Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 reg-
ister) with a modulo-32 prescaler implemented with the lower five bits of the TL0 register
(se e Figure 90 ). Th e uppe r three bits of the TL0 re gister are indet erminat e and should
be ignored. Prescale r overflow incr ements t he TH0 register.
Figure 91 gives the overflow period calculation formula.
Fi gure 90. Timer/Counter x (x= 0 or 1) in Mode 0
Fi gure 91. Mode 0 Overflow Period Formula
Mode 1 (16-bit Timer) M ode 1 configures T im er 0 as a 16-bit Timer with the TH0 a nd TL 0 regist ers c onnect ed
in a cascade (see Figure 92). The select ed input increments the TL0 regis ter.
Figure 93 gives the overflow period calculation formula when in timer mode.
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow Ti m e r x
Interrup
t
Reques
t
C/Tx#
TM OD re g
TLx
(5 bits)
THx
(8 bits)
INTx#
Tx
FCK_Tx
/6
6
⋅ (16384 – (THx, TLx))
TFxPER
=
FCK_Tx
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Fi gure 92. Timer/Counter x (x = 0 or 1) in Mode 1
Fi gure 93. Mode 1 Overflow Period Formula
Mode 2 (8-bit Timer with Auto-
Reload) Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads
from the T H 0 registe r (s ee F igure 94). T L0 overflow sets the TF0 flag in the TCON reg-
ist er and re loads T L0 with the co ntents o f TH0 , which i s prese t by the softw are. Whe n
the interrupt request is servi ced, the ha rdware c lears TF0. Th e reload leaves TH 0
unc hanged. The nex t reload value m ay b e ch anged at any tim e by writing it to the T H0
register.
Figure 95 gives the autorelo ad period calculation formula when in timer mode.
Fi gure 94. Timer/Counter x (x = 0 or 1) in Mode 2
Fi gure 95. Mode 2 Autoreload Period Form ula
TRx
TCON reg
TFx
TCO N reg
0
1
GATEx
TMOD reg
Overflow Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx#
Tx
FCK_Tx /6
6
⋅ (65536 – (THx, TLx))
TFxPER
=
FCK_Tx
TRx
TCO N reg
TFx
TCO N reg
0
1
GATEx
TMOD reg
Overflow Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx#
Tx
FCK_Tx /6
TFxPER
=
FCK_Tx
6
⋅ (25 6 – THx)
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Mode 3 (Two 8-bit Timers) M ode 3 configures T imer 0 so that regis ters T L0 and TH0 opera te as 8-bit Timers (see
Figu re 96). This m ode is provided f or applications re quiring an ad ditional 8-bit T imer or
Counter . TL0 uses the Timer 0 cont rol bits C/T0# and GATE 0 in the TMOD register, and
TR0 and TF0 in the TCON register in the normal manner. TH0 is locked into a Timer
function (counting FUART) and takes ov er use of the Ti mer 1 interrupt (TF1) and run con-
trol (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3.
Figure 97 gives the autorelo ad period calculation formulas for b oth TF0 and TF1 flags.
Fi gure 96. Timer/Counter 0 in Mode 3: Two 8-bit Count ers
Fi gure 97. Mode 3 Overflow Period Formula
Timer 1 Ti mer 1 is id ent ical to T imer 0 e xcep t for M ode 3 w hich i s a ho ld-cou nt mod e. The fol-
lowing com men ts help to understand the differences:
• Timer 1 fu nctions as either a Timer or an event Counter in three operating modes.
Figure 90 through Figure 94 show the logi cal configurati on for modes 0, 1, and 2.
Mode 3 of T imer 1 is a hold-c ount mode.
• Timer 1 is c on trolled by the four high-order bits of the TMOD register (see Ta ble 89
on page 153) and bits 2, 3, 6 and 7 of th e TCON register (see Table 88 on page
152). The TMOD register selects the method of Timer gating (GAT E 1), Tim er or
Counter operat ion (C/T1#) and the operating mode (M11 and M01). The TCON
register provides T imer 1 control functions: overflow fl ag ( TF1), run control bit (TR1),
interru pt flag (IE1) and the interrupt type control bit (IT1).
• Timer 1 can serve as the Baud Rate Generat or for the Serial Port. Mode 2 is best
suited for this purpose.
• For normal T i mer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented
by the se lected input . Setting GAT E1 and T R1 allows external pin INT1# to control
Timer o peration.
• T i m er 1 overflow (count roll s over from all 1s to all 0s) sets the TF1 flag and
generates an interrupt request.
TR0
TCON.4
TF0
TCON.5
INT0#
0
1
GATE0
TMOD.3
Overflow Timer 0
Interrupt
Request
C/T0#
TMOD.2
TL0
(8 bits)
TR1
TCON.6
TH0
(8 bits) TF1
TCON.7
Overflow Timer 1
Interrupt
Request
T0
FCK_T0 /6
FCK_T0 /6
TF0PER
=
FCK_T0
6
⋅ (256 – TL0) TF1PER
=
FCK_T0
6
⋅ (256 – TH0)
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• W hen Timer 0 is in mo de 3, it uses Timer 1’s overflow flag (TF1) and run control bit
(TR1). For this situation, use Ti me r 1 only for applications that do not require an
interrupt (such a s a Baud Rate Generator for the Serial Po rt) and switch Timer 1 in
and out of mode 3 to turn it off and on.
• It is important to stop the Timer/Coun ter before changing modes .
Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Ti mer, which is set up as an 8-bi t Timer (TH1 reg-
ist er) with a modu lo-32 pre scal er implemen ted wi th the lowe r 5 bits o f the TL1 regi ster
(see F igure 90). The upper 3 bits of TL 1 register are ignore d. Prescaler ov erflow incre-
ments the TH1 register.
Mode 1 (16-bit Timer) M ode 1 config ures Timer 1 a s a 16-bit T ime r with TH1 and TL 1 regist ers conne cted i n
cascade (s ee Figure 92). The selected input incremen ts the TL1 register.
Mode 2 (8-bit Timer with Auto-
Reload) Mo de 2 co nfigures T ime r 1 as an 8-bi t Timer (TL 1 regist er) with au tomat ic reload f rom
the TH1 register on overflow (see F igure 94). TL1 overflow sets the TF1 flag in the
TCON register and reloads TL1 with the contents of TH1, which is preset by the soft-
ware . The reload leaves TH1 unchanged .
Mode 3 (Halt) Pla cing Timer 1 in mode 3 causes it to halt and hold its count. This can be used t o halt
Timer 1 when the TR1 run control bit is not available i.e. when Time r 0 is in mode 3.
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Registers T imer/Co unter Control Register
Rese t Va lue = 0000 0000b
Table 88. TCON (S:88h)
76543210
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit
Number Bit
Mnemonic Description
7TF1
Timer 1 Overfl ow flag
Cleared by the hardware when processor vectors interrupt routine.
Set by the hardware when Timer 1 register overflows.
6TR1
Timer 1 Run Control bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
5TF0
Timer 0 Overfl ow flag
Cl ea red b y th e ha rdwa r e whe n pro ces so r vecto r s in ter rup t rou t in e or by sof t wa re
when the interrupt is disabled
Set by the hardware when Timer 0 register overflows.
4TR0
Timer 0 Run Control bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
3IE1
Interrupt 1 Edge flag
Cleared by the hardware when interrupt is processed if edge-t riggered (se e IT1).
Set by the hardware when external interrupt is detected on the INT1# pin.
2IT1
Interrupt 1 Type Control bit
Clear to select low level active (level triggered) for external interrupt 1 (IN T1#).
Set to select falling edge active (edge triggered) for external interrupt 1.
1IE0
Interrupt 0 Edge flag
Cleared by the hardware when interrupt is processed if edge-t riggered (se e IT0).
Set by the hardware when external interrupt is detected on INT0# pin.
0IT0
Interrupt 0 Type Control bit
Clear to select low level active (level triggered) for external interrupt 0 (IN T0#).
Set to select falling edge active (edge triggered) for external interrupt 0.
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Reset Value = 0000 0000b
Tab le 89. Time r/Counter Mode Control Register - T M OD (S:89h)
76543210
GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
Bit Number Bit Mnemonic Descri ption
7GATE1
Timer 1 Gati ng Contr o l bit
Clear to enable Timer 1 whenever TR1 b it is set.
Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.
6C/T1#
Timer 1 Counter/Timer Select bit
Clear for Timer operation: Tim er 1 counts the divided -down system clock.
Set for Counter operation: Timer 1 counts ne gative transitions on external pin T 1.
5M11Timer 1 Mode Select bits
M11 M01 Operating mode
0 0 Mode 0:8-bit Timer/Coun ter (TH1) w ith 5-bit prescale r (TL1).
0 1 Mode 1:16-bit Timer/Counter.
1 0 Mode 2:8-bit auto-reload Timer/Counter (TL1). Reloaded from TH1 at overflow.
1 1 Mode 3:Timer 1 halted. Retains co unt.
4M01
3GATE0
Timer 0 Gati ng Contr o l bit
Clear to enable Timer 0 whenever TR0 b it is set.
Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.
2C/T0#
Timer 0 Counter/Timer Select bit
Clear for Timer operation: Tim er 0 counts the divided -down system clock.
Set for Counter operation: Timer 0 counts ne gative transitions on external pin T 0.
1M10Timer 0 Mode Select bit
M10 M00 Operating mode
0 0 Mode 0:8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).
0 1 Mo de 1:16 -bit Timer/Counter.
1 0 Mo de 2:8-bit auto-reload Timer /Counter (T L0). Reloaded from TH0 at overflow.
1 1 Mo de 3:TL0 is an 8- bit T imer/Counter.
TH 0 is an 8-bit Timer usi ng Timer 1’s TR0 and TF0 bits.
0M00
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Rese t Va lue = 0000 0000b
Rese t Va lue = 0000 0000b
Rese t Va lue = 0000 0000b
Rese t Va lue = 0000 0000b
Table 90. Timer 0 High Byte Register - TH0 (S:8Ch)
76543210
Bit Number Bit
Mnemonic Description
7: 0 Hig h B y te of Timer 0
Table 91. Timer 0 Low Byte Register - TL0 (S:8Ah)
76543210
Bit
Number Bit
Mnemonic Description
7:0 Low Byte of Timer 0
Table 92. Timer 1 High Byte Register - TH1 (S:8Dh)
76543210
Bit Number Bit
Mnemonic Description
7: 0 Hig h B y te of Timer 1
Table 93. Timer 1 Low Byte Regist er - TL1 (S:8Bh)
76543210
Bit Number Bit
Mnemonic Description
7:0 Low Byte of Time r 1
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Keyboard Interface Only for AT8xC5122.
Introduction The AT 8xC5122/ 23 implements a keybo ard in terface al lowin g the c on nec tion of a 8 x n
matr ix keyboard. I t is based o n 8 inputs wi th pr ogrammabl e interrupt capa bility on both
high or low level. These input s are av ailable as alternate function of P5 and allow to exit
from idle and power-down modes.
Description The keyboard interfa ces wit h the C51 c ore thro ugh 3 s pecia l funct ion regis ters: KB LS,
the Keyboard Level Selection register (Table 96 on page 158), KBE, The Keyboard
interrupt Enab le register (Table 95 on pag e 157 ), and KBF, th e Keyboa rd Flag reg ister
(Table ).
Interrupt The keyboard inputs are considered as 8 independent interrupt sources sharing the
same in terrupt vector. An interrupt enable bit ( KBD in IE1) allows global enabl e or dis-
able of the ke yboa rd interru pt (see F igure 9 8). As detaile d in Figu re 99 eac h keyboa rd
input has the capability to detec t a programmable level according to KBLS.x bit value.
Leve l detection is then reported in interrupt flags KBF.x that can be masked by software
using KBE.x bi ts.
This struct ure allows keyboard arrangement from 1 by n t o 8 by n matrix and allows
usag e of P5 inputs for other purpose.
The KBF.x flags are s et by hardware when an active level is on input P5.x . They are
autom atically rese t after any r ead acce ss on KB F. If the content o f KBF must be ana-
lyzed , the first read instruction must tran sfer K BF contend to another lo ca tion. The KBF
register cannot be written by soft ware.
Fi gure 98. Keyboard Interface Block Diagram
Fi gure 99. Keyboard Input Circuitry
P5.0
Keyboard Interfac
e
Inter rupt Request
EKB
IEN1.0
Input Circuitr y
P5.1 I nput Cir cuitr y
P5.2 I nput Cir cuitr y
P5.3 I nput Cir cuitr y
P5.4 I nput Cir cuitr y
P5.5 I nput Cir cuitr y
P5.6 I nput Cir cuitr y
P5.7 I nput Cir cuitr y
KBDIT
P
5.x
KBE.x
KBF.x
KBLS.x
0
1
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Power Reduct ion Mode P5 inputs allow exit f rom idle and power-down modes as detailed in Section "Power-
Down Mode".
Registers
Rese t Va lue = 0000 0000b
Tab le 94. Keyboard Fla g Register - K B F (9Eh)
76543210
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Bit
Number Bit
Mnemonic Description
7 KBF7
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generate s a
Keyboard interrupt request if the KBE.7 bit in KBE register is set.
Cleared by har dware after the read of the KBF r egister.
6 KBF6
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generate s a
Keyboard interrupt request if the KBE.6 bit in KBE register is set.
Cleared by har dware after the read of the KBF r egister.
5 KBF5
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generate s a
Keyboard interrupt request if the KBE.5 bit in KBE register is set.
Cleared by har dware after the read of the KBF r egister.
4 KBF4
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generate s a
Keyboard interrupt request if the KBE.4 bit in KBE register is set.
Cleared by har dware after the read of the KBF r egister.
3 KBF3
Keyboard line 3 flag
Set by hardware when the Port line 3 detects a programmed level. It generate s a
Keyboard interrupt request if the KBE.3 bit in KBE register is set.
Cleared by har dware after the read of the KBF r egister.
2 KBF2
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generate s a
Keyboard interrupt request if the KBE.2 bit in KBE register is set.
Cleared by har dware after the read of the KBF r egister.
1 KBF1
Keyboard line 1 flag
Set by hardware when the Port line 1 detects a programmed level. It generate s a
Keyboard interrupt request if the KBE.1 bit in KBE register is set.
Cleared by har dware after the read of the KBF r egister.
0 KBF0
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generate s a
Keyboard interrupt request if the KBE.0 bit in KBE register is set.
Cleared by har dware after the read of the KBF r egister.
157
AT8xC5122/23
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Rese t Va lue = 0000 0000b
Table 95. Keyb oard Input En able Register - KBE (9Dh)
76543210
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
Bit
Number Bit
Mnemonic Description
7 KBE7 Ke yb oard line 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.7 bit in KBF register to generate an interrupt request.
6 KBE6 Ke yb oard line 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.6 bit in KBF register to generate an interrupt request.
5 KBE5 Ke yb oard line 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.5 bit in KBF register to generate an interrupt request.
4 KBE4 Ke yb oard line 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.4 bit in KBF register to generate an interrupt request.
3 KBE3 Ke yb oard line 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.3 bit in KBF register to generate an interrupt request.
2 KBE2 Ke yb oard line 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.2 bit in KBF register to generate an interrupt request.
1 KBE1 Ke yb oard line 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.1 bit in KBF register to generate an interrupt request.
0 KBE0 Ke yb oard line 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.0 bit in KBF register to generate an interrupt request.
158
AT8xC5122/23
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Rese t Va lue = 0000 0000b
Table 96. Keyboard Level Selector Register - KBLS (9Ch)
76543210
KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
Bit
Number Bit
Mnemonic Description
7 KBLS7 Keyboard line 7 Level Selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
6 KBLS6 Keyboard line 6 Level Selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
5 KBLS5 Keyboard line 5 Level Selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
4 KBLS4 Keyboard line 4 Level Selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
3 KBLS3 Keyboard line 3 Level Selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
2 KBLS2 Keyboard line 2 Level Selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
1 KBLS1 Keyboard line 1 Level Selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
0 KBLS0 Keyboard line 0 Level Selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
159
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Interrupt System
Introduction The AT8xC5122/23 impl ements an interrupt controller with 15 inputs but only 9 are used
for :– two external interrupts (I NT0 and INT1)
– two t imer interrupts (timers 0 , 1),
– the UART interface
– the SPI interface
– the keyboard interface
– the USB interface
– the Smar t C a r d In ter face.
Interrupt System
Description Each of the interrupt sources can be individ ually enabl ed or disabled by setting or clear-
ing a bi t in t he Interrupt E nable regis ters (Table 98 on pag e 162 and Ta ble 99 on page
163). These registers also contain a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of f our pri ority lev-
els by setting or clearing a bit in the Interrupt Priority Low registers (Table 101 on pa ge
164 and Table 103 on page 166) and in the Interrupt Priority High regist er (Table 102 on
pag e 16 5 and T able 105 on pag e 168) show s the b it va lues an d p riority l evels ass oci-
ated with each combin ation.
A low -pr iority interrupt c an be interrupted by a high priority interrupt, but not by anot her
low-p riority inte rrupt. A high-pr iority interru pt can’t be i nterrup te d by any ot her inte rrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
reques t of higher priority level is serviced. If interrupt re quests of the same priority level
ar e received simul taneous ly, an in terna l polling sequenc e determ ines wh ich requ est is
serviced first. Thus within each priority level there is a second priority structure deter-
mined by the polling sequence.
Table 97. Priority Level Bit Values
IPH.x IPL.x Interrupt Level Priority
0 0 0 (Lowest)
011
102
113 (Highest)
160
AT8xC5122/23
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Figure 100. Interrupt Control System
IE0
SPI
SMART CARD
INT1
CPRES
RXD
RXEN
0
1IE1
1
0
0
1PRESIT
ISEL.0
ISEL.4
RXIT
OEEN
ISEL.2
OELEV
ISEL.3 IT1
TCON.2
TCON.3
PRESEN
ISEL.1
CPLEV
ISEL.7
ISEL.5
0
1
IT0
TCON.0
TF0
TF1
RI
TI
ET1
IEN0.3
EUSB
IEN1.6
ES
IEN0.4
EX0
IEN0.0
00
01
10
11
EA
IEN0.7
ET0
IEN0.1
EX1
IEN0.2
EKB (1)
IEN1.0
ESPI (1)
IEN1.2
IPH/L
Interrupt Enable Lowest Priority
Priority Enable
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
ESCI
IEN1.3
00
01
10
11
Highest Priority
Interrupts
Interrupts
TCON.1
INT0#
RXD
TXD
D+
D-
CIO
CCLK
MOSI
SCK
MISO
TCON.5
TCON.7
SCON.0
SCON.1
P5.x 0
1KBFx
KBExKBLSx
SERIAL
INTERFACE
CONTROLLER
CONTROLLER
USB
CONTROLLER
CONTROLLER
INTERFACE
note (1) : Not applicable to AT83C5123
(1)
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INT1 Inte rru pt Vecto r The INT1 interrupt is multi plexed with the following three inputs:
• INT1 : Standard 8051 interrupt input
• RXD : Received data on UART
• CPRES: Insert ion or remove of the main card
The setting conf igurations for each input is detailed below.
INT1 Input This interrupt input is active under the following condition s :
• It must be enabled by OEEN Bit (ISEL Register)
• It can be active on a level or fal ling edge following IT1 Bit (TCON Register) status
• If level triggering selection is set, t he active level 0 or 1 can be selected with OELEV
Bit (IS E L Register)
The Bit IE1 (TCON Reg ister) is set by hardwa re when external interrupt detected. It is
cleared when interrupt is processed.
RXD Input A seco nd vec tor in terrupt i nput is the reception of a cha racter. UA RT Rx in put can gen-
erate an interrupt if enabled with Bit RX EN (ISEL.0). The global enable bits EX1 and EA
must also be set.
The n, the Bi t RXI T (ISEL R egister) i s set by ha rdwa re when a low le vel is de te cted o n
P3.0/RXD input.
CPRES Input The third input is the detect ion of a level cha nge on CP RE S input (P1.2). Thi s input can
generate an interrupt if enabled with PR ESEN (ISEL.1) , EX1 (IE0.2) and EA (IE0.7)
Bits.
This detection is done according to the level selected with Bit CPLEV (ISEL.7).
Then the Bit PRESIT (ISEL.5) is set by hardware when the triggering conditions are
met. This Bit must be cleared by software.
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Registers
Rese t Value = 0000 0000b (Bit addressable)
Table 98. Interrupt Enable Register 0 - IEN0 (A8h)
76543210
EA - - ES ET1 EX1 ET0 EX0
Bit
Number Bit
Mnemonic Description
7EA
Enable All interrupt bit
Cleared to disable all int errupts.
S et to en able all int err u pts .
6 - 5 - Reserved
The value read from this bit is indeterminate . Do not chang e these bits.
4ES
Serial port Enable bit
Cleared to disable serial port interrupt.
S et to en able seri al po r t int er ru pt.
3ET1
Timer 1 ov e rflow in terrupt E nable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2 EX1 External interrupt 1 Enable bit
Cleared to disable external interr upt 1.
S et to enab le exte rna l in terr up t 1.
1ET0
Timer 0 ov e rflow in terrupt E nable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0 EX0 External interrupt 0 Enable bit
Cleared to disable external interr upt 0.
S et to enab le exte rna l in terr up t 0.
163
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Rese t Value = X0XX 00X0b (Bit addressable )
Table 99. Interrupt Enable Register 1 - IEN1 (B1h) for AT8xC5122
76543210
- EUSB - - ESCI ESPI - EKB
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is inde termi nate. Do not change th is bit.
6EUSB
USB Interrupt En abl e bit
Cleared to disable USB interrupt .
Set to enable USB interrupt.
5 - 4 - Reserved
The value read from this bit is inde termi nate. Do not change th ese bits.
3 ESCI SCI interrupt Enable bit
Cleared to disable SCIinterrupt .
Set to enable SCI interrupt.
2 ESPI SPI interrupt Enable bit
Cleared to disable SPI interrupt .
Set to enable SPI interrupt.
1-
Reserved
The value read from this bit is inde termi nate. Do not change th is bit.
0 EKB Keyboard interrupt Enable bit
Cleared to disable keyboard interrupt .
Set to enable keyboard interrupt.
164
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Rese t Value = X0XX 0XXXb (Bit addressabl e)
Rese t Value = X000 0000b (Bit addressabl e)
Table 100. Interrupt Ena ble Register 1 - I E N1 (B1h) for AT8 3C5123
76543210
- EUSB - - ESCI -
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is inde termi nate. Do not change th is bit.
6EUSB
USB Interrupt En abl e bit
Cleared to disable USB interrupt .
Set to enable USB interrupt.
5 - 4 - Reserved
The value read from this bit is inde termi nate. Do not change th ese bits.
3 ESCI SCI interrupt Enable bit
Cleared to disable SCIinterrupt .
Set to enable SCI interrupt.
2Reserved
The value read from this bit is inde termi nate. Do not change th is bit.
1-
Reserved
The value read from this bit is inde termi nate. Do not change th is bit.
0Reserved
The value read from this bit is inde termi nate. Do not change th is bit.
Table 101. Interrupt Priority Low Register 0 - IPL0 (B8h )
76543210
- - - PSL PT1L PX1L PT0L PX0L
Bit
Number Bit
Mnemonic Description
7 - 5 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
4 PSL Seri al port Prio r ity bit
Refer to PSH for pri o rity level.
3PT1L
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority le vel .
2 PX1L Ex ternal interrupt 1 Priority bit
Refer to PX1H for priority level.
1PT0L
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority le vel .
0 PX0L Ex ternal interrupt 0 Priority bit
Refer to PX0H for priority level.
165
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Rese t Value = X000 0000b (Not bit addressable)
Table 102. Interrupt Priority High Register 0 - IPH0 (B7h)
76543210
- - - PSH PT1H PX1H PT0H PX0H
Bit
Number Bit
Mnemonic Description
7 - 5 - Reserved
The value read from this bit is indeterminate. Do not change these bits .
4 PSH
Serial port Priority High bit
PSHPSL Priori ty Level
00 Lowest
01
10
1 1 Highest
3PT1H
Timer 1 overflow interrupt Priority High bit
PT1H PT1L Priority Leve l
00 Lowest
01
10
1 1 Highest
2 PX1H
External interrupt 1 Priority High bit
PX1H PX1L Priority Leve l
00 Lowest
01
10
1 1 Highest
1PT0H
Timer 0 overflow interrupt Priority High bit
PT0H PT0L Pri ority Level
00 Lowest
01
10
1 1 Highest
0 PX0H
External interrupt 0 Priority High bit
PX0H PX0L Priority Level
00 Lowest
01
10
1 1 Highest
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Rese t Value = X00X 00X0b (Bit addressab le)
Table 103. Interrupt Priority Low Register 1 - I P L1 (B2h) for AT8 xC5122
76543210
- PUSBL - - PSCIL PSPIL - PKBDL
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
6 PUSBL USB Interrupt Priority bit
Refer to PUSBH for prio rity level.
5 - 4 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
3PSCIL
SCI Inte rrupt Pr io rity bit
Refer to PSPIH for priority level.
2PSPIL
SPI Interrupt Priority bit
Refer to PSPIH for priority level.
1-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
0 PKBL Key board Interrupt Priority bit
Refer to PKBDH for priority level.
167
AT8xC5122/23
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Rese t Value = X0XX 0XXXb (Bit addressabl e)
Table 104. Interrupt Priority Low Register 1 - IPL1 (B2h ) for AT83C5123
76543210
- PUSBL - - PSCIL
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
6 PUSBL USB Interrupt Priority bit
Refer to PUSBH for prio rity level.
5 - 4 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
3PSCIL
SCI Inte rrupt Pr io rity bit
Refer to PSPIH for priority level.
2Reserved
The value read from this bit is indeterminate. Do not change this bit.
1Reserved
The value read from this bit is indeterminate. Do not change this bit.
0Reserved
The value read from this bit is indeterminate. Do not change this bit.
168
AT8xC5122/23
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Reset Value = XXXX X000b (Not bit addressable)
Table 105. Interrupt Priority High Register 1 - IPH1 (B3h) for AT8xC5122
76543210
- PUSBH - - PSCIH -
Bit
Number Bit
Mnemonic Description
7-
Reserved
Th e valu e r ea d fr om thi s bi t is ind eterm in ate. D o no t cha ng e th i s bit.
6PUSBH
USB Interrupt Priotity High bit
PUSBH PUSBL Priority Level
00 Lowest
01
10
1 1 Highest
5-4 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
3PSCIH
SCI Interrupt Priority Hi gh bit
PSCIH PSCIL Priority Level
00 Lowest
01
10
1 1 Highest
2PSPIH
SPI Interrupt Priority High bit
PSPIH PSPIL Priority Level
00 Lowest
01
10
1 1 Highest
1-
Reserved
Th e valu e r ea d fr om thi s bi t is ind eterm in ate. D o no t cha ng e th i s bit.
0 PKBH
Keyboard Inte rrupt Priority High bit
PKBDH PKBDL Priority Level
00 Lowest
01
10
1 1 Highest
169
AT8xC5122/23
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Rese t Value = X0XX 0XXXb (Not bit addressable )
Table 106. Interrupt Priority High Register 1 - IPH1 (B3h) for AT83C5123
76543210
- PUSBH - - PSCIH - - -
Bit
Number Bit
Mnemonic Description
7-
Reserved
Th e valu e r ea d fr om thi s bi t is ind eterm in ate. D o no t cha ng e th i s bit.
6PUSBH
USB Interrupt Priotity High bit
PUSBH PUSBL Priority Level
00 Lowest
01
10
1 1 Highest
5-4 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
3PSCIH
SCI Interrupt Priority Hi gh bit
PSCIH PSCIL Priority Level
00 Lowest
01
10
1 1 Highest
2Reserved
The value read from this bit is indeterminate. Do not change these bits.
1-
Reserved
Th e valu e r ea d fr om thi s bi t is ind eterm in ate. D o no t cha ng e th i s bit.
0Reserved
The value read from this bit is indeterminate. Do not change these bits.
170
AT8xC5122/23
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Rese t Value = 0000 0000b
Table 107. Interrupt Ena ble Register - ISEL (S:A 1h)
76543210
CPLEV - PRESIT RXIT OELEV OEEN PRESEN RXEN
Bit
Number Bit
Mnemonic Description
7CPLEV
Card presence detection level
This bit indicates which CPRES level will bring about an interrupt
Set this bit to indicate that Card Presence IT will appear if CPRES is at high
level.
Clear this bit to indicate that Card Presence IT will appear if CPRES is at low
level.
6-
Reserved
Th e valu e r ea d fr om thi s bi t is ind eterm in ate. D o no t cha ng e th i s bit.
5PRESIT Card presence detection interrupt flag
Set by hardware
Must be cleared by software
4RXIT Re ce iv ed da ta int e rrupt flag
Set by hardware
Must be cleared by software
3OELEV INT1 signal active level
Set this bit to indicate that high level is active.
Clear this bit to indicate that low level is active.
2OEEN INT 1 Inte r rupt Disable bit
Clear to disable INT1 interrupt
Set to enable INT1 interrupt
1PRESEN Card presence detection Interrupt Enable bit
Clear to disabl e the card presence detection interrupt c oming from SCIB.
Set to enable the card presence detection interrupt coming from SCIB.
0RXEN
Re ceiv ed da ta Interr upt Ena ble bit
Clear to disable the RxD interr upt.
Set to enabl e t he RxD interrupt (a minima l bit width of 100 μs is required to
wake up from power-down) .
171
AT8xC5122/23
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Interrup t Sources and
Vectors
Note: 1. Only fot AT8xC5122
Table 108. Interrupt Vectors
Interrupt Sour ce Polling Priority
at Sam e Level Vector
Address
Reset 0
(Highest Priority) C:0000h
INT0 1 C:0003h
Timer 0 2 C:000Bh
INT1 3 C:0013h
Timer 1 4 C:001Bh
UART 6 C:0023h
Reserved 7C:002Bh
Reserved 5 C:0033h
Keyboard Contro ller (1) 8C:003Bh
Reserved 9 C:0043h
SPI Co ntroller (1 ) 10 C:004Bh
Smart Card Controller 11 C:0053h
Reserved 12 C:005Bh
Reserved 13 C:0063h
USB Controller 14 C:006Bh
Reserved 15
(Lowest Priorit y) C:0073h
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AT8xC5122/23
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Microcontroller Reset
Introduction The internal reset is used to start up (cold reset) o r to re-start (warm reset) the m icro-
controller activity. When the re se t is applied (active state), all internal registers are
initialized so that the microcontroller s tarts fr om a known and clean state for the program
always runs as expected.
The reset is released (inactive stat e) when the following conditions are internally met :
– The power supply has reatched a minimum level which garantees that the
microcontroller works properly
– The on-c hip oscillato r has reac hed a min imum oscillation lev el w hich
ensures a good noise to signal ratio and a correct internal duty cycle
– the active state duration is at least two machine cycles.
If one of the above conditions is not met the microcontroller is not correctly reset and
migh t not work properly.
The internal reset comes from four different sources :
– Res et pin
– Power On Reset (POR)
– Power Fail Detector (PFD)
– Hardware Watch-Dog Timer (W DT)
Fi gure 101. Re se t bock diagram
Watch Do g
RST
Internal Reset
Timer
Microcontroller
Vcc 3.3V Internal
Digital Regulator
C51
Core
VCore
POR PFD
173
AT8xC5122/23
4202E–SCR–06/06
Power On Reset (POR) T he role of the PO R is to moni tor the power suppl y rise of the microco ntroller core and
release the internal reset only when t he internal vol ta ge excee ds the VPFDP th reshold
from which the microcontro ller core is stable (see Figure 102). This feature replaces the
external reset funct ion and t herefore av oid th e use of ext ernal compo nent s on t he res et
pin.
Power Fail Detector
(PFD) The role of the P FD is to mon itor the po wer supply falls during a ste ady state condition
in order to suspend the microcontroller and peripherals activity as soon as the power
supply drops below the VPFDM threshold from which the microcontroller’s core might
bec om e instab le (see F igure 10 2). The PDF sus pends t he m icroco ntrol ler’s activ ity by
holding t he microcont roller under a reset stat e to av oid an unpredictable behaviour.
A filter prevents the system from res eting w hen glitches lower than 50 ns duration a re
carried on Vcore. See Figu re 102 and F igure 103 on page 174.
174
AT8xC5122/23
4202E–SCR–06/06
Fi gure 102. S tatic behaviour of POR and PFD
Fi gure 103. Dynamic behaviour of POR a nd PFD
VCore
t
Internal
VPFDP
VPFDM
1
0
POR
POR
PFD
Reset
VCore
t
Internal
VPFDP
VPFDM
1
0
POR
POR
PFD
Reset
t<50ns t>50ns
175
AT8xC5122/23
4202E–SCR–06/06
Reset pin As explained in the POR section there is no need to use the reset pin as the internal
reset function at power up is ensured by the POR. Anyway, if some applications
requires a long reset, a reset controlled by the user or a reset controlled by external
supe rviser device, the use of the reset pin is necessary.
Long Reset As the pad integrat es an int ernal pull-up of 10K, only an external capacitor of at least 10
µF is requir ed to have an impact on the reset duration.
Fi gure 104. Long Reset
Reset Con trolle d by the User The ex ternal capacitor is not needed if no long reset is required.
Fi gure 105. Re se t Co ntrolled by the User
RST
Vcc
10 K
Internal Reset
Microcontrolleur
10 µF
RST
Vcc
10 K
Internal Reset
Microcontrolleur
176
AT8xC5122/23
4202E–SCR–06/06
Reset Con trol led by an
Externa l Su pe rvis er Device As t he reset pin can be forced i n output by the Watch-Dog t imer (WDT) or the POR/PFD
features, there can be a conf lict between the e xternal superv iser device and t he micro-
con troller’s reset pin when in on e side t he external supervis er is pulling the reset pin to
VCC and in another side the WDT or POR/PFD features tries to force the reset pin to
ground. Therefore, it recommended to insert a series res istor of 1.8K + /-10% or a dio de
(1N4148 for instance) betwee n th e external superviser device and the re se t pi n as
detailed in the following figures.
Fi gure 106. Use of an External Serial Resisto r
Fi gure 107. Use of an External Diode
RST
Vcc
10 K
Microcontrolleur
1.8 K
Superviser
device
To other on-board
circuitry
Power Fa il
Detector
Watchdog
Timer
Powe r On
Reset
RST
Vcc
10 K
Microcontrolleur
Superviser
device
To other on-board
circuitry
Power Fail
Detector
Watchdog
Timer
Power On
Reset
1N4148
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Watchdog Timer The AT8xC5122/23 microcontrollers contain a powerfull programmable hardware
Wat chdog Timer (WDT) that automatically resets the chip if its software fails to reset the
WDT before t he selected time interval has elaps ed. It permits large timeout ranking from
4ms to 524ms @ FCK_WD = 24 MHz / X2
Th is WD T cons ist of a 14-b it coun ter plus a 7 -bit pro gram m able coun ter , a Wat chdo g
Timer reset register (WDTRST) and a Watchdog Timer programmation (WDTPRG) reg-
ister. When exiting the reset, the WDT is, by default, disabled. To activate the WDT, the
user has to write the s equence 1EH and E1H into WDRST register. When the Watchdog
Timer is enabled, it will increment every machine cycle while the oscillat or is running
and t here is no way t o disable the WDT except through reset (either hardwa re reset or
WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at
the RST pin. The RESET pulse duration is 96xTOSC, where T OSC=1/FOSC. To make the
best use of t he WDT, it should be s erviced in those sect ions of code that will periodically
be executed within the time required to prevent a WDT reset.
The WDT is controlled by two registers (WDTRST and WDTPRG).
Fi gure 108. Watchdog Timer
RESET Decoder
Control
WDTRST
WR
Enable
14-bit COUNTER 7 - bit COUNTER
Outputs
FCK_WD
RESET
- - -
- - 2 1 0
WDTPRG
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Reset Value = XXXX X000b
The three lower bits (S0, S1, S2) located into WDTPRG register enables to program the
W DT duration.
To compute WD Timeout, the following formula must be applied:
T ime Ou t = 6 * (214 * 2 Svalue - 1 ) / FCK_WD
Note: Svalue re presents the deci m al value of (S2 S1 S0)
Table 109. Watchdog Timer Out Register - WDTPRG (0A7h)
76543210
-----S2S1S0
Bit
Number Bit
Mnemonic Description
7 - 3 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
2 S2 WDT Time-out select bit 2
1 S1 WDT Time-out select bit 1
0 S0 WDT Time-out select bit 0
Table 110. Mach ine Cycl e Count
S2 S1 S0 Machine Cycle Cou nt
000 2
14 - 1
001 2
15 - 1
010 2
16 - 1
011 2
17 - 1
100 2
18 - 1
101 2
19 - 1
110 2
20 - 1
111 2
21 - 1
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Table 111. Timeout value for FCK_WD = 24 M Hz / X2
Reset Value = XXXX XXXXb
The WDTRST register is used to reset / enable the WDT by writing 1EH then E1H in
sequence.
S2 S1 S0 Timeout for FCK_WD= 24 MHz / X2
000 4.10 ms
001 8.19 ms
0 1 0 16.38 ms
0 1 1 32.77 ms
1 0 0 65.54 ms
1 0 1 131.07 ms
1 1 0 262.14 ms
1 1 1 524.29 ms
Table 112. Watchdog Timer Enable register (Write Onl y) - W DTRST (A6h)
76543210
--------
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Power Management
Before act ivating the Id le Mode or P ower Do wn Mo de, the C PU clock must be sw itched
to o n- c h ip o s c illat o r so u rce if the PL L is u sed to fed t he CPU c loc k .
Idle Mode An instruction that sets PCON.0 indicates that it is the last instruction to be executed
before goin g into the Idle mode. In the Id le mode, the internal clock signal is gate d off to
the CP U, but not to the interrupt, Timer, and Serial Port functions. The CPU status is
preserved in its entiret y: the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold
the logical states they had at the time Idle was activated. ALE and PSEN h old at logic
high level.
The re are tw o ways to term inate t he Idle mode. A ctiva tion of any enabl ed interru pt will
cau se PCON.0 to be cleared by hardware, te rminating the Idle mode . The interrupt will
be s erviced , and fol lowin g RETI th e nex t ins tructio n to be ex ecut ed will be the one fo l-
lowing the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured dur-
ing norm al operation or during an Idle. For example, an instruction that activates Idle
ca n also set on e or both flag bits. When Id le is terminated by an interru pt, the interrupt
service routine can examin e the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycl es ( 24 osci ll ato r p e riod s) to co mplete the re se t.
Power Down Mode To sav e maximum power, a power-d own mode can be inv oked by softw are (see Tabl e
13, PCON registe r).
WARNING: To minimize power consumption, all peripherals and I/Os with static current
co nsum pt ion mu st b e se t in the pr oper state . I/O s pro gra mmed wit h lo w spee d out put
configuration (KB_OUT) must be switch to push-pull or Standard C51 configuration
before entering powe r-down. The CVCC generator mu st also b e switch off.
In power -do wn mo de, t he osc illato r is s topped an d the in struc tion that invoke d powe r-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from power-
down . To prope rly te rminate p ow er-down , the r eset o r exte rna l inter rupt sh ould not be
executed before VCC is restored to its normal operating level and must be held active
long enough for the os c illat or to res ta rt and stabi lize.
Onl y external interrupts INT0 , INT1, Keyboard , Card insertion/re moval and USB I nter-
rupts are useful to exit from power-down. For that, interrupt must be enabled and
configured as level or edge sensitive interrupt input. When Keyboard Interrupt occurs
after a powe r-down mode, 102 4 clocks are necessary to exit to power-down mode a nd
enter in operating mode.
Holding the p in low restarts the os cillator b ut bringing the pi n high com pl etes the exit as
detailed in Fig ure 109. When both interrupts a re enable d, the oscil lator restarts as soon
as one of the two inputs is held low and power-down exit wi l l be completed when the fir st
inp ut is rel ease d. In th is cas e, t he high er prio rity i nte rrupt s erv ice ro uti ne i s ex ecut ed.
O nce the inter rupt i s servic ed, the next ins tr uctio n to be ex ecu ted aft er RETI will be the
one following the instruction that put AT8xC5122/23 into power-down mode.
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Fi gure 109. Power-down Exit Wavef orm
Exit from power-down by reset redefines all the SFRs, exit from power -down by external
interrupt does no affect the SFRs.
Exit from power-down by either reset or external interrupt does not affec t the internal
RAM content.
Note: If idle mode is activated with power-down mode (IDL and PD bits set) , the exit sequence
is unchanged, when executi on is vectored to inter rupt, PD and IDL bits are cleared and
idle mode i s not ent ered.
Table shows the state of ports durin g idle and power-down modes.
Note: 1. Port 0 can force a 0 level. A "one" wil l leave port fl oating.
Re duced EMI Mode The ALE signal is used to demult iplex address and data buses on port 0 when used with
external program or data mem ory. Nevertheless, during internal code execution, ALE
sign al is s till g enerate d. In o rder to red uce EM I, ALE sign al can be d isabl ed by s etting
AO bit.
The A O bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no
longer output but remains active during MOVX and MOVC instructions and external
fetches . During ALE disabling, ALE pin is weakly pulle d high.
INT1
INT0
XTAL1
Power-down ph ase Oscillator restart phase Active phaseActive phase
Table S ta te of Ports
Mode P rogra m Mem ory ALE P SEN P0 P1 P2 P3 P4 P 5
Idle In te rna l 1 1 Por t Data(1) Port Data Port Data Port Data Port Data Port Data
Idle External 1 1 Floating Port Data Address Port Data Po rt Data Port Data
Power-down Internal 0 0 Port Dat* Port Data Port Data Port Data Port Data Port Data
Power-down External 0 0 Floating Port Data Port Data Port Data Port Data Port Data
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USB Interface
Suspend T he S uspend stat e can be d etect ed by t he US B co ntroller if all the cloc ks are e nable d
and if the USB controller is enabled. The bit SPINT is set by hardware when an idle
state is detected for more t han 3 ms. This tr iggers a USB interrupt if enabled.
In order to reduce current consumption, the firmware can put t he USB PAD in idle mode,
stop the clocks a nd p ut the C51 in Idle or Power-down m ode. The Resume detection is
st ill ac tive.
The USB PAD is put in idle mode when the firm ware clear the SPINT bit. In order to
avoid a new suspend detection 3ms later, the firmware has to disable the USB clock
input using the SUSPCLK bit in the USBCON Register. The USB PAD autom atically
exits of idle mode when a wake-up event is detected.
The stop of the 48 MHz clock from the PLL should be done in the following order:
1. Disable of the 48 MHz clock input of the USB controller by s etting to 1 the SUS-
PCLK bit in the USBCON register.
2. If CPU clock is fed from PLL, the on-chip oscillator must be selected to f ed the
CPU clock.
3. Disable the PLL by clearing the PLLEN bit in the PLLCON register.
Resume When the US B cont roller is in Sus pend s tate, t he Res ume detec tion i s act ive even if all
the clocks are disabled and if the C51 is in Idle or Power-down mo de. The WUPC PU bit
is set by hardw are when a non-idle state occurs on the USB bus. Th is t riggers an inter-
rupt if en abled. This interrupt wakes up the CPU f rom its Idle or Power-dow n state an d
the interrupt function is t hen executed. The firmware will first enable the 48 MHz gener-
ation and then reset to 0 the SUSPCLK bit in the USBCO N register if needed.
The firmware has to clear the SPINT bit in the USBINT register before any other USB
operation in order to wake up the USB controller from its Suspend mo de.
The USB cont roller is then re-activated.
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Fi gure 110. Example of a Suspend/ Resume Management
Smart Card Interface
Entering in Power-down Mode In ord er to reduce the p ower consu mption, a pow er-down or idle mode can be invoked
by softwa re (see Table 13 , PCON register). Before activating the se mode s the applica-
tion will need to:
Power-off the Smart Card Interface by applying the following sequence:
• Set CRST pin at low level by clearing the bit CARDRST in SCCON register.
• Set CCLK pin at low level by cl earing the bit CLK then the CARDCLK in SCCON
register.
• Set CIO pin at low level by cl earing the bit UART in SCICR register then the bit
CARDIO in SCCON register.
• Power the Smart Interface of f by clearing t he CARDVCC bit in SCCON register . Thi s
instruction enables to switch DC/DC converter off.
CPRES input:
• Set the bit PRSEN in ISEL register
• Set the bit EX1 in IE0 register
• Set the bit EA in th e IE0 register
• Invert the bit CPLEV in ISEL regist er (INT1 interrupt vector)
• Clear the bit PR ESIT in the ISEL register
Exiting from P ower-down
Mode The microcont roller will exit from Pow er-down or Idle m odes u pon a reset or INT 1 inter -
rupt which is a multiplexing of the interruptions generated by the CPRES p in (Card
detection), RxD flag (UART recepti on) and INT1 pin.
USB Controller Init
D
etection of a SUSPEND State SPINT
Set SUSPCLK
Disable PLL
microcontroller in power-down
Detection of a RESUME State WUPCPU
Enable PLL
C lear SUSPCLK
Clea r WUPCPU bit
Clear SPINT
Note :
WUPCPU bit must be
Cleared before enabling
the PLL
Put the USB pads
in power down mod
e
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Keyboard Interface T he keyboard interface appl ies only to AT8xC5122 version.
Entering in Power-down Mode In order to reduce the power consumption, the microcont rol ler can be set in power-down
or idle mode by software (see Table 13, PCO N register). Before activating these modes
the application will need to configure the keyboard interface as follows:
• Set all keyboard’s ouputs pins KB Rx at low level by writing a 0 on the ports. This
operation has a double effe ct:
– any key that is pressed generates an interrupt capable of waking-up the
microcontroller,
– Se t all bits KBE.x in KBE registers to enable interrupts.
Exiting from P ower-down
Mode The microcontroller will exit from Power-down Mode upon a reset or any interrupt gener-
ated by a key press. Note that 1024 cloc ks are necessary to exit from power-down m ode
when a keyboard interrupt occurs. This means that there will be a delay between the
time at which the key is pressed and the time at which the a pplication is able to identify
the key.
Watchdog Timer during
Power-down and Id le
Mode
In Powe r- down mo de t he osc illato r s top s, w hich me ans the WDT al so s tops . Wh ile in
Power-do wn mo de th e user does not need to service the WDT. There are 2 methods of
exiting Power-down mode : by a hardware reset or by a level acti vated external interrupt
which is e nabled pri or to e nterin g power-down mod e. When Po wer-dow n is exited with
hardware reset, servicing the WDT should occur as it normally does whenever
AT8xC5122D is reset. Exiting Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to s tabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the int errupt is pulled high.
It is sugges ted that the WDT be reset duri ng th e interrupt service f or the interrupt u sed
to exit Power-down.
To ensure that the WDT does not overflow wi thin a f ew states of exiting of powerdown, it
is best to reset the WDT just before entering powerdown .
In the I dle mode, the oscillator continues to run. To prevent the WDT from resetting
while the m icrocontroller is in Idle mode, the use r s hould always s et up a timer that will
periodical ly exit Idle, service the WDT , and re-enter Idle mode.
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Registers
Rese t Value = 00X1 0000b
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect t he value of this bit.
Table 113. P owe r Control Register - PCON (S:87h)
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number Bit
Mnemonic Description
7SMOD1
Serial port Mod e bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3
6SMOD0
Serial port Mod e bit 0 for UART
Cleared to select SM0 bit in SCON register
Set to select FE bit in SCON register
5-
Reserved
The value read fr om this bit is indeterminat e. Do not change this bit.
4POF
Power-Off Flag (Only for ROM version parts)
Cleared to recognize next reset type
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software
Warning : in CRAM and FLASH versions, this bit is reserved.
3GF1
Gener a l purpose Flag
Cleared b y user fo r gene ral-purpose us age
Se t by us er f or ge ne r al - pu rp os e us age
2GF0
Gener a l purpose Flag
Cleared b y user fo r gene ral-purpose us age
Se t by us er f or ge ne r al - pu rp os e us age
1PD
Power-Down mode bit
Cleared by hardware when reset occurs
Set to enter pow er-dow n mode
0IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs
Set to enter idle mode
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Electrical Characteristics
Ab solu te Maximum Rati ngs
DC Parameters
TA = -40 to +8 5°C; VSS = 0 V, FCK_CPU= 0 to 24 MHz , V CC = 3.0V to 5.5V
Ambiant Temperat ure Under Bias ......................-25°C to 8 5°C
Sto rage Tem p e ra t ur e..... .. ... ..... .. .......... .. ... .... - 6 5°C to + 150°C
Voltage on VCC to VSS......................................-0.5 V to + 6.0V
Voltage on Any Pin to VSS........................-0.5 V to VCC + 0.5 V
Power Di ssipation 1 W
Note: Stresses at or above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the devi ce. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational
secti ons of this speci fication is not implied. Exposure
to absolute maximum rating conditions may affect
device reliabi li ty.
Power Dissipation value is based on the maximum
allowable die temperature and the t hermal resi stance
of the package.
S ymbol Par amete r Min Typ M ax Unit Te st C ond itio ns
VIL In pu t Low Vol tag e - 0.5 0. 2 VCC - 0.1 V
VIH Input High Voltage except XTAL1, RS T 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Inp ut High Voltage, XTAL1, RST 0.7 VCC VCC + 0.5 V
VOL Output Low Vo ltage: P0, ALE, PSEN 0.45 V IOL = 1.6 mA
VOH Output High Voltage: P0, ALE, PSEN 0.9 VCC VI
OH = 10 µ A
VOL1 Output Low Voltage: P2, P3, P4, P5, P 1 .2, P1.6,
P1.7 0.45 V IOL = 0.8 mA
VOH1 Output High Voltage: P2, P3, P4, P5, P1.2, P1.6,
P1.7 0.9 VCC VI
OH = -10 µA
IIL Logical 0 Input Current ports 2 to 5 and P1.2, P1.6,
P1.7, if Weak pull-up enabled -50 μA Vin = 0.45 V
ILI Input Leakag e Current ±10 μA0.45 V < V
IN < VCC
ITL Logica l 1 to O tra ns is t io n C urren t, P ort 51
configuration −650 μAV
IN = 2 V
RMEDIUM Medium Pullup Resistor 10 kΩ
RWEAK Weak Pullup Resistor 100 kΩ
CIO Capacitance of I/O Buffer 10 pF Fc = 1MHz
TA = 25°C
DVCC Digital Supply Voltage 3 3.4 3.6 V CL = 470 nF
DICC Digital Supply Output Current (DVcc pin) 10 mA CL = 100 nF
FCK_CPU = 24 MH z
VPFDP Power Fail High Level Threshold 2.8 3 V
VPFDM Power Fail Low Level Threshold 2,5 2.6 V
trise, tfall VDD rise and fall time 1μs 600 second
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RRST Internal reset pull-up resistor 5 10 30 k
Ω
IPD Po wer do w n co ns um p tio n 60µA
40µA 200µA
200µA Vcc = 5.5V
Vcc = 3 . 6V
ICCIDLE Po w er S up pl y cu r rent in ID L E mode 0.4*F+2 mA V cc = 5.5V (F in MHz )
ICCOP
Power Suppl y current in Active mod e
(AT89C5122) with DC/DC ON 1.6*F+3 mA Vcc = 5.5V (F in MHz)
ICCOP
Power Suppl y current in Active mod e
(AT85C5122) with DC/DC ON 1.6*F+3 mA Vcc = 5.5V (F in MHz)
ICCOP
Power Suppl y current in Active mod e
(AT83C5122) with DC/DC ON 1.6*F+2 mA Vcc = 5.5V (F in MHz)
ICCWRITE
Power Suppl y current in Active mod e
(AT89C5122) Flash or E2PROM wr ite DC/ DC ON 1.6*F+4 mA Vcc = 5.5V (F in MHz)
ICCOP
Power Suppl y current in Active mod e
(AT89C5122) with DC/DC OF F 0.8*F+3 mA Vcc = 5.5V (F in MHz)
ICCOP
Power Suppl y current in Active mod e
(AT85C5122) wit h DC/DC FF 0.8*F+3 mA Vcc = 5.5V (F in MHz)
ICCOP
Power Suppl y current in Active mod e
(AT83C5122) with DC/DC OF F 0.8*F+2 mA Vcc = 5.5V (F in MHz)
ICCWRITE
Power Suppl y current in Active mod e
(AT89C5122) Flash or E2PROM wr ite DC/ DC OFF 0.8*F+4 mA Vcc = 5.5V (F in MHz)
S ymbol Par amete r Min Typ M ax Unit Te st C ond itio ns
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ICC Cu rrent Tes t Co ndi t io ns F ig ure 111. Power Down Mode
Fi gure 112. Active and Idle Mode
LED’s
Note: 1. (TA = -20°C to +50°C, VCC - VOL = 2 V )
All other pins are disconnected.
EA
Ipd
VCC VCC
(NC)
P0
XTAL2
XTAL1
Vss
VCC
PLLF
GND GND
LI AVCC
GND
AVss
V
CC
GND
All other pins are disconnect ed.
EA
VCCIcc
VCC VCC
(NC)
P0
XTAL2
XTAL1
Vss
VCC
C LOCK SIGN AL PLLF
GND GND
LI AVCC
GND
AVss
Symbol Parameter Min Typ M ax Unit Test Conditions
IOL Output Low Current, P3.0 and P3.7 LED modes 1
2
5
3
6
10
5
8
20
mA
mA
mA
2 mA conf igura tion
4 mA conf igura tion
10 mA configuration
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Smart Card Interface
Card VCC 5V (for IEC7816-3 Class A cards)
Symbo l Pa r ame t er Min Typ Max Uni t Te st Cond it io ns
Vcc Pow er Supply 3.0 5.5 V
CICC_ovf C ard Supply Current overflow 100 m A
CVCC Card Supply Voltage 4.6 5.4 V VccMin = 4.0V, CICC = 6 0 mA
VccMin = 3. 0V, CICC = 3 0 mA
Ripple on Card Voltage 200 mV 0 < CIcc < 60 mA
CVCC Card Supply Voltage during spike on Icc 4.5 5.5 Max. charge 2 0 nA.s
Max . d uration 400 ns
Max. va r iati o n CICC 100 mA
TOFF CVcc to 0 750 μsCload=10µF, Lload=10µH
Vcard = CVcc to 0.4V
TON 0 to CVcc 750 μsCload=10µF, Lload=10µH
Vcard = 0V to CVcc
With Boost at 60 %
Card VCC 3V Po wer Supply (for IEC7816-3 Class B cards)
Symb ol P ara me ter Mi n Typ M a x Un it Te st Conditio ns
Vcc Power Supply 3.0 5.5 V
CICC_ovf Card Suppl y Current overflow 100 mA
CVCC Card Supply V oltage 2.76 3.24 V VccMin = 3.6V, CICC = 55mA
VccMin = 3.0V, CICC = 30 mA
Ripple on Vcard 200 mV 0 < CICC < 55mA
CVCC Card Supply Volt age during spike o n Icc 2.7 3.3 V Maxi. charge 10nA.s
Max . duration 400 ns
Max . variation CICC 50mA
TOFF CVcc to 0 750 μsCload =10µF, Lload=10µH
Vcard = CVcc to 0.4V
TON 0 to CVcc 750 μsCload =10µF, Lload=10µH
Vcard = 0V to CVcc
With Boost at 60%
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Notes: 1. Test conditions, Capacitor 10 µF, Inductance 10 µH.
2. Ceramic X7R, SMD type capacitor wit h minimum ESR or 250 m
Ω
is mandatory
Notes: 1. The voltage on CLK should remain between -0.3V an d VCC+0.3V during dynamic operat ion.
Card VCC 1.8V Power Supp ly (for IEC7816-3 Class C cards)
Symbol Parameter Min T yp M ax Unit Test Conditions
Vcc Power Supply 3.0 5.5 V
CICC_ovf Card Supply Current overflow 100 mA
CVCC Card Supply Voltage 1.68 1.92 V CICC = 35 mA
TOFF CVcc to 0 750 μsCload=10µF, Lload=10µH
Vcard = CVcc to 0.4V
TON 0 to CVc c 750 μsCload=10µF, Lload=10µH
Vc ard = 0V to CV c c
With Boost at 60%
Smart Card CCLK, DC parameters
Symb ol Pa ram et er Min Typ M ax Unit Te st Conditio ns
VOL Output Low Voltage 0(1) 0.4
0.1 5 CVCC
0.1 5 CVCC
VIOH = 50 μA (5V until 2009)
IOH = 100 μA (5V from 2009)
IOH = 100 μA (3V & 1 . 8V)
IOL Output Low Current 15 mA
VOH Output High Voltage CVCC-0,5
0.8 CVCC
0.8 CVCC
CVCC VIOH = 50μA (+5V until 2009)
IOH = 100 μA (+5V from 2009)
IOH = 100 μA (+3V & 1.8V)
IOH Output High Current 15 mA
tR tFRise and Fall delays 14.5
15.5
32 ns
CIN=30pF (5V)
CIN=30pF (3V)
CIN=30pF (1.8V)
Voltage S tabil ity -0.25
CVCC-0.5 0.4 CVCC
CVCC + 0.25 VL ow le ve l
High level
Frequency variation (Jitter) 1%
Cycle ratio 45% 55%
Smart Card CIO , DC Parameters
Symbol Parameter Min Typ Max Unit Test Conditions
VIL Input Low Voltage 0(1) 0.2 CVCC V
IIL Input Low Current 500 μA
VIH Input High V o lt age 0.6 CVCC CVCC V
IIH Input High Current -20 / +20 μA
VOL Out put Low Volt age 0(1) 0.15 CVCC V
IOL = 1 mA (5V & 3V))
IOL = 0.5 mA (1.8V)
Ext er nal 10 K p ul l-u p t ied to
CVCC
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Note: 1. The voltage on RST should rema in between -0.3V and VCC+0.3 V during dynamic operation.
Note: 1. The voltage on RST should rema in between -0.3V and VCC+0.3 V during dynamic operation.
IOL Output Low Cu rrent 15 mA
VOH Output High Voltage 0.8 CVCC CVCC (1) V IOH = 20 μA
Exte rnal 10K pull-u p
re sist or tie d to C VCC
IOH Output High Current 15 mA
Voltage S tabil ity -0.25
0. 8 CVCC
0.4
CVCC + 0.25 V Low lev e l
High level
tR tFRise and Fall delays 0.8 μsC
IN=30pF.
Smart Card RST, CC4, CC8, DC Parameters
Symb ol Pa ram et er Min Ty p M ax U nit Te st C ond itio ns
VOL Out put Low Volt age 0(1) 0.4
0.1 2 CVCC
0.1 2 CVCC
VIOL = 50 μΑ (5V until 2009)
IOL = 200 μΑ (5V from 2009 )
IOL = 200 μΑ (3V & 1.8V)
IOL Output Low Cu rrent 15 mA
VOH Output High Voltage CVCC-05
0.8 CVCC
0.8 CVCC
CVCC (1) VIOH = 50 μΑ (+5V until 2009)
IOH = 150 μΑ (+5V from 20 09)
IOH = 150 μΑ (+3V & 1.8V)
IOH Output High Current 15 mA
tR tFRise and Fall delays 0.8 μsC
IN=30 pF
Voltage S tabil ity -0.25
CVCC-0.5 0.4 CVCC
CVCC + 0.25 Low level
High level
Smart Card CIO , DC Parameters
Symbol Parameter Min Typ Max Unit Test Conditions
Card Presence (P 1.2) DC Parameters
Sym bol P ara me t er Min Typ M a x Unit Te st C ond itio ns
IOL1 C PR ES w ea k pu ll-up outp ut curre nt 3 10 25 μAP1.2=1, short to VSS
Pull-up enabled
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USB Interface Figu re 113. USB Interface
Symbol Parameter Min Typ(5) Max Unit
VREF USB Ref erence Volt age 3.0 3. 6 V
VIH Input High Voltage for D+ and D- (driven) 2.0 4.0 V
VIHZ Input High Voltage for D+ and D- (floating) 2.7 3.6 V
VIL Input Low Voltag e for D+ and D- 0.8 V
VOH Output High Voltage for D+ and D- 2.8 3.6 V
VOL Output Low Voltage for D+ and D- 0.0 0.3 V
193
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AC Para mete rs
Explanation of the AC
Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for
time). The other characters, depending on their positions, stand for the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time fo r ALE Low to PSEN Low.
TA = -40°C to +85°C; VSS = 0V ; VCC = 3 .0V to 5.5V ; FCK_CPU = 0 to 24 MHz.
( Load Capac ita nce f or por t 0, A LE an d PS EN = 60 pF ; L oad Ca paci tan ce fo r all ot her
outputs = 60 pF.)
Table and Table 118 give the description of each AC symbols.
Table 117 and T able 120 give for each range the AC parameter.
Table 115, Table 117 and Table 119 give the frequency derating formula of the AC
param eter for each speed rang e description. To calculat e each AC symbols. take the x
value and use this v alue in the formul a.
Example: TLLIV and 20 MHz, St andard c lock.
x = 30 ns
T = 50 ns
TCCIV = 4T - x = 170 ns
Ext ernal Prog ram Mem ory
Characteristics Table 114. S ym bol Desc ription
Symbol Parameter
T CPU clock period (FCK_CPU)
TLHLL ALE pulse width
TAVLL Address Valid to ALE
TLLAX Address Hold After ALE
TLLIV ALE to Valid Instruction In
TLLPL ALE to PSEN
TPLPH PSEN Pulse Width
TPLIV PSEN to Valid Instruction In
TPXIX Input Instruction Hold After PSEN
TPXIZ Input Instruction Float After PSEN
TAVIV Address to Valid Instruction In
TPLAZ PSEN Low to Address Float
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Ext ernal Prog ram Mem ory
Read Cycle
Table 115. A C P aram eters for a Variable Clock
Symbol Type Standard
c lock X2 Clock X parameter Units
TLHLL Min 2 T - x T - x 15 ns
TAVLL Min T - x 0.5 T - x 20 ns
TLLAX Min T - x 0.5 T - x 20 ns
TLLIV M ax 4T - x 2 T - x 35 ns
TLLPL Min T - x 0.5 T - x 15 ns
TPLPH Min 3T - x 1.5 T - x 25 ns
TPLIV Max 3T - x 1.5 T - x 45 ns
TPXIX Min x x 0 ns
TPXIZ Max T - x 0.5 T - x 15 ns
TAVIV Max 5T - x 2 .5 T - x 45 ns
TPLAZ Max x x 10 ns
12 TCLCL
TLLIV
TLHLL TLLPL
ALE TPLPH
PSEN
PORT 0 INSTR IN A0-A7 INSTR IN A0-A7 INSTR IN
TLLAX TPLAZ
TPXAV
TAVLL TPXIX TPXIZ
TPLIV
TAVIV
PORT 2 ADDRESS
OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15
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Exte rnal Data M em ory
Characteristics Table 116. S ym bol Desc ription
Symbol Parameter
TRLRH RD Pulse Width
TWLWH WR Pulse Width
TRLDV RD to V alid Data In
TRHDX Data Hold After RD
TRHDZ Data Float After RD
TLLDV ALE to Valid Data In
TAVDV Address to Valid Data In
TLLWL ALE to WR or RD
TAVWL Address to WR or RD
TQVWX Data Valid to WR Tran s iti on
TQVWH Data set-up to WR High
TWHQX Data Hold After WR
TRLAZ RD Low to Address Float
TWHLH RD or WR High t o ALE high
196
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Table 117. A C P aram eters for a Variable Clock
(warning x value differ from AT89C51RD2)
External Data M e mory Write
Cycle
Symbol Type Standard
Clock X2 Clock X parameter Units
TRLRH Min 6 T - x 3 T - x 20 ns
TWLWH Min 6T - x 3 T - x 20 ns
TRLDV Max 5T - x 2.5 T - x 25 ns
TRHDX Min x x 0 ns
TRHDZ Max 2T - x T - x 20 ns
TLLDV Max 8T - x 4T - x 40 ns
TAVDV Max 9T - x 4.5 T - x 60 ns
TLLWL Min 3T - x 1.5 T - x 25 ns
TLLWL Max 3T + x 1.5 T + x 25 ns
TAVWL M i n 4T - x 2 T - x 25 ns
TQVWX Min T - x 0.5 T - x 15 ns
TQVWH Min 7 T - x 3.5 T - x 25 ns
TWHQX Min T - x 0.5 T - x 10 ns
TRLAZ Max x x 0 ns
TWHLH Min T - x 0.5 T - x 15 ns
TWHLH Max T - x 0.5 T + x 15 ns
TQVWH
TLLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TQVWX
ADDRESS A8-A15 OR SFR P2
TWHQX
TWHLH
TWLWH
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Exte rna l Data Memo ry R ead
Cycle
Serial Port Timing - Shift
Register Mod e Table 118. S ymbol Description (F = 40 MHz )
Table 119. A C P aram eters for a Variable Clock
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TRLAZ
ADDRESS A8 -A 15 OR SFR P2
TRHDZ
TWHLH
TRLRH
TLLDV
TRHDX
TLLAX
TAVDV
Symbol Parameter
TXLXL Seri al p ort clock cycle time
TQVHX Output data set-up to clock rising edge
TXHQX Output data hold after clock rising edge
TXHDX Input data hold after clock rising edge
TXHDV Clock rising edge to input data valid
Symbol Type Standard
Clock X2 Clock X parameter Units
TXLXL Min 12T 6 T ns
TQVHX Min 10T - x 5 T - x 50 n s
TXHQX Min 2T - x T - x 20 n s
TXHDX Min x x 0 ns
TXHDV Max 10T - x 5 T- x 133 ns
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Shi ft Regis te r Timi ng
Waveform
Externa l Clock Drive
Characteristics (XTAL1) T ab le 120. AC Parameters
Externa l Clock Drive
Waveforms
AC Testing Input/Output
Waveforms
AC in puts during testin g are driven at VCC - 0.5 fo r a logic “1” and 0. 45V for a logic “0”.
Timing m easurem ent are made at VIH min for a logi c “1” and VIL max for a logic “0”.
VALID VALID VALID VALID VALIDVALID
INPUT DAT A VALID
0123456 87
ALE
CLOCK
OUTPUT DATA
WRITE to SBUF
CLEAR RI
TXLXL
TQVXH TXHQX
TXHDV TXHDX SET TI
SET RI
INSTRUCTION
01234567
VALID
Symbol Parameter Min Max Units
TCLCL Oscillator Period 125 ns
TCHCX High Time 5 ns
TCLCX Low T ime 5 ns
TCLCH Rise Time 5 ns
TCHCL Fall T i me 5 ns
TCHCX/TCLCX Cyclic ratio in X2 mode 40 60 %
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL TCLCX TCLCL
TCLCH
TCHCX
INPUT/OUTPUT 0.2 VCC + 0. 9
0.2 VCC - 0.1
VCC -0.5V
0.45V
199
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Float Waveforms
For t iming pu rposes as port pin is no longer flo ating when a 10 0 mV ch ange from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL le v el
occurs. IOL/IOH ≥ ± 20 mA.
Clock Waveform s Valid in norm al clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
FLOAT
VOH - 0.1 V
VOL + 0.1 V
VLOAD VLOAD + 0.1 V
VLOAD - 0.1 V
DATA PCL OUT DATA PCL OUT DATA PCL OUT
SAMPLED SAMPLED SAMPLED
STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
FLOAT FLOAT FLOAT
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
INDICATES ADDRESS TRANSITIONS
EXTE RNAL P ROGRAM MEMORY FETCH
FLOAT
DATA
SAMPLED
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXT ERN AL)
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
PCL OUT (IF PROGRA
M
MEMORY IS EXTERNA
L)
OLD DATANEW DATA P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAM PLED
P0 PINS SAMPL ED
RXD SAMPLED
INTERNAL
CLOCK
XTAL2
ALE
PSEN
P0
P2 (EXT)
READ CYCLE
WRITE CYCLE
RD
P0
P2
WR
PORT OPERAT ION
MOV PO RT SRC
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0
P2
RXD SAMPLED
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This diagram indi cates when signa ls are clocked in ternally. The time it takes the signals
to prop agate to the pins, h owever, ra nges from 25 to 12 5 ns. This propagat ion delay is
dep en dent on vari able s such as tempe ratu re and pin l oad ing. Pr opa gation als o vari es
from output to ou tput an d compo nent . Typicall y thou gh (TA=25°C fu ll y loa ded ) RD an d
WR propagatio n delays are ap proxima tely 50 ns. The other sig nals ar e typ ically 85 ns.
Propagation delays are inc orporated in the AC specifications.
USB Interface
Rise Ti me Fall Time
VCRS
Differential
Data Lines
90%
10%
90%
10%
tRtF
VHmin
VLmax
Symbol Parameter Min Typ(5) Max Unit
tRRise T im e 4 20 ns
tFFa ll Time 4 20 ns
tFDRATE Full-speed Data Rate 11.9700 12.0300 Mb/s
VCRS Crossover Voltage 1.3 2.0 V
tDJ1 Source Jitter Total to next transaction -3.5 3.5 ns
tDJ2 Sou r ce Jitt er To tal fo r paired
transactions -4 4 ns
tJR1 Receiver Jitter to next transaction -18.5 18.5 ns
tJR2 Receiver Jitter for paired transactions -9 9 ns
201
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Packaging
Information
Ordering Information
Standard
Part Number Lead free/ R oHS
Part Number Memor y Size
(bytes) Supply
Voltage (V) Temperature
Range Max Frequency
(MHz) Package Packing
AT83C5122xxx-RDTIM AT83C5122xxx-RDTUM 32K ROM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray
AT83C5122xxx-RDRIM AT83C5122xxx-RDRUM 32 K ROM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tape & Reel
AT83C5122xxx-SISIM AT83C5122xxx-SISUM 32K ROM 3. 0 - 5.5 Industrial 48 MH z / X1 PLCC28 Stick
AT83C5122xxx-SIR IM AT83C5122xxx-SU RIM 32K ROM 3.0 - 5.5 Industrial 48 MHz / X 1 PLCC28 Tap e & Reel
AT83C 5122xxx-PSVI M AT83C5122xxx- PSTUM 32K ROM 3.0 - 5.5 Industrial 48 MHz / X 1 QFN64 Tray & Dry
Pack
AT83C5122xxx-PSFIM AT83C5122xxx-PSRUM 32K ROM 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tape & Reel &
Dry Pack
AT83EC5122xxx-RDVIM AT83EC5122xxx-RDTUM 30K ROM +
512 Bytes
EEPROM 3. 0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray & Dry pac k
AT83EC5122xxx-RDFIM AT83EC5122xxx-
RDRUM
30K ROM +
512 Bytes
EEPROM 3. 0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tape & Reel
& Dry pack
AT83EC5122xxx-PSVIM AT83EC5122xxx-PSTUM 30K ROM +
512 Bytes
EEPROM 3. 0 - 5.5 Industrial 48 MHz / X1 QFN64 Tray & Dry
Pack
AT83EC5122xxx-PSFIM AT83EC5122xxx-PSRUM 30K ROM +
512 Bytes
EEPROM 3. 0 - 5.5 Industrial 48 MHz / X1 QF N64 Tape & Reel &
Dry Pack
AT85C 5122D-RDTIM AT85C5122D-RD TU M 32K C RAM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray
AT85C5122D-RDRIM AT85C5122D-RDRUM 32 K CRA M 3.0 - 5.5 Industrial 48 MHz / X1 VQFP 64 Tape & Reel
AT85C5 122D-SISIM AT85C5122D-SISUM 32K CRAM 3.0 - 5.5 Industrial 48 MHz / X1 PLCC28 Stick
AT85C5122D-SIRIM AT85 C5122D- SIRUM 32K CRAM 3.0 - 5.5 Ind ustrial 48 MHz / X1 PLCC28 Tape & Reel
AT89C5122D-RDVIM(1) AT89C5122D-RDTUM 32 K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray & Dry pack
AT89C5122D-RDFIM(1) AT89C5122D-RDRUM 32K FLAS H 3.0 - 5.5 Ind ustrial 48 MHz / X1 VQFP64 Tape & Reel
& Dry pack
AT89C 5122D-PSVIM AT89C5122D-PSTUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tray & Dry
Pack
AT89C 5122D-PSFI M AT89C5122D-PSRUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tape & Reel &
Dry Pack
202
AT8xC5122/23
4202E–SCR–06/06
Note: 1. Check avaibility with sales office
AT89C5122DS-RD VIM AT89C5122DS -RDTUM 32K FLAS H 3.0 - 5.5 Industrial 4 8 MHz / X1 VQFP64 Tray & Dry
Pack
AT89C5122DS-RDFIM AT89C5122DS-RDRUM 32K FLASH 3.0 - 5.5 Indust rial 48 MHz / X1 VQFP64 Tape & Reel &
Dry Pack
AT89C 5122D S-PSVIM AT89C5122D-PSTU M 32 K FLASH 3.0 - 5.5 Industrial 4 8 MHz / X1 QFN64 Tray & Dry
Pack
AT89C5122DS- PSFIM AT89C5122D-PSRU M 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tape & Reel &
Dry Pack
AT83C5123xxx-RATIM AT83C5123xxx-RATUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP32 Tray
AT83C5123xxx-RARIM A T83C5123xxx-RARUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP32 Tape & Reel
AT83C5123xxx-SISIM AT83C5123xxx-S ISUM 30K ROM 3. 0 - 5.5 Industrial 48 MH z / X1 PLCC28 Stick
AT83C5123xxx-SIR IM AT83C5123xxx-SIRUM 3 0K ROM 3.0 - 5.5 Industrial 48 MHz / X 1 PLCC28 Tap e & Reel
AT83C 5123xxx-PUTI M AT83C5123xxx-PUTUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X 1 QF N32 Tray
AT83C5123xxx-PURIM AT83C51 23xx x-PURUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X 1 QFN32 Tape & Reel
AT83EC5123xxx-RAVIM AT83EC5123xxx-RATUM 30K ROM +
512 Bytes
EEPROM 3. 0 - 5.5 Industrial 48 MHz / X1 VQFP32 Tray & Dry pac k
AT83EC5123xxx-RAFIM AT83EC5123xxx-RARUM 30K ROM +
512 Bytes
EEPROM 3. 0 - 5.5 Industrial 48 MHz / X1 VQFP32 Tape & Reel
& Dry pack
AT83EC5123xxx-PUVIM AT83EC5123xxx-PUTUM 30K ROM +
512 Bytes
EEPROM 3. 0 - 5.5 Industrial 48 MHz / X1 QFN32 Tray & Dry
Pack
AT83EC5123xxx-PUFIM AT83EC5123xxx-PURUM 30K ROM +
512 Bytes
EEPROM 3. 0 - 5.5 Industrial 48 MHz / X1 QFN32 Tape & Reel &
Dry Pack
Standard
Part Number Lead free/ R oHS
Part Number Memor y Size
(bytes) Supply
Voltage (V) Temperature
Range Max Frequency
(MHz) Package Packing
203
AT8xC5122/23
4202E–SCR–06/06
Mechanical Dimensions
PLCC28 P ackag e
204
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VQFP6 4 P ackag e
205
AT8xC5122/23
4202E–SCR–06/06
PLCC68 Packag e
206
AT8xC5122/23
4202E–SCR–06/06
VQFP32 Package
207
AT8xC5122/23
4202E–SCR–06/06
QFN32 Pa ckage
208
AT8xC5122/23
4202E–SCR–06/06
QFN64 Pa ckage
209
AT8xC5122/23
4202E–SCR–06/06
Datasheet Revision History
Changes from 4202A to 4202B
1. Product AT8xEC5122 adde d.
2. Products AT83 C5123 and AT83EC512 3 added.
Changes from 4202B to 4202C
1. All se ctions upda ted.
2. QFN64 and QFN 32 packages added.
3. SCIB section : VCC mu st be higher than 4.0V when DC/DC is operated at 5V.
Changes from 4202C to 4202D
1. Product AT89C5 122DS added (EA pin changed to VCC)
2. Typical applications section : external pull-up shown on CIO pin
3. Ports sec tion : Det ailed explanations on CIO, CC4, CC8 quasi-bi di rectional port s
4. Ordering information section : AT89C5122DS part-numbers added
Changes from 4202D to 4202E
1. Changed input voltage frequency from 3.6V to 3.0V t hroughout the document.
2. Update of DC parameters of smart card interface to be EMV 4.1 compliant.
210 4202E–SCR–06/06
AT8xC5122/23
Table of Contents
Features ................................................................................................. 1
Reference Documents.......................................................................................... 2
Product Description.............................................................................................. 3
AT8xC5122 Block Diagram .................................................................................. 5
AT83C5 123 Block Diagram ..................................................................................5
Pinout .................................................................................................... 6
High Pin Count Package Description.................................................................... 6
Low Pin Count Package Description .................................................................. 11
Pin Description... ................................................................................................. 13
Typical Applicati ons .............. .......... ............................ ......... ......... ..... 17
Recomme nded E xternal components .................................................................17
USB Keyboard with Smart Card Reader Using the AT8xC 5122 and A T89 C5122DS Ver-
sions............................................................................................................................. 18
USB Smart Card Reader Using the AT83C5123 Vers ion................................... 19
Memory Organization ......................................................................... 20
Program Mem ory Managam ent.......................................................................... 20
Data Memory Managament............... ....... ..... ....... .. .......... ....... .. ....... .......... .. ...... 21
Dual Data Pointer Register (DDPTR)................................................................. 22
Registers............................................................................................................. 24
AT8xC5122’s CRAM and E 2PROM Versi ons ........................ .. ..... ....... ..... ....... ..26
AT8x C5 1 22’ s ROM Version........ ............ ....... ............ ....... ....... ............ ....... ........ 30
AT83C5123 V ersion .. ............ ....... ............ ....... ....... ............ ....... ....... ............ ...... 32
Special Function Registers (SFR’s) .................................................. 33
Introduction......................................................................................................... 33
AT8 xC5 1 22 Ver sion............. ....... ............ ....... ............ ....... ............ ....... ............ ... 34
AT83C5 123 Version . .......................................................................................... 35
SFR’s Descri ption............................................................................................... 36
Clock Controller .................................................................................. 41
On- Ch ip Osc il lator........ ....... ............ ....... ........................ ....... ........... ........ .......... 41
Phase Lock Loop (PLL).. ....... ....... ............ ....... ............ ............ ....... ............ ........ 42
Clock Tree Architecture...................................................................................... 43
Registers............................................................................................................. 50
I/O Port Definition ............................................................................... 53
Port Configuration............................................................................................... 57
Registers............................................................................................................. 61
Smart Card Interface Block (SCIB) ................................................... 64
Blo ck Diag ra m.............. ....... ........................ ....... ............ ....... ........... ........ .......... 65
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Definitions........................................................................................................... 65
Functional Descriptio n........................................................................................ 67
Additional Features.. .. ............ ............ .............. ....... ................. ......... ............ ...... 74
Alte rnate Card..................................................................................................... 78
Registers ........ ........... ........ ....... ............ ....... ........... ........ ........... ....... ............ .......78
DC/DC Converter.......... ....... ............ ....... ........................ ....... ........... ........ ....... ... 88
USB Controller .................................................................................... 95
Description .......................................................................................................... 96
Configuration ...................................................................................................... 99
Read/Write Dat a FIFO......... .. ....... ..... ..... .. ....... ..... .. .......... .. ..... .. ....... ..... ..... ...... 102
Bul k / In te r ru p t Tra n sa ctions.. ....... ........................ ....... ............ ....... ............ ...... 103
Control Transactions......................................................................................... 107
Is o ch r o nous Tra n sa c tions......... ............ ....... ........... ........ ........... ....... ............ .... 108
Miscel l a n eou s........ ............ ....... ............ ....... ....... ............ ....... ........... ........ ........ 110
Suspend/Resume Management ..................... ................. ......... ....... ............ .....111
Detach Simulation......... ....... ............ ....... ............ ....... ............ ....... ....... ............ . 114
USB Interrupt System....................................................................................... 115
Registers......... ........... ........ ....... ............ ....... ........... ........ ........... ....... ............ .... 117
Serial I/O Port .................................................................................... 126
Fra mi n g Erro r De te cti o n...... ....... ........................ ....... ............ ....... ............ ....... . 126
Automatic Addr ess Recognition. ....................................................................... 127
Asynchronous Modes (Modes 1, 2 and 3)... .... ....... ............ ....... ....... ............ .... 131
Modes 2 and 3................................................. ....... ................... ................... .... 132
Registers......... ........... ........ ....... ............ ....... ........... ........ ........... ....... ............ .... 135
Serial Port Interface (SPI) ................................................................ 137
Fe at u re s............ ....... ............ ....... ............ ....... ............ ....... ............ ....... ............ . 137
Signal Description......................... .......... ....... ....... ....... ....... ....... ....... ............ .... 137
Functional Descriptio n...................................................................................... 139
Timers/Counters ............................................................................... 147
Timer/Counter Operations................................................................................ 147
Timer 0.............................................................................................................. 147
Timer 1.............................................................................................................. 150
Registers......... ........... ........ ....................... ....... ............ ....... ............ ....... ........... 152
Keyboard Interface ........................................................................... 155
Introduction....................................................................................................... 155
Descri p tion........ ............ ....... ........................ ....... ............ ....... ....................... .... 155
Registers......... ........... ........ ....................... ....... ............ ....... ............ ....... ........... 156
Interrupt System ............................................................................... 159
Introduction....................................................................................................... 159
Int e r ru p t System Descr iption ................ ....... ....................... ....... ....................... 159
212 4202E–SCR–06/06
AT8xC5122/23
Registers......... ........... ........ ....... ............ ....... ........... ........ ........... ....... ............ .... 162
Interrupt Sources and Vectors.......................................................................... 171
Microcontroller Reset ....................................................................... 172
Introduction....................................................................................................... 172
Power On Reset (POR).................................................................................... 173
Power Fail Detector (PFD) ..... ............ ....... ............ ....... ....... ............ ....... ....... .... 173
Reset p in....................... ....... ............ ....... ............ ....... ............ ....... .................... 175
Watchdog Ti mer ............................................................................................... 177
Power Management .......................................................................... 180
Idle Mode.......................................................................................................... 180
Power Down Mod e .... ............ ....... ........................ ....... ........................ ....... ...... 180
Reduced EM I Mode.......................................................................................... 181
USB Interface ................................................................................................... 182
Smart Card Inter face ............. ....... ............ ....... ............ ....... ............ ....... ........... 183
Keyboard Interface ........................................................................................... 184
Watchdog Timer during Power-down and Idle Mode. ....... .. ....... ..... ....... ..... ...... 184
Registers......... ........... ........ ....... ............ ....... ........... ........ ........... ....... ............ .... 185
Ele ctrical Char act eristics ................ ............................ ......... ......... ... 186
Absolute Maximum Rat ing s ......... ........ ........... ....... ............ ....... ........................186
DC Parameters .................................................................................................1 86
LED’s ................................................................................................................188
Sma rt Card In te r face .... ............ ....... ............ ....... ............ ....... ........... ........ ........ 189
USB Interface ................................................................................................... 192
AC Pa ra me te rs. ....... ............ ....... ............ ....... ............ ....... ....... ............ ....... ...... 193
Float Waveforms............................................................................................... 199
Packaging Information ..................................................................... 201
Ord e rin g In fo rmation..... ............ ....... ............ ....... ............ ....... ........... ........ ........ 201
Mechanical Dimensions.................................................................................... 203
Datasheet Revision History ............................................................. 209
Changes from 4202 A to 4202B ........................................................................209
Changes from 4202 B to 4202C ........................................................................2 09
Changes from 4202 C to 4 202D ........................................................................2 09
Changes from 4202 D to 4202E ........................................................................209
Table of Contents ............................................................................. 210
Pr inted o n rec ycled paper.
4202E–SCR–06/06
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