es FAIRCHILD rer ere SEMICONDUCTOR m NDS9948 Dual P-Channel Enhancement Mode Field Effect Transistor General Description These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. Features M -2.3A, -BOV. Rogan = 0.250 @ Vag = -10V. m High density cell design for low Rosen). = High power and current handling capability i used surface mount package. = Dual MOSFET in surface mount package. February 1996 na widely Absolute Maximum Ratings T, = 25C unless otherwise noted Symbol | Parameter NDS9948 Units Vinge Drain-Source Voltage -60 V Vise Gate-Source Voltage +20 V I, Drain Current -Continuous T, = 25C (Note 1a) +23 - Pulsed T, = 250 +10 -Continuous = =T,= 70C (ote ta +18 P, Power Dissipation for Dual Qperation 2 W Power Dissipation for Single Operation (Note ta} 1.6 (Note 1b) 1 (Note 1c) 0.9 Ty. Tera Operating and Storage Temperature Range -65 to 150 C THERMAL CHARACTERISTICS Ray A Thermal Resistance, Junction-to-Ambient (Note 1) 78 CAN Rac Thermal Resistance, Junction-to-Case (Note 1) 49 CAN 1997 Fairchild Semiconductor Corporation NDS9948 SAMElectrical Characteristics (T, = 25C unless otherwise noted) Symbol | Parameter Conditions | Min | Typ | Max | Units OFF CHARACTERISTICS BV pac Drain-Source Breakdown Voltage Vos = 0 V, |p=-250 HA -60 Vv loss Zero Gate Voltage Drain Current Vos = 40 V, V5=0V 2 pA T, =55C 25 | pA Inger Gate - Body Leakage, Forward Veg =20V, Vag= OV 100 nA lnesr Gate - Body Leakage, Reverse Vos = -20V, Vi= OV -100 | nA ON CHARACTERISTICS poe 2) Vestn) Gate Threshold Voltage Vos = Ves: |, = -250 PA -1 -24 3 Vv [T,=15c | 08 | 2 | 26 Rosrony Static Drain-Source On-Resistance Veg =-10V, 1,=-29A 0.21 | 0.25 Q T,=125C o3 | o4 Veg =-4.5V, |,=-1.6A 0.36 | 05 lyr) On-State Drain Current Vag =-10V, Vig =-5 V -10 A rs Forward Transconductance Vog = 15 V, p= -2.3A 35 s DYNAMIC CHARACTERISTICS C., Input Capacitance Vog = -25V, V5 =0V, 570 pF Cos Output Capacitance f= 1.0 MHz 140 pF Cres Reverse Transfer Capacitance 40 pF SWITCHING CHARACTERISTICS (note 2) botany Turn - On Delay Time Vip =-30V, |, =-1A, 8 15 ns t, Turn - On Rise Time Vey = 10 V, Rony = 6 O 20 49 ns en Turn - Off Delay Time 20 40 ns L Turn - Off Fall Time 5 20 ns Q, Total Gate Charge Vig =-30V, 16 25 no Q,, Gate-Source Charge p= 23A, Vog=-10V 2 nc Q., Gate-Drain Charge 4 nc NDS9948 SAMElectrical Characteristics (T, = 25C unless otherwise noted) Symbol | Parameter | Conditions | Min | Typ | Max | Units DRAIN-SOURCE DIGDE CHARACTERISTICS AND MAXIMUM RATINGS le Maximum Continuous Drain-Source Diode Forward Current -17 Veo Drain-Source Diode Forward Voltage [Ves =0V, I=-29A onin2) gs] 12 | Vv Notes 1 Ag, 8 the sum of the unction-to-case and case-to-ambient thermal resistance where the case thermal reference ig defined as the solder mounting surface of the drain pins Ry,.i8 guaranteed by design while R,,,is determined by the user's board design _ Ty-Ta Tyla e Pol) = ee = Forman (ol) Rosav sar, Typical R,,, for single device operation using the board layouts shown below on 4 5"x5" FR-4 PCB in a still air environment a 78CAW when mounted on @ 0 5in* pad of 2oz cpperr b 125CAW when mounted on a 0 02 in pad of 20z cpper c 135C when mounted on a 0 003 ir? pad of 207 cpper tanger 1b tc Qe Cgpgea 7 tind cri vt a bh de G dhe Scale 1 1 on letter size paper ? Pulse Test Pulse Width <300us Duty Cycle < 2 0% NDS9948 SAMTypical Electrical Characteristics Roston) YORMALIZED DRAIN-SCUIRCE ON-RESISTANCE Ip DRAIN'SGURGE CURRENT (A) DRAIN CURRENT (A) be Fi] o bo -2 3 4 Vog DRAIN-SOURCE VOLTAGE () Figure 1. On-Region Characteristics. io ha a oo D6 -5D -25 Q 25 50 75 100 125 T, , JUNCTION TEMPERATURE (C) Figure 3. On-Resistance Variation with Temperature. b 0 Vg = -10 Ty = 88% / , 125C |, =-23A I Vagg = -10 150 -3 Figure 5. Voltage and Temperature. 4 V__ , GATE TO SOURGE as 5 VOLTAGE t) -6 Drain Current Variation with Gate R DSton}) NORMALIZED DRAIN-SOURCE ON-RESISTANCE Rogyony ORMAL IZED th NORMALIZED GATE-SOURCE THRESHOLD VOLTAGE (} os QO 3 6 3 Ip , DRAIN GURRENT (A) Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. 3 Vag = -10 Ww oO Zz = bb 2 io Ty= 128C r z oe nl o a 25C liam a 1 a 55C z = c a 5 Oo -3 -6 9 -12 -15 5 , DRAIN GURRENT (tA) Figure 4. On-Resistance Variation with Drain Current and Temperature. 12 lan Vog= Vas " Ip =-250NA | 4 09 Ph oe ~~ ay -50 -25 0 25 50 7S 100 125 150 T, JUNCTION TEMPERATURE (%)} J Figure 6. Gate Threshold Variation with Temperature. NDS9948 SAMTypical Electrical Characteristics (continued) 115 > = ly = 250A a all = oe 1 La = us Le 5B = >= wl z g 105 La tf a4 "| 3g TJ= 58C > & z ae 4 6 ay fa 5 aA w 5 095 LL u Zz p a <= 7 r ao ag -50 -25 0 25 50 75 100 425 150 0 004 7), JUNCTION TEMPERATURE {C} 03 06 O89 Ve 15 18 2 Ven , BODY DIODE FORWARD VOLTAGE t) Figure 7. Breakdown Voltage Variation with Figure 8. Body Diode Forward Voltage Variation Temperature. with Current and Temperature. {ooo 10 A Vog = -10 lbp = -2 3A PS je -30 500 = s = 6 a _ 300 8 jp | -poy 4 F = 200 So 6 4A a > 2 Ww 3 4. @ 100 B 4 : ti 50 z | f=1MHz ar a0 Vag = OV wf 20 D O71 o2 o5 1 2 5 10 20 5D D 5 io 15 PO -Vog , DRAIN TO SOURGE VOLTAGE (V) Q@ g, GATE CHARGE int} Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics. -Vopb ae t he Y t ee x d(on) R L Di < Vout y a ~ OUT 0, 10% PULSE WIDTH | INVERTED Figure 11. Switching Test Circui.t Figure 12. Switching Waveforms. NDS9948 SAMTypical Electrical Characteristics (continued) _ Vong =-15 T, = 85C wn L i ii 25C z a 4 = & i 2 a 126C = L a] i a a a fo z 5 2 Z Vag = 10 g 4 SINGLE PULSE = | Raia = 100 C/W im Ta = 25C fa a Q 0 2 -4 -6 6 -10 01 o2 o5 1 2 5 1B 6o 100 |, DRAIN CURRENT {A} - Vos , DRAIN-SOURCE VOLTAGE () Figure 13. Transconductance Variation with Drain Figure 14. Maximum Safe Operating Area. rit) NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE Current and Temperature. os oe Rua ti) = tt) * Raga a1 R gua = See Note ic oo05 PAph} oo2 oo te bem ty 1 oot Single Pulse hag ~ tg el 0 005 7 lps Ty Ty =P Raga bone Duty Cycle, D =ty/tos bool booool Boot boi o1 1 1b {oo 300 t1 TIME (sec) Figure 15. Transient Thermal Response Curve. Note Thermal characterization performed using the conditions described in note 1 Transient thermal response will change depending on the circuit board design NDS9948 SAM