LM3450MTX/NOPB - Texas Instruments

ZCD

GATE

LM3450/50A

GND

COMP

HOLD

DIM

FLT2

FLT1

PWM

BIAS

RETURN

SECONDARY

LED DRIVER

OPTICAL

ISOLATION

RETURN

EMI FILTER

PWM

INPUT

LED

LOAD

VCC

VAC

ISEN

VREF

VADJ

HOLD

LM3450

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SNVS681D –NOVEMBER 2010–REVISED MAY 2013

LED Drivers with Active Power Factor Correction and Phase Dimming Decoder

Check for Samples: LM3450

1FEATURES DESCRIPTION

The LM3450/50A is a power factor controller (PFC)

2• Critical Conduction Mode PFC with separate phase dimming decoder. The PFC

• Over-Voltage Protection regulates the output voltage while maintaining

• Feedback Short Circuit Protection excellent power factor. The phase dimming decoder

interprets the phase angle and remaps it to a 500Hz

• 70:1 PWM Decoded From Phase Dimmer PWM output. This device is ideal for implementing a

• Analog Dimming dimmable off-line LED driver for 10-100W loads.

• Programmable Dimming Range The phase dimming decoder has several unique

• Digital Angle and Dimmer Detection features. The input-output mapping is programmable

• Dynamic Holding Current for design flexibility, while a dynamic filter and

variable sampling rate provide smooth uniform

• Smooth Dimming Transitions dimming. A dynamic hold circuit ensures that the

• Low Power Operation phase dimmer angle is decoded properly while

• Start-Up Pre-Regulator Bias minimizing extra power loss.

• Precision Voltage Reference The LM3450A is identical to the LM3450 with the

exception of one circuit operation. The dynamic hold

APPLICATIONS current is sampled in the LM3450 while it

continuously operates in the LM3450A. This

• Dimmable Downlights, Troffers, and Lowbays difference between the two devices defines the

• Large Form Factor Bulbs suitable applications for each. The following is a

• Indoor and Outdoor Area SSL general guideline for choosing the correct device:

• Power Supply PFC • Any 120V designs with POUT > 15W - LM3450A

• Any 230V designs with POUT > 25W - LM3450A

• 120V 2-Stage designs with POUT < 15W - LM3450

• 230V 2-Stage designs with POUT < 25W - LM3450

Typical Application

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

VCC

VREF

ZCDFLT2

DIM GATE

VAC CS

COMP GND

FB ISEN

HOLDVADJ

FLT1

BIAS

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

www.ti.com

Connection Diagram

Top View

Figure 1. 16-Lead TSSOP

Package Number PW

PIN DESCRIPTIONS

Pin Name Description Application Information

Reference Output: Connect directly to VADJ or to resistor divider feeding VADJ

1 VREF 3V Reference and to necessary external circuits.

Analog Dim and Phase Dimming Range Input: Connect directly to VREF to force

standard 70% phase dimming range. Connect to resistor divider from VREF to

2 VADJ Analog Adjust extend usable range of some phase dimmers or for analog dimming. Connect to

GND for low power mode.

Ramp Comparator Input: Connect a series resistor from FLT1 capacitor and a

3 FLT2 Filter 2 capacitor to GND to establish second filter pole.

Angle Decoder Output: Connect a series resistor to a capacitor to GND to

4 FLT1 Filter 1 establish first filter pole.

Open Drain PWM Dim Output: Connect to dimming input of output stage LED

5 DIM 500 Hz PWM Output driver (directly or with isolation) to provide decoded dimming command.

Multiplier and Angle Decoder Input: Connect to resistor divider from rectified AC

6 VAC Sampled Rectified Line line.

Error Amplifier Output and PWM Comparator Input: Connect a capacitor to GND

7 COMP Compensation to set the compensation.

Error Amplifier Inverting Input: Connect to output voltage via resistor divider to

control PFC voltage loop for non-isolated designs. Connect a 5.11kΩresistor to

8 FB Feedback GND for isolated designs (bypasses error amplifier). Also includes over-voltage

protection and shutdown modes.

Input Current Sense Non-Inverting Input: Connect to diode bridge return and

9 ISEN Input Current Sense resistor to GND to sense input current for dynamic hold. Connect a 0.1µF

capacitor and Schottky diode to GND, and a 0.22µF capacitor to HOLD.

10 GND Power Ground System Ground

MosFET Current Sense Input: Connect to positive terminal of sense resistor in

11 CS Current Sense PFC MosFET source.

12 GATE Gate Drive Gate Drive Output: Connect to gate of main power MosFET for PFC.

Power Supply Input: Connect to primary bias supply. Connect a 0.1µF bypass

13 VCC Input Supply capacitor to ground.

Demagnetization Sense Input: Connect a 100kΩresistor to transformer/inductor

14 ZCD Zero Crossing Detector winding to detect when all energy has been transferred.

Open Drain Dynamic Hold Input: Connect to holding resistor which is connected

15 HOLD Dynamic Hold to source of passFET.

Pre-regulator Gate Bias Output: Connect to gate of passFET and through

16 BIAS Pre-regulator Gate Bias resistor to rectified AC (drain of passFET) to aid with startup.

Product Folder Links: LM3450

LM3450

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SNVS681D –NOVEMBER 2010–REVISED MAY 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS (1)(2)

VCC, HOLD, DIM, BIAS -0.3V to 25.0V

HOLD Power 250 mW Continuous

BIAS Current 5.0mA Continuous

ZCD Current +/- 10mA

COMP, FB, VAC, FLT1, FLT2, VREF, CS, VADJ -0.3V to 7.0V

ISEN -7.0V to 7.0V

GATE -0.3V to 18V Continuous

-2.5V for 100ns

20.5V for 100ns

-1mA to +1mA Continuous

Continuous Power Dissipation Internally Limited

Maximum Junction Temperature Internally Limited

Storage Temperature Range -65°C to +150°C

Maximum Lead Temperature (Solder and Reflow) (3) 260°C

ESD Susceptibility (4) HBM 2kV

MM 200V

FICDM 750V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified and do not imply ensured performance limits. For specified performance limits and associated

test conditions, see the Electrical Characteristics table. All voltages are with respect to the potential at the GND pin, unless otherwise

specified.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) Refer to http://www.ti.com/packaging for more detailed information and mounting techniques.

(4) Human Body Model, applicable std. JESD22-A114-C. Machine Model, applicable std. JESD22-A115-A. Field Induced Charge Device

Model, applicable std. JESD22-C101-C.

OPERATING CONDITIONS (1)

VCC Range 8.5V to 20V

Junction Temperature Range -40°C to +125°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified and do not imply ensured performance limits. For specified performance limits and associated

test conditions, see the Electrical Characteristics table. All voltages are with respect to the potential at the GND pin, unless otherwise

specified.

Product Folder Links: LM3450

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

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ELECTRICAL CHARACTERISTICS(1)

Unless otherwise specified VCC = 14V. Specifications in standard type face are for TJ= 25°C and those with boldface type

apply over the full Operating Temperature Range ( TJ=−40°C to +125°C). Typical values represent the most likely

parametric norm at TA= TJ= +25°C, and are provided for reference purposes only.

Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units

SUPPLY VOLTAGE INPUT (VCC)

VCC-RISE Controller Enable Threshold VCC Rising 12.2 13.0 13.6 V

VCC-FALL Controller Disable Threshold VCC falling 7.4 7.9 8.5

Glitch Filter Delay 9 µs

Turn-on Delay 40

IQVCC Quiescent Current No Switching 1.6 mA

IQ-SD VCC Shutdown Current VFB = 0V 515 625 µA

ERROR AMPLIFIER & COMPENSATION (FB, COMP)

VFB FB Reference (Normal Operation) 2.43 2.50 2.57 V

Input Bias Current VFB = 2.5V 100 nA

GMTransconductance VFB =2.5V 69 115 161 µS

Output Source / Sink Capability 60 85 110 µA

FB Pull-up Current Source VFB < 1.8V 43 51 59

COMP Pull-up Resistor 5 kΩ

VCMP-B COMP Low Threshold (Burst) VCMP Falling VTHM -0.08 V

COMP Low Hysteresis 20

VFB-SD Low Threshold (Shutdown) VFB Falling 150 168 186

FB Low Hysteresis 20 mV

VFB-EAD FB Mid Threshold (EA Disabled) VFB Falling 328 346 368

FB Mid Hysteresis 20

VFB-OV FB High Threshold (Over-voltage) 1.20 x VFB 1.22 x VFB V

COMP Pre-bias Source Current VCMP= 0.5V 415 µA

VTHM Minimum COMP Voltage (Normal) 1.47 V

ANGLE DEMODULATION & MULTIPLIER (COMP, VAC)

VAC-DET VAC Angle Detection Threshold 334 356 378 mV

Angle Demodulation Delay Time Both edges 8 µs

VAC Dynamic Input Voltage Range 0 to 5.5 V

COMP Dynamic Input Voltage Range VTHM to

VTHM+2

VAC Input Impedance 500 kΩ

KMMultiplier Gain (Includes Internal VAC = 3V, VCMP =0.5 1/V

Resistor Divider) VTHM+1.5V

ZERO CURRENT DETECTOR (ZCD)

VZCD-RIS ZCD Input Threshold VZCORising 1.45 1.5 1.55 V

Hysteresis 150 200 250 mV

Delay to Output 135 ns

VZCD-H Positive Clamp Voltage IZCO = 1mA 6.0 V

VZCD-L Negative Clamp Voltage IZCO = –50µA 0.61

PWM COMPARATOR (CS)

VOS PWM Comparator Input Offset Voltage 30 mV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified and do not imply ensured performance limits. For specified performance limits and associated

test conditions, see the Electrical Characteristics table. All voltages are with respect to the potential at the GND pin, unless otherwise

specified.

(2) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are

100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)

methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).

(3) Typical numbers are at 25°C and represent the most likely norm.

Product Folder Links: LM3450

LM3450

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SNVS681D –NOVEMBER 2010–REVISED MAY 2013

ELECTRICAL CHARACTERISTICS(1) (continued)

Unless otherwise specified VCC = 14V. Specifications in standard type face are for TJ= 25°C and those with boldface type

apply over the full Operating Temperature Range ( TJ=−40°C to +125°C). Typical values represent the most likely

parametric norm at TA= TJ= +25°C, and are provided for reference purposes only.

Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units

PWM Comparator Input Bias Current 20 nA

VLIM CS Current Limit Threshold 1.40 1.50 1.60 V

CS Delay to Output 100 ns

CS Blanking Sinking Impedance 1 kΩ

tLEB Leading Edge Blanking (LEB) Time 140 ns

ANALOG ADJUST INPUT (VADJ)

VADJ-LP VADJ Low Threshold (Low Power Mode) VADJ Falling 56 75 mV

VADJ Low Hysteresis 50

VADJ Pull-up Current Source 1 µA

VADJ Open Voltage VADJ Open 3 V

DYNAMIC HOLD CIRCUIT (HOLD, ISEN)

RDSON-HD HOLD MosFET On-Resistance ISEN Short to GND 22 30 42 Ω

VSEN-REF ISEN Reference Voltage 162 200 232 mV

ISEN Bias Current 5 µA

PRE-REGULATOR GATE DRIVE OUTPUT (BIAS)

VBIAS BIAS High Voltage @ 100µA VCC < VCC-FALL 18.8 21 22.6 V

BIAS Low Voltage @ 100µA VCC > VCC-RISE 13.5 14 14.5

GATE DRIVER OUTPUT (GATE)

VGATE-H GATE Voltage High IGATE = 20mA 11.5 V

IGATE = 200mA 10.5

GATE Pull Down Resistance 2 8Ω

GATE Peak Current (4)±1.5 A

REFERENCE VOLTAGE OUTPUT (VREF)

VREF Reference Voltage No Load 2.85 33.15 V

Current Limit 1.5 2.0 3.0 mA

DIMMING OUTPUT (DIM, FLT1, FLT2)

FLT1 Output Impedance Standby Mode 500 kΩ

Transition mode 1.6

Triangle Waveform Compared to FLT2 High 1.49 V

Low 15 mV

fDIM DIM Frequency 180 460 700 Hz

OFF-TIMERS

tOFF-MAX Maximum Off-Time (Normal Operation) 340 µs

tOFF-LP Off-Time (Low Power Mode) 42

THERMAL SHUTDOWN

Thermal Limit Threshold (4) 160 °C

Thermal Limit Hysteresis 20

THERMAL RESISTANCE

θJA Junction to Ambient TSSOP-16(4)(5) 38.0 °C/W

θJC Junction to Case 10.0

(4) These electrical parameters are specified by design, and are not verified by test.

(5) Junction-to-ambient thermal resistance is highly board-layout dependent. In applications where high maximum power dissipation exists,

namely driving a large MOSFET at high switching frequency from a high input voltage, special care must be paid to thermal dissipation

issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to be derated.

Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C for Q1, or

150°C for Q0), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance

of the package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).

Product Folder Links: LM3450

TEMPERATURE (°C)

GM (S)

140

130

120

110

100

-50 -14 22 58 94 130

TEMPERATURE (°C)

VBIAS (V)

-50 -14 22 58 94 130

BIAS High

BIAS Low

TEMPERATURE (°C)

VLIM (V)

1.505

1.503

1.501

1.499

1.497

1.495

-50 -14 22 58 94 130

TEMPERATURE (°C)

0.510

0.504

0.498

0.492

0.486

0.480

-50 -14 22 58 94 130

TEMPERATURE (°C)

RDS-ON ()

-50 -14 22 58 94 130

TEMPERATURE (°C)

tLEB (ns)

150

146

142

138

134

130

-50 -14 22 58 94 130

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

www.ti.com

TYPICAL PERFORMANCE CHARACTERISTICS

TA=+25°C and VCC = 14V unless otherwise specified

HOLD RDSON vs. Junction Temperature Leading Edge Blanking vs. Junction Temperature

Figure 2. Figure 3.

Current Limit Threshold vs. Junction Temperature Multiplier Gain vs. Junction Temperature

VAC = 3V; VCMP = VTHM + 1.5V VAC = 3V; VCMP = VTHM + 1.5V

Figure 4. Figure 5.

Transconductance BIAS Voltage vs. Junction Temperature

VFB = 2.5V; ΔVFB = 50mV High @ VCC < VCCFALL; Low @ VCC > VCCRISE

Figure 6. Figure 7.

Product Folder Links: LM3450

TEMPERATURE (°C)

VSEN-REF (mv)

205

203

201

199

197

195

-50 -14 22 58 94 130

TEMPERATURE (°C)

VVAC-REF (mv)

357.0

356.6

356.2

355.8

355.4

355.0

-50 -14 22 58 94 130

TEMPERATURE (°C)

VREF (V)

3.03

3.02

3.01

3.00

2.99

2.98

-50 -14 22 58 94 130

TEMPERATURE (°C)

VFB (V)

2.510

2.506

2.502

2.498

2.494

2.490

-50 -14 22 58 94 130

TEMPERATURE (°C)

VCC (V)

-50 -14 22 58 94 130

UVLO Rising

UVLO Falling

TEMPERATURE (°C)

IQ (#A)

580

560

540

520

500

480

-50 -14 22 58 94 130

LM3450

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SNVS681D –NOVEMBER 2010–REVISED MAY 2013

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

TA=+25°C and VCC = 14V unless otherwise specified

VCC UVLO Threshold vs. Junction Temperature Shutdown Current vs. Junction Temperature

Figure 8. Figure 9.

VREF Reference vs. Junction Temperature FB Reference vs. Junction Temperature

Figure 10. Figure 11.

ISEN Reference vs. Junction Temperature VAC Detection Threshold vs. Junction Temperature

Figure 12. Figure 13.

Product Folder Links: LM3450

0.0 0.2 0.4 0.6 0.8 1.0

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

DIM PIN DUTY CYCLE

DEMODULATED VAC PIN DUTY CYCLE

VADJ=3V

1.5V

0.5V

2.5V

VFB (V)

GM (Ps)

250

200

150

100

1.5 2.0 2.5 3.0 3.5

VCMP (V)

VCS (V)

4.90

3.92

2.94

1.96

0.98

0.00

1.0 1.8 2.6 3.4 4.2 5.0

VAC = 3V

VAC = 4V

VAC = 2V

VAC = 1V

VAC = 0.1V

VAC = 0.5V

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

TA=+25°C and VCC = 14V unless otherwise specified

Transconductance vs. VFB Current Sense Threshold vs. VCOMP and VAC

Figure 14. Figure 15.

Decoder Mapping from VAC to DIM

Figure 16.

Product Folder Links: LM3450

ANGLE

DEMOD

DIM

COMP

2.7V

2.5V

346mV

50 PA

1 PA

168mV

75 mV

FLT1

FLT2

500 k:

Low Power

VCCUV

GND

ZCD

HOLD

GATE

5 PA

5 k:

40 k:

LEB

1.5V

LOGIC

CONTROL

Over Voltage

Shutdown

Error Amp

Disable

PWM

Current Limit

Multiplier

1.5V

Zero Crossing

BIAS

VCCUV

14V

INTERNAL

REGULATORS

VCC UVLO

THERMAL

SHUTDOWN

10V

LEB

VCCUV

Sampled Hold

Transition

140 ns

Low Power

MAXIMUM

OFF-TIME

(340 Ps, 42 Ps)

1 k:

VCCUV

COMP

PRE-BIAS

Amplitude Adjust

Low Power Reset Off-Timer

Timer Expired

-Burst

1.4V

Burst

1.5V

SAMPLE and

LOG REMAP

DIN

DOUT

500 Hz Triangle

DIN

DOUT

VCC

ISEN

VREF

VAC

VADJ

LM3450A has

Continuous Hold

*LM3450 and LM3450A are identical except where indicated in blue

LM3450

www.ti.com

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

BLOCK DIAGRAM

Product Folder Links: LM3450

ZCD

GATE

LM3450/50A

GND

COMP

HOLD

DIM

FLT2

FLT1

PWM

TO OPTO

BIAS

RETURN

INPUT 24V

RZCD

RHLD

RBS

CVCC

QPS

COUT

VCC

ISEN

VREF

VADJ

VAC

CHLD CSEN

CCMP

CF1

CF2

CREF

CPFC

RAD2

RAD1

RF2

RF1

RAC2

RAC1

RFB1

RCS

RSEN

QSW

DSW

FLYBACK

OUTPUT

FEEDBACK

FROM OPTO

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

www.ti.com

Figure 17. Typical Flyback Application

THEORY OF OPERATION

The LM3450/50A is a single device with both power factor control (PFC) and phase dimming decoder functions.

This device is designed to control isolated flyback converters and provide active power factor correction. In

addition to being a PFC, the LM3450/50A can interpret a phase dimming (frequently called triac dimming) input

and provide a corresponding PWM output to properly dim an LED load. This combination of features provides an

excellent method to convert a standard AC mains input to a dimmable LED output of 10-100W. It should be

noted that the LM3450/50A can control a boost converter in a similar manner. However, this datasheet will focus

mostly on the flyback topology due to the high demand for isolated LED driver applications. Discussion of the

LM3450/50A functionality will refer to Figure 17 component designators.

The PFC control operates in critical conduction mode (CRM) using zero crossing detection (ZCD) to terminate

the off-time. The PFC portion of this device includes an error amplifier, multiplier, current sense circuit, zero

crossing detector, and gate driver. The internal error amplifier is used for feedback of the output voltage in non-

isolated designs. However, it can be disabled for isolated designs where the error amplifier needs to be on the

secondary side.

The phase dimmer decoder detects the dimming angle of the rectified AC line, decodes, filters and remaps it to a

500Hz PWM output. The PWM output can then be sent directly, or through optical isolation, to the dimming input

of a second stage LED driver. To ensure the decoder properly interprets the dimming angle, dynamic hold is

provided which prevents the phase dimmer from misfiring. The input current is sensed and when the current

drops below a preset minimum, the system adds more current.

Both the dynamic hold and the decoder are sampled synchronously in the LM3450 to reduce the overall

efficiency drop due to the additional hold current. When a decoding sample period occurs, the dynamic hold is

activated to ensure a proper angle is decoded. Because of this sampling method, non-sampled cycles will

potentially cause the phase dimmer to misfire but should not affect the output LED current regulation.

Product Folder Links: LM3450

DISPDIST KKPF x

PF=AVG

RMSRMS IV x

VREF +

Switching Regulator

VREF +

EMI Bridge Rectifier Energy

Storage

LM3450

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SNVS681D –NOVEMBER 2010–REVISED MAY 2013

For higher power applications, where the dynamic hold provides much less current on average, the LM3450A

can be used. The LM3450A has continuous dynamic hold which prevents the dimmer from ever misfiring. This is

extremely helpful when designing for single stage solutions, where there is no second stage to provide good line

rejection. The continuous dynamic hold is also helpful for the higher power two stage applications where the

input capacitance is larger.

One last feature of the phase decoder is a dynamic filter that, combined with the variable sampling rate, provides

fast, smooth dimming transitions.

Figure 18. PFC System Architecture

PFC BACKGROUND

Power factor (PF) is a number between 0 and 1 that indicates how well energy is transmitted from input to output

of a system. It can be described by average power (PAVG), RMS voltage (VRMS), and RMS current (IRMS):

(1)

Or by distortion factor (KDIST) and displacement factor (KDISP):

(2)

With a purely resistive system, PF = 1. The addition of reactive elements necessary in any converter, such as

EMI filters and energy storage, will induce some amount of displacement (phase shift between the input voltage

and input current). The addition of switching devices will also create distortion (energy present in the harmonics

relative to the switching frequencies). These non-idealities decrease the PF towards zero.

Active power factor correction attempts to make the input impedance look as resistive as possible to the power

source. Since the output of the converter is usually a regulated voltage or current, there is a need for large

energy storage elements to remove the twice line frequency (100Hz or 120Hz) ripple. A power factor control

architecture, as shown in Figure 18, has very little capacitance at the input. Instead, the twice line frequency

content is removed with large energy storage capacitance at the output.

Using this control architecture, the converter is able to provide two important functions at the same time:

• Shape the input current

• Regulate the output voltage

The PFC control approach requires two separate control loops to achieve both functions: a fast loop which

shapes the input current, and a slow loop that regulates the output voltage.

The fast control loop shapes the input current to have the same sinusoidal shape as the AC input voltage.

Assuming both are perfect sinusoids with zero distortion or phase shift, the power factor will be perfect (unity).

Unfortunately, distortion is always present in switching converters. An input filter, which is required to comply with

EMI standards, helps to attenuate the switching content, thereby reducing distortion. However, the added filter

capacitance will increase the phase shift at the same time. Though perfect PF is not achievable within real

applications, extremely high PF (>.99) is possible using most active PFCs.

Product Folder Links: LM3450

)2()

tDI PKP x

(tIin =

iL (t)

IL-MAX

tON = DTStOFF = (1-D)TS

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

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The output voltage has to be regulated slowly to ensure the converter ignores the twice line frequency ripple

present on the output. Therefore, the voltage loop containing the error amplifier should have a bandwidth at least

an order of magnitude slower (<20Hz is common). Sometimes the bandwidth is increased to improve transient

response, which is the case with off-line dimmable LED drivers. Though PF decreases with the increase in

bandwidth, high PF (>.95) is still possible.

Figure 19. Basic CRM Inductor Current Waveform

CRM BACKGROUND

During critical conduction mode (CRM), a converter operates at the boundary of continuous conduction mode

(CCM) and discontinuous conduction mode (DCM). This is usually implemented as follows. The main switching

MosFET (QSW) is turned on and the inductor current rises to a peak threshold. QSW is then turned off and the

current falls until it reaches zero. At this point, QSW is turned on and the cycle repeats. Near zero voltage

switching, enabled by the inductor current return to zero, gives CRM topologies an efficiency improvement

compared to CCM topologies. Figure 19 shows the resulting inductor current waveform, where the average

inductor current (IL) is half of the peak current (IL-MAX).

In a CRM flyback PFC application, the rectified AC input is fed forward to the control loop, creating a sinusoidal

primary peak current envelope (IP-pk) as shown in Figure 20. The secondary peak current envelope (IS-pk) will

simply be a scaled version of the primary according to the turns ratio of the transformer. Assuming good

attenuation of the switching ripple via the EMI filter, the average input current (IIN), represented by the red line in

Figure 20, can also be approximated as a sinusoid proportional to the duty cycle (D(t)):

(3)

Since CRM operation is hysteretic and the input voltage is fed-forward, the input current shaping loop is as fast

as possible. Only the output voltage needs to be regulated with a narrow bandwidth error amplifier, which greatly

simplifies the system dynamics.

Product Folder Links: LM3450

LOGIC

Rectified AC

ZCD

GATE

LM3450/50A

GND

COMP

VAC

2.7V

2.5V

346mV

50 P$

5 k:

1.5V

Error Amp

Disable

Multiplier

VOUT

(Non-

isolated)

1/3

OPTO

(Isolated)

RAC2

RAC1

RZCD

QSW

RCS

CCMP

RFB1

RFB2

168mV Shutdown

3V OVP

IIN-PK

IP-PK

IS-PK

tON TSW

LM3450

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SNVS681D –NOVEMBER 2010–REVISED MAY 2013

Figure 20. CRM Flyback Current Waveforms

Figure 21. PFC Control Circuit

Product Folder Links: LM3450

( ) OSTHMCOMPACMMLT VVVVKV +-

t=PKP

IL -

PKIN

V-

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

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POWER FACTOR CONTROLLER

The LM3450/50A uses CRM control to regulate the output voltage and provide power factor correction. In a non-

isolated boost topology, an external voltage divider (RFB1, RFB2) is used to sense the output voltage, as shown in

Figure 21. The divider is connected to the inverting input (FB) of the internal error amplifier. The LM3450/50A

regulates the feedback voltage (VFB) to 2.5V in a closed loop fashion.

The FB pin has a shutdown mode to protect against a feedback short and an OVP mode which terminates

switching when output over-voltage is sensed.

With the FB shutdown mode, it is necessary to have a preliminary biasing method for the output of the error

amplifier (COMP). Otherwise, the converter would never start. COMP is pre-biased with a 415µA current until the

voltage at COMP (VCMP) exceeds the minimum operational voltage (VTHM).

For an isolated flyback topology, where the error amplifier is on the secondary, the LM3450/50A internal error

amplifier can be bypassed using a single 5.11kΩresistor (RFB1) from FB to GND. This engages an internal 5kΩ

pull-up resistor at COMP. COMP can then be connected directly to the optical isolation as shown in Figure 21.

COMP and the sensed rectified AC input voltage (VAC), provided via a resistor divider (RAC1, RAC2), are inputs to

the multiplier. The current through the sense resistor (RCS) produces a voltage (VCS) that is compared to the

multiplier output. When VCS exceeds the multiplier output, QSW is turned off. The peak detect threshold and the

current slope during an on-time are proportionally changing which yields a nearly constant on-time, shown in

Figure 20:

(4)

Once QSW is turned off, the LM3450/50A waits until the inductor (boost) or transformer (flyback) is demagnetized

to turn QSW on again. Demagnetization, sensed at ZCD, occurs when the current through the magnetic

component falls to zero. Since the output voltage is regulated, the slope of the current remains relatively constant

and, coupled with the variable peak detect, creates a variable off-time.

The sinusoidal peak detection envelope creates an input current that is sinusoidal and in phase with the input

voltage providing excellent PF. The PWM comparator 30mV input offset voltage ensures current is drawn at the

zero-crossings of the AC line, reducing distortion and further improving PF.

CURRENT SENSE

The LM3450/50A senses current through QSW via a sense resistor (RCS) between the source of QSW and GND.

When VCS exceeds the output of the multiplier (VMLT), QSW is turned off. VMLT is variable over the line cycle and is

a function of the scaled rectified AC voltage (VAC), the COMP voltage referenced from its operational minimum

(VCOMP-VTHM), the multiplier gain (KM) and the PWM comparator offset (VOS):

(5)

The LM3450/50A has a leading edge blanking (LEB) circuit that pulls the current sense input to the PWM

comparator low for 140µs at the beginning of each on-time. The LEB blanks the current spike and associated

ringing due to the turn-on transient of QSW, limiting the minimum achievable duty cycle.

OVER CURRENT PROTECTION

The LM3450/50A has a current limit threshold (VLIM = 1.5V) at CS to protect the system from over-current

conditions. If VCS exceeds VLIM, QSW is immediately turned off until ZCD triggers a new on-time.

Product Folder Links: LM3450

()x=

SW tDf xPK-P

IL PKIN-

VSW

VRING

VZCD

1.3V

VIN

LM3450

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Figure 22. ZCD Waveforms for Flyback Design

ZERO CURRENT DETECTION

ZCD is implemented with a 100kΩresistor from the ZCD pin to a coupled winding on the transformer or inductor

as shown in Figure 21. This winding is also used to bootstrap VCC after start-up. When QSW turns off, the voltage

at the ZCD pin (VZCD) increases as energy is transferred through the auxiliary winding. The circuit arms when

VZCD exceeds 1.5V. Then, when the energy is fully transferred, VZCD decreases towards zero. When VZCD falls

below 1.3V, the transformer is assumed to be demagnetized, the circuit disarms, and QSW is turned back on as

shown in Figure 22. The ZCD pin voltage will remain low until QSW is turned off via peak detection and the cycle

repeats.

SWITCHING FREQUENCY

With a constant on-time and variable off-time, there is a variable switching frequency:

(6)

Figure 20 shows that the minimum switching frequency occurs at the peak of the rectified AC waveform, while

the maximum switching frequency occurs at the valley.

ERROR AMPLIFIER

The LM3450/50A internal error amplifier is used for non-isolated designs (boost) where the output voltage can be

directly sensed, via a resistor divider, at the FB pin. The FB pin is the inverting input of the trans-conductance

amplifier which is regulated to 2.5V. The COMP pin is the output of the amplifier and external compensation is

placed from COMP to GND in the form of a single capacitor (CCMP) as shown in Figure 21, a series resistor and

capacitor, or both. The output of the amplifier sources or sinks current as necessary to force the inputs of the

amplifier to be equal. The compensation method depends upon the transient performance desired and requires a

loop gain analysis. This analysis can be somewhat complex and cumbersome. A detailed analysis can be found

Application Notes AN-2098 (literature number SNVA463) and/or AN-2150 (literature number SNVA485).

Product Folder Links: LM3450

VOUT

VSB

LMV431

COMP

OPTO

LM3450/50A

RFB2

RFB1

RSC

CSC

RSBS

CCMP

SOFT

START

RFB

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

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If the COMP pin voltage (VCMP) falls below 1.4V at any time, the device enters burst mode where the GATE is off

for 340µs then is turned on. If VCMP is still below 1.4V at the end of the on-time then another 340µs off-time

occurs. However, if VCMP has risen above 1.4V, the converter continues switching until it falls below the threshold

again. This feature is necessary to prevent the output of the converter from rising arbitrarily high because the

minimum on-time of the device prevents less energy transfer.

The LM3450/50A also implements both feedback short circuit protection and output over-voltage protection

(OVP) functions at the FB pin. If VFB exceeds 3V, then OVP is engaged and the part stops switching until VFB

falls below 3V. In the same manner, if VFB falls below 168mV, then shutdown is engaged and switching stops

until VFB exceeds 188mV.

The flyback topology is frequently used to provide isolation from input to output. Since, the current transfer ratio

(CTR) of standard optical isolation varies over temperature, proper regulation using primary error amplifiers is

difficult. An error amplifier is usually placed in the secondary to regulate the output voltage accurately. To

accommodate isolated designs, the LM3450/50A internal error amplifier can be bypassed by placing a 5.11kΩ

resistor from FB to GND. This engages a 5kΩpull-up resistor from COMP to an internal 5V rail.

SECONDARY ERROR AMPLIFIER

For isolated designs, the error amplifier on the secondary should take the form of a proportional integral (PI)

compensator. The amplifier is frequently implemented with an LMV431. The output voltage resistor divider (RFB1,

RFB2) provides the sensed output voltage to the LMV431 inverting input. The PI compensation is achieved by

connecting RSC and CSC in between the LMV431 input and output, shown in Figure 23. In addition, CCMP is

placed from COMP to GND on the primary for higher frequency noise attenuation.

In addition to the basic error amplifier, a soft-start circuit can be implemented using a capacitor, two diodes and a

Zener diode as shown in Figure 23. This secondary softstart circuit has no restart mechanism, therefore a

primary side softstart is recommended as described in the SOFTSTART section of this document.

Figure 23. Secondary Error Amplifier

PRECISION VOLTAGE REFERENCE

The LM3450/50A provides a 3V voltage reference (VREF) for biasing the VADJ pin as well as any external circuitry.

VREF is regulated once VCC exceeds 3V. There is a 2mA current limit for the reference. A 10nF ceramic bypass

capacitor should be placed from VREF to GND.

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DELAY

(a)

(b)

(c)



LM3450

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LOW POWER SHUTDOWN

The LM3450/50A can be placed into a low power shutdown by grounding the VADJ pin (any voltage below 75mV).

During low power shutdown, the device will turn on the GATE for one cycle followed by a fixed off-time of 42µs

and the cycle repeats. During shutdown, the DIM output will be high (zero light output) since the buffer rail at

FLT1 will be at or near zero. This feature is designed to hold up the PFC output voltage while removing the load

(turning the LEDs off).

THERMAL SHUTDOWN

Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction

temperature is exceeded. The threshold for thermal shutdown is 160°C with a 20°C hysteresis. During thermal

shutdown GATE is disabled.

Figure 24. Phase Dimming Waveforms

Product Folder Links: LM3450

BRIGHT

DIM

R1MAX  250 k:

DIAC

R2  3.3 k:

C1  100 nF

LOAD

MAINS

TRIAC

FORWARD PHASE DIMMER

LM3450

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PHASE DIMMER OPERATION

A simplified schematic of a phase dimmer is shown in Figure 25. An RC network consisting of R1, R2, and C1

delay the turn-on of the triac until the voltage on C1 reaches the trigger voltage of the diac. Increasing the

resistance of the potentiometer (wiper moving downward) increases the turn-on delay which decreases the on-

time or “conduction angle” of the triac (θ). This reduces the average power delivered to the load.

Figure 25. Basic Forward Phase Dimmer

Phase dimmer voltage waveforms are shown in Figure 24.

Figure 24a shows the full sinusoid of the input voltage. Even when set to full brightness; few dimmers will provide

100% conduction angle.

Figure 24b shows a waveform from a forward phase dimmer. The off-time can be referred to as the firing angle

and is simply 180° – θ.

Figure 24c shows the waveform of a reverse phase dimmer (also called an electronic dimmer in the lighting

industry). These typically or more expensive, microcontroller based dimmers that use switching devices other

than triacs. Note that the conduction angle starts from the zero-crossing, and terminates some time later. This

method of control reduces the noise spike at the transition.

Any form of phase dimming modulates the incoming AC waveform by chopping part of the sinusoid, reducing the

average power to the load. These dimmers work very well with standard incandescent bulbs, but not with power

converters. A converter attempts to regulate the load in with presence of any input, effectively ignoring the phase

angle. To implement a dimmable converter, the angle must be sensed at the input, decoded and used to properly

control the LED current regulator.

Product Folder Links: LM3450



356 mV

VAC

DIN

OPTO

0-3V

Analog

Input

VCC

VSB

PWM OUT

Rectified AC

RF1 RF2

CF1 CF2

RPB

RSB

RAC2

RAC1

-DIM

VAC

500k

Transition

LM3450/50A

ANGLE

DEMOD

SAMPLE / REMAP

DIN

DOUT

DIN DOUT

FLT2

FLT1

VADJ

VREF

REF

500 Hz

LM3450

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SNVS681D –NOVEMBER 2010–REVISED MAY 2013

Figure 26. Dimming Decoder Circuit

PHASE DIMMING DECODER

The LM3450/50A uses the rectified AC line voltage to interpret the conduction angle. Figure 26 shows the

LM3450/50A decoder circuit with associated external circuitry. The rectified AC line voltage is scaled via a

resistor divider (RAC1, RAC2) and connected to the VAC pin. VAC is compared to a 356mV reference to generate a

twice line frequency PWM signal with corresponding duty cycle as shown in Figure 27.

Figure 27. Phase Angle Demodulation

For best results, RAC1 and RAC2 are suggested to be sized so that the VAC voltage crosses the 356mV threshold

when the rectified AC line is as follows:

• 120V systems: 25V to 45V

• 230V systems: 40V to 70V

The demodulated duty cycle is sampled and logarithmically remapped to a 300Hz PWM signal improving the

resolution of low dimming levels to the human eye. A minimum duty cycle limits the maximum achievable

contrast ratio to approximately 70:1. The remapped PWM signal is buffered and output at FLT1 with amplitude

equal to VADJ as shown in Figure 28.

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VFLT2

VDIM

VADJ

VFLT2

VFLT1

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Figure 28. FLT1 to FLT2 Mapping

The FLT1 signal is routed through a 2 pole low pass filter (RF1, CF1, RF2, CF2), as shown in Figure 26, to remove

the twice line frequency ripple. The resulting analog signal at FLT2 is compared to a 500Hz Triangle wave to

create the inverted PWM signal at the DIM pin as shown in Figure 29:

Figure 29. FLT2 to DIM Mapping

This PWM signal at the DIM pin can be used as the dim input to a secondary LED driver. DIM is an open drain

output designed for isolated solutions. Optical isolation is used to transmit signals across the isolation boundary.

With most opto-isolators, the edge rate is dependent on the amount of drive current through the photodiode. The

open-drain configuration allows the primary bias supply (VCC) to provide the current as shown in Figure 26. The

choice of resistor (RPB) between VCC and the photodiode anode will set the drive current. This enables the user

to trade-off PWM accuracy with system efficiency.

The open drain configuration also ensures that the secondary has a resistor from the phototransistor’s emitter to

secondary ground (not from collector to secondary bias). During system turn-off, this prevents an undesired LED

blink because the secondary stage LED driver is forced off.

A variable sample rate and dynamic filter ensure fast, smooth dimming transitions (movement of the dimmer)

while maintaining robust flicker-free behavior when the dimmer is static. The sample rate depends on past and

present angle information. The dynamic filter is a dual mode filter. During standby mode, when a transition has

not been made and the dimmer is static, a 500kΩseries resistor is connected between the buffered output and

FLT1 as shown in Figure 26.

The 500kΩresistor is shorted when the LM3450/50A senses a large transition of the dimmer. This increases the

filter speed while the dimmer is transitioning between levels to improve response time.

The FLT1 and FLT2 poles created by each RC pair (RF1 and CF1, RF2 and CF2) should be set as follows:

• CF1 and CF2 can be 1µF ceramic capacitors for all designs.

• RF1 and RF2 should be set between 15kΩ(~10Hz) and 75kΩ(~2Hz).

2 Hz poles provide a “smooth fade” while 10Hz poles create a “snappy” response.

These component values ensure that the static filter condition in standby mode has 1 pole approximately a

decade lower than the nominal in order to provide good noise immunity to the system.

Product Folder Links: LM3450

GND

5 P$

40 k:

Rectified AC

BIAS

AC AC

LM3450/50A

Sample

CHLD

CSEN

RSEN

RHLD

QPS

RBS

VSEN

ISEN

HOLD

10k

NTC

15k

3904

Connect if thermal

protection circuit is

not desired

QPS

thermal

protection

circuit

0.0 0.2 0.4 0.6 0.8 1.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

DIM PIN DUTY CYCLE (INVERTED)

LM3450/A DEMODULATED VAC PIN DUTY CYCLE

0.5V

2.5V

1.5V

VADJ=3V

LM3450

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Figure 30. Complete Decoder Mapping

Since the buffered decoder output has amplitude equal to VADJ and the resulting PWM signal is filtered into an

analog voltage at FLT2, the VADJ pin can be used to change the mapping as shown in Figure 30. The maximum

LED current (DIM = 0) when VADJ = 3V corresponds to decoded angles of 70% or greater. Some dimmers have a

maximum angle greater than this. If VADJ is reduced to 2.5V, the maximum LED current will correspond to an

angle of 80% and at VADJ = 2V the maximum will occur at a decoded angle of 95%.

The VADJ pin can also be used to implement a standard analog adjust function. If the demodulated phase angle

at VAC is above 85%, then the fast filter is always enabled (500kΩshorted) and the VADJ pin can solely be used

to scale the DIM pin duty cycle. When VADJ is pulled below 75mV the part enters low power shutdown so the

maximum attainable contrast ratio using VADJ only is approximately 40:1.

Both FLT1 and FLT2 have pull-down MosFETs that are turned on when VCC UVLO falling threshold is triggered.

This provides a quick discharge path for the capacitors and eliminates the possibility of an undesired light level at

the next startup.

Figure 31. Dynamic Hold Circuit

Product Folder Links: LM3450

1

IIN-MIN-REG Added

Hold

Current

~VCC

VHOLD

IIN

2

Misfire

1

356 mV

Misfire

2

Original

Angle

VAC

DIN

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

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DYNAMIC HOLD

A forward phase “triac” dimmer requires a minimum amount of current to be flowing through it during the entire

conduction angle. This is referred to as hold current. If the minimum hold current requirement is not met, the triac

will shut off (misfire). During normal operation, the converter will demand some amount of input current.

However, at any point during the cycle, the input current can be low enough to cause a misfire.

During an LM3450/50A sampling period, the triac should not misfire or the decoded angle will be inaccurate as

shown in Figure 32. Since the triac is asymmetrical phase-to-phase, misfires can occur at different points in the

waveform. After the triac misfires, the voltage returns to zero exponentially. This can create a large difference

between decoded angles which can be observed as a “fluttering” of the light.

Figure 32. Forward Phase Waveform

To ensure the triac does not misfire during a sampling period and the angle is correctly decoded, a dynamic hold

function is enabled. The input current is sensed with a resistor (RSEN) from GND to ISEN (the return of the full

bridge rectifier). If the voltage across this resistor is less than 200mV, the device adds holding current via the

HOLD circuitry to maintain 200mV across RSEN.

The hold current is added by linearly adjusting the gate voltage of QHLD as shown in Figure 31. As the gate

voltage of QHLD is increased, the HOLD pin voltage decreases, forcing a voltage across the resistance (RHLD)

from the source of QPS to HOLD. This extra current is drawn from the input through the triac, but is not

processed by the converter. Figure 33 shows a typical dynamic hold waveform of the LM3450 where interval 1 is

a non-sampled conduction angle, 2 is the firing angle, and 3 is a sampled conduction angle. It should be noted

that using the LM3450A will ensure every conduction angle looks like interval 3 in Figure 33.

Figure 33. Dynamic Hold Waveform

Product Folder Links: LM3450

=I MAX-HOLD VCC

+30

RHLD

REGMIN-IN-

I=mV200

SEN

1

356 mV

Turn-off

no bleeder

2

Turn-off

with bleeder

VAC

DIN

LM3450

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SNVS681D –NOVEMBER 2010–REVISED MAY 2013

The dynamic hold function is also necessary for reverse phase dimmers, but for a different reason. Reverse

phase dimmers do not use triacs, therefore they do not require a minimum “holding” current. Instead, they need

what is commonly called bleeder current. When a reverse phase dimmer turns off, the AC voltage is at a high

value. There is an RC time constant associated with discharging the total effective input capacitance (EMI

capacitors, PFC capacitor, damper capacitance). The decoder does not record the angle until the voltage

reaches the 356mV threshold. This can cause the decoded angle to be much larger than it actually is and

dependent on the RC time constant as shown in Figure 34.

Figure 34. Reverse Phase Waveforms

The dynamic hold will quickly bleed off the excess charge in an attempt to regulate the voltage across RSEN. This

will preserve the accuracy of the decoded phase angle.

During the conduction angle (θ), dynamic hold is enabled only during a sample period for the LM3450. However,

during the firing angle (delay time), dynamic hold is always enabled with the LM3450. This will ensure the

rectified line voltage does not begin to rise due to leakage currents through the phase dimmer. Again, with the

LM3450A the dynamic hold is continuously active during all conduction and firing angles.

The minimum regulated input current can be calculated:

(7)

The maximum possible additional holding current (which can occur when HOLD is still transitioning usually at the

rising edge of the triac firing) can be approximated:

(8)

It is recommended that the maximum hold current is set 10-15% higher than the minimum regulated input

current.

A minimum of 0.1µF capacitance should be placed between ISEN and HOLD to limit the bandwidth of the dynamic

hold circuit to well below the switching frequency. However, if too large a capacitor is used, the bandwidth will be

too low to respond to line transients. A maximum of 0.47µF should ensure good performance.

Finally, a small Schottky diode should be placed from GND to ISEN to absorb the large current spikes associated

with the triac firing edge. This diode should have a forward voltage above 200mV at the worst-case operating

temperature so that it won’t interfere with dynamic hold regulation.

Product Folder Links: LM3450

Rectified AC

BIAS

LM3450/50A

VCCUV

14V

VCC

RETURN

VCC UVLO

24V

CVCC

QPS

RBS

QSW

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THERMAL PROTECTION

With the LM3450A, QPS has to dissipate more power than with the LM3450. During worst case conditions such

as open LED load, the converter will be demanding very little current regardless of the triac position. If the phase

dimmer conduction angle is large and the load is not present, QPS has to dissipate many watts since the dynamic

hold is attempting to regulate the current to ten's of mA. Using the LM3450, this is nominally not a problem since

it is sampling the dynamic hold infrequently. However, the LM3450A is drawing the hold current every cycle

which becomes a problem very quickly. It should be noted that If the input AC line is very noisy, the VAC input to

the decoder could have enough variation in steady state to cause the decoder to think the dimmer is transitioning

all of the time. This would increase the sampling rate dramatically, putting much more thermal strain on the

passFET in LM3450 applications as well.

To mitigate these problems, a thermal protection circuit should be implemented on the LM3450A designs (and

can be on the LM3450 designs as well) as shown in red in Figure 31. The NTC thermistor should be placed on

the opposite side of the PCB directly under the drain of QPS. This will provide the best thermal coupling while

maintaining the necessary high voltage spacing constraints. At startup the NTC is at a high resistance value,

turning the PNP fully on which provides the dynamic hold path. As the NTC heats up the resistance decreases

and the base voltage increases. Eventually, the PNP will transition into linear mode and the effective resistance

from collector to emitter will increase. This will decrease the maximum holding current, thereby decreasing the

thermal stress on QPS. Given enough headroom, the circuit should reach thermal equilibrium in a safe controlled

manner.

Since this method of thermal protection linearly reduces the maximum hold current with increasing temperature,

the foldback will not be perceptible to the consumer. Instead, the result of the foldback will simply be a reduction

of contrast ratio, meaning the minimum achievable LED current will increase as the temperature increases

beyond the foldback level.

Figure 35. Primary Bias Circuitry

PRIMARY BIAS SUPPLY

The LM3450/50A requires a supply voltage at VCC, not to exceed 25V. The device has VCC under-voltage lockout

(UVLO) with rising and falling thresholds of 12.9V and 7.9V respectively. A 24V Zener diode should be placed

from the VCC pin to GND to protect the device from substantial spikes that could cause damage.

Product Folder Links: LM3450

18V

3.9V

500k

47uF

20k

COMP

LM3450/50A

BIAS VADJ VCC

LM3450

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SNVS681D –NOVEMBER 2010–REVISED MAY 2013

Figure 35 shows how the LM3450/50A provides a quick way to generate the necessary primary bias supply at

start-up. Since the AC line peak voltage is always higher than the rating of the controller, all designs require an

N-channel MosFET (passFET). The passFET (QPS) is connected with its drain attached to the rectified AC. The

gate of QPS is connected to the BIAS pin which has a stack of 2 Zener diodes internal to the device. These

diodes are then biased from the rectified AC line through series resistance (RBS). The source of QPS is held at a

VGS below the Zener voltage and current flows through QPS to charge up whatever capacitance is present. If the

capacitance is large enough, the source voltage will remain relatively constant over the line cycle and this

becomes the input bias supply at VCC.

This bias circuit enables instant turn-on. However, once the circuit is operational it is desirable to bootstrap VCC

to an auxiliary winding of the inductor or transformer (also used for ZCD). The two bias paths are each

connected to VCC through a diode to ensure the higher of the two is providing VCC current. This bootstrapping

greatly improves efficiency when quick start-up is necessary.

To ensure that the auxiliary winding is powering VCC at all times except start-up, the LM3450/50A has a dual

BIAS mode. The BIAS voltage at startup is 20V through two Zener diodes. When the VCC UVLO rising threshold

is exceeded and the device turns on, the BIAS pin voltage is reduced to 14V (bottom 6V Zener is shorted). Once

the VCC UVLO falling threshold is reached again, the BIAS pin will return to 20V to attempt to restart the device.

It should be noted that the large hysteresis of VCC UVLO and the dual BIAS mode allow for a large variation of

the auxiliary bias circuitry easing the design of the magnetics.

SOFTSTART

As in any off-line system, softstart is an important part of the design. Since the LM3450/50A are used with phase

dimming applications, the typical startup problems are magnified since a phase dimmer is frequently turned on

and off rapidly. This requires a softstart mechanism that quickly resets when the LM3450/50A turns off. Since the

LM3450/50A has two distinct functional parts (PFC and phase decoder), ideally both should be softstarted

simultaneously. This will ensure the most controlled start-up possible.

The circuit in Figure 36 provides this exact functionality. Both VADJ and COMP are diode or'ed into an RC

charging circuit fed from VCC. The reset mechanism is accomplished using an 18V Zener from BIAS, a current

limiting resistor and an NPN transistor. The reset is activated when VCC uvlo falling is triggered and BIAS

transitions to 20V. This discharges the RC to zero and as soon as VCC uvlo rising is passed BIAS transitions to

14V again, releasing the clamp on the RC softstart circuit. The RC will charge up to the 3.9V Zener clamp (which

is above the dynamic range of COMP and VADJ and become effectively out of the circuit until the next turn-off.

Figure 36. Dual Softstart Circuit

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DESIGN INFORMATION

HOW TO SELECT THE CORRECT DEVICE (LM3450 or LM3450A)

What application(s) are suitable for the LM3450, and when is the LM3450A appropriate? The difference centers

on the power dissipation in the passFET. The passFET stands off the high AC voltage from the LM3450/50A,

and provides a path for the hold current. The passFET operates in the linear region and dissipates power equal

to the product of the voltage across it and the current through it.

The LM3450 was designed to minimize the power dissipation in the passFET by applying holding current in a

sampled form. The standby sampling rate (when the dimmer is not moving) is infrequent, allowing minimal impact

on the thermal considerations of the passFET. Sampling of the dynamic hold is not desired for some applications

although. An example where the sampled hold current may cause undesirable effects is the single stage flyback

topology where the output of the flyback is directly connected to the LEDs. If the phase dimmer is allowed to

misfire or create erratic differences in the input voltage and current waveforms, this behavior will appear as a

"fluttering" of the LED light output at the sampling rate when the single stage topology is used. The light flutter is

most observable at low input currents (dimming). A small perturbation in the input voltage due to phase dimmer

misfire can create a visible difference in the output light. Using a secondary LED driver stage eliminates this

problem.

Cost sensitive applications may drive the design to a single stage solution, and the LM3450A was developed to

address this market. The LM3450A provides continuous dynamic hold current on every AC cycle preventing the

phase dimmer from misfire, and the sampling frequency from appearing at the output. Another design

consideration where continuous dynamic hold may be advantageous is the reduced stresses on input EMI R/C

snubber networks.

The designer must pay close attention to the power loss of the passFET when using the LM3450A. Designers

must consider worst case possibilities with any power conversion designs. Worst case operating conditions with

the LM3450A are usually found with the largest triac holding current requirements. Many phase dimmers require

25mA-40mA of holding current, and frequently designers are choosing 50mA as their minimum holding current

requirement. The passFET package for common LM3450/50A designs should be capable of dissipating between

1W and 1.5W. The pass-FET can always be increased in size and/or the hold current can be reduced. Power

calculations for the dynamic hold circuit as well as effective thermal protection are both described in the

DYNAMIC HOLD section.

The LM3450 and LM3450A is best differentiated in terms of the appropriate applications for each device. The

Table 1 can be used as a general guide for when to use each part.

Table 1. Device Selection Guide

Product AC Input Output Power Device Topology

POUT < 15W LM3450

120V POUT > 15W LM3450A

High End Downlight Two Stage Design

POUT < 25W LM3450

230V POUT > 25W LM3450A

Low Cost Downlight 120V POUT > 15W

or LM3450A Single Stage Design

230V POUT > 25W

Large High End Bulb

Product Folder Links: LM3450

ZCD

GATE

LM3450

VCC

GND

COMP

HOLD

VAC

VADJ

DIM

FLT2

FLT1

ISEN

PWM

VREF BIAS

IADJ

CSN

LM3409HV

UVLO

VCC

COFF

GND

CSP

PGATE

DAP

VIN

VOUT

PWM

VOP1

VOP2

RETURN

VLED

LMV431

OPTO1

OPTO2

VOP2

VOP1

VCC

VOUT

EMI

FILTER

CONTROL

FEEDBACK

SECONDARY

LED DRIVER

DIMMING

VREF +

MAINS

LED

LOAD

D3 D5

C9 D8

C10

C12

C13

C14 C15

C16

R1 R2

R11

R12

R13

R14

R15

R16

R17 R18

R19

R20

R21

R22

R23

R24

R25

C17

C18

C19 C21

C22

C20

D16

D13

D14

D15

D11D12

Q5 L4

R28

HOLD

VLED

R27

D10

C11

VCC

VADJ

COMPBIAS

D18

D17

R10

SOFTSTART

AUX

LM3450

www.ti.com

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

Applications Information

See AN-2098 (literature number SNVA463) and/or AN-2150 (literature number SNVA485) for detailed design and

application information.

TWO STAGE LED DRIVER – LM3450 PRIMARY AND LM3409HV SECONDARY

Product Folder Links: LM3450

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

www.ti.com

15W TWO STAGE DESIGN SPECIFICATIONS

AC Input Voltage: 120VAC nominal (90VAC - 135VAC) or 230VAC nominal (180VAC - 265VAC)

Regulated Flyback Output Voltage: 50V

Regulated LED Current: 350mA

LED Stack Voltage Maximum: 45V

Table 2. Bill of Materials(1)

Reference Designator Description Manufacturer Part Number

LM3450 IC PFC CONT 16-TSSOP TI LM3450MT

LM3409HV IC LED DRIVR 10-eMSOP TI LM3409HVMY

LMV431 IC SHUNT REG SOT-23 TI LMV431AIM5

C1a, C1b, C5a, 120V CAP CER 0.22µF 250V 1210 MURATA GRM32DR72E224KW01L

C5b 230V CAP CER 68nF 250V 1210 MURATA GRM32QR72E683KW01L

C2 CAP MPY 33nF 250VAC X1 RAD EPCOS B32912A3333M

C3 CAP CER 47µF 6.3V 0805 TAIYO YUDEN JMK212BJ476MG-T

C4 120V CAP MPY 0.1µF 400V RAD EPCOS B32612A4104J008

230V CAP MPY 33nF 1000V RAD WIMA MKP10 - .033/1000/10

C6 CAP CER 4.7nF 500VAC Y1 RAD EPCOS VY1472M63Y5UQ63V0

C7a CAP ELEC 470µF 63V RAD NICHICON UPW1J471MHD3

C7b, C8b, C9b, C11, C15 CAP CER 0.1µF 50V 1206 MURATA GRM188R71H104KA93D

C8a, C9a CAP ELEC 100µF 50V RAD NICHICON UHE1H101MPD

C10 CAP CER 10nF 25V 0603 MURATA GRM188R71E103KA01D

C12, C13 C14, C21 CAP CER 1µF 16V 0603 MURATA GRM188R71C105KA12D

C16 CAP CER 0.22µF 16V 0603 TDK C1608X7R1C224K

C17 CAP CER 10µF 16V 1206 MURATA GRM31CR71C106KAC7L

C18, C20 CAP CER 1µF 100V 1206 TDK C3216X7R2A105M

C19 CAP CER 2.2µF 6.3V 0603 TDK C1608X5R0J225M

C22 CAP CER 470pF 100V 0603 TDK C1608C0G2A471J

D1 120V DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D

230V DIODE FAST 400V 1A DO-214AC FAIRCHILD ES1G

D2 DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D

D3, D5 DIODE ULTRAFAST 100V 0.2A SOT-23 FAIRCHILD MMBD914

D4 DIODE DUAL SCHOTTKY 20V 0.5A SOT-23 NXP SEMI PMEG3005CT,215

D6 120V DIODE TVS 150V 600W UNI SMB LITTLEFUSE SMBJ150A

230V DIODE TVS 220V 600W UNI SMB LITTLEFUSE SMBJ220A

D7 DIODE ULTRAFAST 600V 1A SMA FAIRCHILD ES1J

D8 DIODE ZENER 24V 1.5W SMA MICRO-SEMI SMAJ5934B-TP

D9 DIODE SCHOTTKY 20V 3A SMA FAIRCHILD ES2AA-13-F

D10 DIODE RECT 600V 0.5A Minidip COMCHIP HD06

D11, D12 DIODE ZENER 10V 500mW SOD-123 FAIRCHILD MMSZ5240B

D13 DIODE ULTRAFAST 70V 0.2A SOT-23 FAIRCHILD BAV99

D14 DIODE ZENER 3.3V 500mW SOD-123 ON-SEMI MMSZ3V3T1G

D15 DIODE ZENER 1.8V 500MW SOD-123 ON-SEMI MMSZ4678T1G

D16 DIODE SCHOTTKY 60V 2A SMB ON-SEMI SS26T3G

D17 DIODE ZENER 3.9V 500MW SOD-123 ON-SEMI MMSZ4686T1G

D18 DIODE ZENER 18V 500MW SOD-123 ON-SEMI MMSZ5248T1G

L1, L2, L3 IND SHIELD 1mH 0.46A SMT COILCRAFT MSS1038-105KL

(1) Components are used in both versions unless otherwise noted

Product Folder Links: LM3450

LM3450

www.ti.com

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

Table 2. Bill of Materials(1) (continued)

Reference Designator Description Manufacturer Part Number

L4 IND SHIELD 470µH 1.06A SMT COILCRAFT MSS1278-474KLB

Q1 MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4

Q2 120V MOSFET N-CH 600V 4.4A DPAK INFINEON IPD60R950C6

230V MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4

Q3, Q4 TRANS NPN 40V 0.6A SOT-23 FAIRCHILD MMBT4401

Q5 MOSFET P-CH 70V 5.7A DPAK ZETEX ZXMP7A17K

Q6 TRANS PNP 40V 0.2A SOT-23 FAIRCHILD MMBT3904

R1 120V RES 330Ω5% 1W 2512 VISHAY CRCW2512330RJNEG

230V RES 510Ω5% 1W 2512 VISHAY CRCW2512510RJNEG

R2 120V RES 430Ω5% 1W 2512 VISHAY CRCW2512430RJNEG

230V RES 1.6kΩ5% 1W 2512 VISHAY CRCW25121K60JNEG

R3 120V RES 402kΩ1% 0.25W 1206 VISHAY CRCW1206402KFKEA

230V RES 953kΩ1% 0.25W 1206 VISHAY CRCW1206953KFKEA

R4 RES 100Ω1% 1W 2512 VISHAY WSL2512100RFKEA

R5 RES 100kΩ1% 0.1W 0603 VISHAY CRCW0603100KFKEA

R6 RES 6.04kΩ1% 0.1W 0603 VISHAY CRCW06036K04FKEA

R7 RES 499kΩ1% 0.1W 0603 VISHAY CRCW0603499KFKEA

R8, R9 RES 75.0kΩ1% 0.1W 0603 VISHAY CRCW060375K0FKEA

R10 RES 20.0kΩ1% 0.1W 0603 VISHAY CRCW060320K0FKEA

R11 120V RES 1.00MΩ1% 0.25W 1206 VISHAY CRCW12061M00FKEA

230V RES 2.00MΩ1% 0.25W 1206 VISHAY CRCW12062M00FKEA

R12 RES 15.0kΩ1% 0.1W 0603 VISHAY CRCW060315K0FKEA

R13 RES 5.11kΩ1% 0.1W 0603 VISHAY CRCW06035K11FKEA

R14a RES 10Ω1% 0.25W 1206 VISHAY CRCW120610R0FKEA

R14b RES 1.00Ω1% 0.33W 1210 VISHAY CRCW12101R00FNEA

R15a, R15b RES 5.62Ω1% 0.25W 1206 VISHAY CRCW12065R62FNEA

R16 RES 2.00kΩ1% 0.125W 0805 VISHAY CRCW08052K00FKEA

R17 120V RES 20.0kΩ1% 0.1W 0603 VISHAY CRCW060320K0FKEA

230V RES 10.0kΩ1% 0.1W 0603 VISHAY CRCW060310K0FKEA

R18 RES 105kΩ1% 0.125W 0805 VISHAY CRCW0805105KFKEA

R19 RES 2.67kΩ1% 0.1W 0603 VISHAY CRCW06032K67FKEA

R20 RES 6.04kΩ1% 0.125W 0805 VISHAY CRCW08056K04FKEA

R21 RES 10.0kΩ1% 0.125W 0805 VISHAY CRCW080510K0FKEA

R22 RES 80.6kΩ1% 0.1W 0603 VISHAY CRCW060380K6FKEA

R23 RES .62Ω1% 0.5 2010 SMD ROHM MCR50JZHFLR620

R24, R25 RES 10kΩ1% 0.1W 0603 VISHAY CRCW060310K0FKEA

R27, R28 120V RES 10Ω10% 2W FILM WELWYN EMC2-10R0

230V RES 22Ω10% 2W FILM WELWYN EMC2-22R0

OPTO1, OPTO2 OPTO-ISOLATOR SMD LITE ON CNY17F-3S

T1 120V XFORMER 120V 15W OUTPUT 50V WURTH 750813550

230V XFORMER 230V 15W OUTPUT 50V WURTH 750817550

Product Folder Links: LM3450

ZCD

GATE

LM3450A

VCC

GND

COMP

HOLD

VAC

VADJ

DIM

FLT2

FLT1

ISEN

PWM

VREF BIAS

VOP1

VOP2

RETURN

VOP1

VOUT

EMI

FILTER

VREF +

MAINS

D3 D5

C9 D8

C10

C12

C13

C14 C15

C16

R1 R2

R11

R12

R13

R14

R15

R24

R25

D11D12

R28

HOLD

R27

D10

C11

VCC

VADJ

COMPBIAS

D18

D17

R10

SOFTSTART

AUX

R18

R19

R20

R21 C18

D13

PWM

VOUT

OPTO1 OPTO2

VOP2

VOP1 VCC

CONTROL

FEEDBACK DIMMING

LED

LOAD

VSDIM

R17

C17

R16

VSDIM C19

R23

R22

R30 R29

R32

1.24V

Thermal

Protect

R26

1.24V

LMV431

D19

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

www.ti.com

SINGLE STAGE LED DRIVER – LM3450A FLYBACK

Product Folder Links: LM3450

LM3450

www.ti.com

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

30W SINGLE STAGE DESIGN SPECIFICATIONS

AC Input Voltage: 120VAC nominal (90VAC - 135VAC) or 230VAC nominal (180VAC - 265VAC)

Flyback Output Voltage Maximum: 60V

Regulated LED Current: 700mA

Table 3. Bill of Materials(1)

Reference Designator Description Manufacturer Part Number

LM3450A IC PFC CONT 16-TSSOP TI LM3450AMT

LMV431 IC SHUNT REG SOT-23 TI LMV431AIM5

U1 IC DUAL OP-AMP TI LM2904

C1a, C1b, C1c, 120V CAP CER 0.22µF 250V 1210 MURATA GRM32DR72E224KW01L

C5a, C5b, C5c 230V CAP CER 68nF 250V 1210 MURATA GRM32QR72E683KW01L

C2 CAP MPY 33nF 250VAC X1 RAD EPCOS B32912A3333M

C3 CAP CER 47µF 6.3V 0805 TAIYO YUDEN JMK212BJ476MG-T

C4 120V CAP MPY 0.22µF 400V RAD WIMA MKP10-.22/400/20

230V CAP MPY 62nF 1000V RAD VISHAY BFC238330623

C6 CAP CER 4.7nF 500VAC Y1 RAD EPCOS VY1472M63Y5UQ63V0

C7a CAP ELEC 1mF 63V RAD NICHICON UPW1J102MHD

C7b, C8b, C9b, C11, C15 CAP CER 0.1µF 50V 1206 MURATA GRM188R71H104KA93D

C8a, C9a CAP ELEC 220µF 50V RAD NICHICON UHE1H221MPD

C10 CAP CER 10nF 25V 0603 MURATA GRM188R71E103KA01D

C12, C13, C14, C18, C19 CAP CER 1µF 16V 0603 MURATA GRM188R71C105KA12D

C16 CAP CER 0.22µF 16V 0603 TDK C1608X7R1C224K

C17 CAP CER 10µF 16V 1206 MURATA GRM31CR71C106KAC7L

D1a, D1b 120V DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D

230V DIODE FAST 400V 1A DO-214AC FAIRCHILD ES1G

D2 DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D

D3, D5 DIODE ULTRAFAST 100V 0.2A SOT-23 FAIRCHILD MMBD914

D4 DIODE DUAL SCHOTTKY 20V 0.5A SOT-23 NXP SEMI PMEG3005CT,215

D6 120V DIODE TVS 150V 600W UNI SMB LITTLEFUSE SMBJ150A

230V DIODE TVS 220V 600W UNI SMB LITTLEFUSE SMBJ220A

D7 DIODE ULTRAFAST 600V 1A SMA FAIRCHILD ES1J

D8 DIODE ZENER 24V 1.5W SMA MICRO-SEMI SMAJ5934B-TP

D9 DIODE SCHOTTKY 20V 3A SMA FAIRCHILD ES2AA-13-F

D10 DIODE RECT 600V 0.5A Minidip COMCHIP HD06

D11, D12 DIODE ZENER 10V 500mW SOD-123 FAIRCHILD MMSZ5240B

D13 DIODE ZENER 1.8V 500MW SOD-123 ON-SEMI MMSZ4678T1G

D17 DIODE ZENER 3.9V 500MW SOD-123 ON-SEMI MMSZ4686T1G

D18 DIODE ZENER 18V 500MW SOD-123 ON-SEMI MMSZ5248T1G

D19 DIODE SCHOTTKY 30V 200mA SOT-23 FAIRCHILD BAT54

L1 IND LINE FILTER 6mH 0.3A 11M PANASONIC ELF-11M030E

L1, L2, L3 IND SHIELD 1mH 1.18A SMT COILCRAFT MSS1278-105KL

L4 IND SHIELD 270µH 2.34A SMT COILCRAFT MSS1278-274KLB

Q1 MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4

Q2 120V MOSFET N-CH 500V 9A DPAK ST MICRO STD11NM50N

230V MOSFET N-CH 800V 6A DPAK INFINEON SPD06N80C3

Q3, Q4 TRANS NPN 40V 0.6A SOT-23 FAIRCHILD MMBT4401

Q6 TRANS NPN 40V 0.2A SOT-23 FAIRCHILD MMBT3904

(1) Components are used in both versions unless otherwise noted

Product Folder Links: LM3450

LM3450

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

www.ti.com

Table 3. Bill of Materials(1) (continued)

Reference Designator Description Manufacturer Part Number

R1 120V RES 330Ω5% 1W 2512 VISHAY CRCW2512330RJNEG

230V RES 510Ω5% 1W 2512 VISHAY CRCW2512510RJNEG

R2 120V RES 430Ω5% 1W 2512 VISHAY CRCW2512430RJNEG

230V RES 1.6kΩ5% 1W 2512 VISHAY CRCW25121K60JNEG

R3 120V RES 402kΩ1% 0.25W 1206 VISHAY CRCW1206402KFKEA

230V RES 953kΩ1% 0.25W 1206 VISHAY CRCW1206953KFKEA

R4 RES 100Ω1% 1W 2512 VISHAY WSL2512100RFKEA

R5 RES 100kΩ1% 0.1W 0603 VISHAY CRCW0603100KFKEA

R6 RES 6.04kΩ1% 0.1W 0603 VISHAY CRCW06036K04FKEA

R7 RES 499kΩ1% 0.1W 0603 VISHAY CRCW0603499KFKEA

R8, R9 RES 49.9kΩ1% 0.1W 0603 VISHAY CRCW060349K9FKEA

R10 RES 20kΩ1% 0.1W 0603 VISHAY CRCW060320K0FKEA

R11 120V RES 1.00MΩ1% 0.25W 1206 VISHAY CRCW12061M00FKEA

230V RES 2.00MΩ1% 0.25W 1206 VISHAY CRCW12062M00FKEA

R12 RES 15.0kΩ1% 0.1W 0603 VISHAY CRCW060315K0FKEA

R13 RES 5.11kΩ1% 0.1W 0603 VISHAY CRCW06035K11FKEA

R14a, R14b, R23a, R23b, RES 1.00Ω1% 0.33W 1206 VISHAY CRCW12061R00FKEA

R23c

R15a, R15b RES 5.62Ω1% 0.25W 1206 VISHAY CRCW12065R62FKEA

R16 RES 1.00kΩ1% 0.125W 0805 VISHAY CRCW08051K00FKEA

R17 120V RES 30.1kΩ1% 0.1W 0603 VISHAY CRCW060330K1FKEA

230V RES 15.0kΩ1% 0.1W 0603 VISHAY CRCW060315K0FKEA

R18 RES 105kΩ1% 0.125W 0805 VISHAY CRCW0805105KFKEA

R19 RES 2.49kΩ1% 0.1W 0603 VISHAY CRCW06035K49FKEA

R20 RES 6.04kΩ1% 0.125W 0805 VISHAY CRCW08056K04FKEA

R21 RES 10.0kΩ1% 0.125W 0805 VISHAY CRCW080510K0FKEA

R22 RES 1.4kΩ1% 0.125W 0805 VISHAY CRCW08051K40FKEA

R24, R25 RES 10kΩ1% 0.1W 0603 VISHAY CRCW060310K0FKEA

R26 120V RES 2.49kΩ1% 0.125W 0805 VISHAY CRCW08052K49FKEA

230V RES 4.99kΩ1% 0.125W 0805 VISHAY CRCW08054K99FKEA

R27, R28 120V RES 5Ω10% 3W WIREWOUND VISHAY PAC300005008FAC000

230V RES 10Ω10% 3W WIREWOUND VISHAY PAC300001009FAC000

R29, R30 RES 4.99kΩ1% 0.1W 0603 VISHAY CRCW06034K99FKEA

R32 RES 909Ω1% 0.1W 0603 VISHAY CRCW0603909RFKEA

OPTO1, OPTO2 OPTO-ISOLATOR SMD LITE ON CNY17F-3S

T1 120V XFORMER 120V 30W OUTPUT 50V WURTH 750813651

230V XFORMER 230V 30W OUTPUT 50V WURTH 750817651

Thermal Protect see DYNAMIC HOLD section

Product Folder Links: LM3450

LM3450

www.ti.com

SNVS681D –NOVEMBER 2010–REVISED MAY 2013

REVISION HISTORY

Changes from Revision C (May 2013) to Revision D Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 32

Product Folder Links: LM3450

PACKAGE OPTION ADDENDUM

www.ti.com 10-Sep-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM3450AMT/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS

& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM LM3450

AMT

LM3450AMTX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM LM3450

AMT

LM3450MT/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS

& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LM3450

LM3450MTX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LM3450

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Sep-2014

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM3450AMTX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

LM3450MTX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM3450AMTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0

LM3450MTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2015

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

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