PRELIMINARY
Publicati on# 20977 Rev: CAmendment/+1
Issue Date: March 1998
Refer to AMD’s Website (www.amd.com) for the latest information.
Am29LV081
8 Megabit (1 M x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Optimized architecture for Miniature Card and
mass storage applications
Single power supply operation
Full v olt age r ange: 2.7 to 3.6 volt read and write
operations for battery-powered applications
Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibi lity with high
performance 3.3 volt microprocessors
High performan c e
Full voltage range: ac cess times as fast as 100
ns
Regulated voltage range: access times as fast
as 90 ns
Ultra low po wer consumption (typical values at
5 MHz)
200 nA Automatic Sleep mode current
200 nA standby mode current
10 mA read current
20 mA program/erase current
Flexible sector architecture
Sixteen 64 Kby te sectors
Supports full chip erase
Sector Protection features:
A hardware method of locking a sector (using
programming equipment) to prevent any
program or erase operations within that sector
Temporary Sector Unprotect feature allows code
changes in prev iously locked sectors
Embe dded Algorith ms
Embedded Erase algorithm automatically
preprogr ams and erases the ent ire chip or any
combination of designated sectors
Embedded Program algorithm automatically
writes and verifies data at specif ied addresses
Typical 1,000,000 write cycles per sector
(100,000 cycles minimum guaranteed)
Package option
40-pin TSOP
Compatibility with JEDEC standards
Pinout and software compatible with single-
power supply Flash
Superior inadvertent write protection
Data# Polling and toggle bits
Provides a software method of detecting
program or erase operation completion
Ready/ Busy# pin (RY/BY#)
Provides a hardware method of detec ting
program or erase cycle completion
Erase Suspend/Erase Resume
Suspends an erase operati on to read dat a from,
or progr am data to, a sector that is not being
erased, then res umes the erase operation
Hardware reset pin (RESET#)
Hardware method t o reset the device to reading
array data
2 Am29LV081
PRELIMINARY
GENERAL DESCRIPTION
The Am29LV081 is an 8 Mbit, 3.0 volt-only Flash
memory organized as 1,048,576 bytes. The device is
offered in a 40-pin T SOP package. The byte-wide (x8)
data appears on DQ7–DQ0. This device requires only
a single, 3.0 v olt V CC supply to perf orm read, program,
and erase operations. A standard EPROM pro-
grammer can also be used to program and erase the
device.
The standard device offers access times of 90, 100,
120, and 150 ns, allo wing hi gh speed microprocessors
to oper ate without wait states. To eliminate b us c onten-
tion the device has separate chip enable (CE#), write
enable ( WE#) and output enable (OE#) controls.
The de vice requires only a single 3.0 volt power sup-
ply for both read and write functions. Inter nally gener-
ated and regulated voltages are provided for the
program and erase operations.
The de vice is entirely command set compatib le with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the er ase and programming circuitry. Write cycles
also internally latch addresses and data neede d f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM de vices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
De vice erasure occurs by e xecuting the erase command
sequence. This initiates the Embedded Erase algo-
rithm—an inter nal algorithm th at automatica lly prep ro-
grams the array (if it is not already pr ogrammed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits . After a program or erase cycle has
been completed, the de v ice is ready to read arr ay data
or accept another command.
The sector erase arc hitecture all ows memory sector s
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
or y. This is achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure . True backgro und eras e can thus be achie ved.
The hardware RESET # pin terminates any operation
in progress and resets the internal state machine to
reading arr a y data. The RESET# pin ma y be tied to the
system reset circuitr y. A s ystem reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The de vice off ers tw o power-saving f eatures. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also plac e the de v ice into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
Am29LV081 3
PRELIMINARY
PRODUCT SELECTOR GUIDE
Note: S ee “AC Characterist ics for full specifications.
BLOCK DIAGRAM
Family Part Number Am29LV081
Speed Options Regulated Voltage Range: VCC =3. 0–3 .6 V -90R
Full Voltage Range: VCC = 2.7–3.6 V -100 -120 -150
Max access time, ns (tACC)90 100 120 150
Max CE# access time, ns (tCE)90 100 120 150
Max OE# access time, ns (tOE)40 40 50 55
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
CE#
OE#
STB
STB
DQ0
DQ7
Sector Switches
RY/BY#
RESET#
Data
Y-Gating
Cell Matrix
Address Latch
A0–A19
20977C-1
4 Am29LV081
PRELIMINARY
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
9
10
11
12
13
14
15
40
25
39
38
37
36
35
34
33
32
31
30
29
28
27
26
24
23
22
21
A16
A5
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A4
A3
A2
A1
A17
DQ0
VSS
NC
A19
A10
DQ7
DQ6
DQ5
OE#
VSS
CE#
A0
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
1
16
2
3
4
5
6
7
8
17
18
19
20
9
10
11
12
13
14
15
40
25
39
38
37
36
35
34
33
32
31
30
29
28
27
26
24
23
22
21
A16
A5
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A4
A3
A2
A1
A17
DQ0
VSS
NC
A19
A10
DQ7
DQ6
DQ5
CE#
VSS
CE#
A0
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
20977C-2
Reverse TSOP
Standard TSOP
Am29LV081 5
PRELIMINARY
PIN CONFIGURATION
A0–A19 = 20 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
VCC = 3.0 volt -only single power supply
(see Product Selector Guide for speed
options and vo ltage s upply toler anc es)
VSS = De vice ground
NC = Pin not connec ted internally
LOGIC SYMBOL
20977C-3
20 8
DQ0–DQ7
A0–A19
CE#
OE#
WE#
RESET#
RY/BY#
6 Am29LV081
PRELIMINARY
ORDERING INFORMATION
Standard Prod ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid C ombi-
nation) is form ed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm a vailability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am29LV081
8 Megabit (1 M x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
CE-90RAm29LV081
OPTIONAL PROCESSING
Blank = Standard Pro ces sin g
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
F = 40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
SPEED OPTION
See Product Selector Guide and Valid Combinations
Valid Combinations
Am29LV081-90R
VCC = 3.0–3.6 V EC, EI, FC, FI
Am29LV081-100 EC, EI, EE,
FC, FI, FE
Am29LV081-120
Am29LV081-150
Am29LV081 7
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The regi st er is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels the y require , and t he resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV081 Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0
±
0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Note: Addresses are A19–A0.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and select s the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at VIH.
The internal state machine is set for reading array
data upo n d e v ice power-up, or af ter a har dw ar e r eset .
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert v alid addresses on the device addr ess inputs pro-
duce v alid data on the de vice data outputs . The de vice
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 12 for the timing diagram. ICC1 in
the DC Characteristics table repres ents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
An erase oper at ion can er ase one sect or, multiple sec-
tors, or the entire device. Tab l e 2 indicat es the address
space that each sector occupies. A “sector address”
consists of th e address bits required to uniquely select
a sector. See the “Command Definitions” section for
details on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autos elect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections f or more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tabl es and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or prog ram opera tion, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Sta ndard read cycle timings and I CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the de vice,
it can place the device in the standby mode. In this
mode, current con sumption is g reat ly reduced, and the
Operation CE# OE# WE# RESET# Addresses (See Note) DQ0–DQ7
Read L L H H AIN DOUT
Write L H L H AIN DIN
Standby VCC ±
0.3 V XX V
CC ±
0.3 V X High-Z
Output Disable L H H H X High-Z
Reset X X X L X High-Z
Temporary Sector Unprotect X X X VID XX
8 Am29LV081
PRELIMINARY
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are he ld at VIH, b ut not within
VCC ± 0.3 V, the device will be in the standb y mode, b ut
the standby current will be greater . The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics table, ICC3 and ICC4 repre-
sents the standby current specific ations.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energ y consumption. The dev ice automatically enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# cont rol signals. Standard addres s
access timings provide new data w hen addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC5 in the DC
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin pro vides a har dware method of reset-
ting the device to readi ng arr a y data. When the s ystem
drives the RESET# pin t o VIL f or at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the de vice is ready
to accept another comm and sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
dra ws CMOS standby current (ICC4). If RESET# is held
at VIL b ut not within VSS±0.3 V, the s tandby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read th e boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset oper at ion is complete . If RESET# i s
asserted when a program or er ase operation is not e x-
ecuting (RY/BY# pin is “1”), the reset operation is
completed wi thin a time of tREADY (not during Embed-
ded Algorithms). The system can read data tRH after
the RESET # pi n r e tu rns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 13 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the de vice is
disabled. The output pins are plac ed in the h igh imped-
ance state.
Am29LV081 9
PRELIMINARY
Table 2. Am29LV081 Sector Address Table
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended f or programming equipment
to automatically match a de vice to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the c ommand register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in Tab le
3. In addition, when verifying sector protection, the sec-
tor address must appear on the appropriate highest
order address bits (see Table 2). Table 3 s how s the re-
maining addres s bits that are don’t care. When all nec-
essary bits hav e been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 4. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
Table 3. Am29LV081 Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
A19 A18 A17 A16 A15 A14 A13 Sector Size Address Range
SA00000XXX 64 Kbytes 00000h-0FFFFh
SA10001XXX 64 Kbytes 10000h-1FFFFh
SA20010XXX 64 Kbytes 20000h-2FFFFh
SA30011XXX 64 Kbytes 30000h-3FFFFh
SA40100XXX 64 Kbytes 40000h-4FFFFh
SA50101XXX 64 Kbytes 50000h-5FFFFh
SA60110XXX 64 Kbytes 60000h-6FFFFh
SA70111XXX 64 Kbytes 70000h-7FFFFh
SA81000XXX 64 Kbytes 80000h-8FFFFh
SA91001XXX 64 Kbytes 90000h-9FFFFh
SA101010XXX 64 Kbytes A0000h-AFFFFh
SA111011XXX 64 Kbytes B0000h-BFFFFh
SA121100XXX 64 Kbytes C0000h-CFFFFh
SA131101XXX 64 Kbytes D0000h-DFFFFh
SA141110XXX 64 Kbytes E0000h-EFFFFh
SA151111XXX 64 Kbytes F0000h-FFFFFh
Description CE# OE# WE#
A19
to A13
A12
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL 01h
Device ID: Am29LV081 L L H X X V ID XLXLH 38h
Sector Protec tion Verif icat ion L L H SA X VID XLXHL
01h
(protected)
00h
(unprotected)
10 Am29LV081
PRELIMINARY
Sector Protection/Unprotection
The hardware sector protection feature disables both
progr am and er ase opera tions in an y sect or. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMDs ExpressFlash™ Service. Contact an
AMD representative for details.
It is possib le to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Sector protection/unprotection must be implemented
using progr amming equipment.The procedure requires
a high voltage (VID) on address pin A9 and OE#. De-
tails on t his method are pro vid ed in a supp lement, pub-
lication number 21225. Contact an AMD r epresentati ve
to request a copy.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sect ors to change data in-s ystem. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, for merly protected
sectors can be progr ammed or er ased b y sele cting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 19 shows the timing diagrams, for this feature.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 4 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
pow er-down transitions , or from system noise .
Low V CC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
pow er-up and power-do wn. The command register and
all internal program/er ase circuits are disabled, and the
dev ice resets . Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protecti on
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical In hibit
Write c ycles are inhibi ted by holding any one of OE#
= VIL, CE# = VIH or WE# = VIH. To initiat e a wr ite cy-
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power
up, the device does not accept commands on the
rising edge of WE#. The inter nal state machine is
automatically reset to reading array data on
power-up.
Figure 1. Temporary Sector Unprotect Operation
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
20977C-4
Am29LV081 11
PRELIMINARY
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates de vice op-
erations. Table 4 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Charac teristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
The system
must
issue the reset command to re-en-
abl e the de vice f or reading arr ay data if DQ5 goes high,
or while in the autoselect mode. See the “Res et Com-
mand” se ctio n , next.
See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more infor mation.
The Read Operations table provides the read param e-
ters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Addres s bits are don’t c are
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the aut oselect mode , the re set command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command retur ns the device to read-
ing array data (also applies during Erase Suspend).
See the applicable “AC Characteristics” section for pa-
rameters, and to the Figure 13 for the timing waveforms.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the man uf acturer and devices c odes,
and determine whether or not a sector is protected.
Table 4 shows the address and data requirements . This
method is an alternativ e to that shown in Tabl e 3, which
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrie v es the manuf ac-
turer code. A read cycle at address XX01h returns the
device code . A read cycle containing a sector address
(SA) and t he a ddr ess 02h i n it, retu rns 01h if t hat sec-
tor is protected, or 00h if it is unprotected. Refer to
Table 2 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading arra y data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated b y writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is
not
required to provide fur ther
controls or timings. The device autom atically provides
internally generated progr am pulses and v erify the pro-
grammed cell margin. Table 4 shows the address and
data requirements for the byte program command se-
quence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
12 Am29LV081
PRELIMINARY
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the de vice has res et to read-
ing array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempt ing to do so ma y halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. Howe ver, a succeeding read will show that the
data is still “0”. Only erase operations can con vert a “0”
to a “1”.
Figure 2 illustrates the algorithm for the program oper-
ation. See the Eras e/Program Operations table in “AC
Characteristics” for parameters, and to Figure 14 for
timing diagrams.
Note: See Table 4 for program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six b us cy cle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up c ommand. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Eras e
algorithm. The device does
not
require the system to
preprogr am prior to erase. The Embedded Erase algo-
rithm automatically preprogr ams and verifies the entire
memor y for an all zero data pattern prior to electrical
erase. The system is not required to provide any c on-
trols or timings during these operations. Table 4 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Not e that a hardware
reset during the chip erase operation imm ediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated b y writing two un-
lock cycles, fo llowed by a set-up com mand. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 4 shows the address and data
requirements f or the sector eras e command sequence.
The device does
not
require the system to preprogram
the memory prior to er ase. The Embedded Erase algo-
rithm automatically progr ams and verifies the s ector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
ma y be done in any sequence , and the number of sec-
tors ma y be from one sector to al l sectors. The time be-
tween these additional cycles mus t be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The inte rrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be les s than 50 µs, the
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
20977C-5
Am29LV081 13
PRELIMINARY
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and com mands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Er ase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence .
Once the sector erase operation has begun, only the
Erase Suspend command is v alid. All oth er commands
are ignored. Note that a hardware reset during the
sector erase operation im mediately terminates the op-
eration. The Sector Eras e command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Eras e algorithm is complete, the
dev ice returns to reading arra y data and addresses are
no longer latched. The system can determine the sta-
tus of the erase opera tion b y using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa-
tion on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters , and to
Figure 15 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend c ommand allo ws the s ystem to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only dur ing the s ector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and s uspends t he er ase oper at ion. Ad-
dresses are “don’t-cares” when writing the Erase Sus -
pend command.
When the Erase Suspend command is written during a
sector erase oper ation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected f or eras ure. (The de vice “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autos elect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “ Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the s ector erase oper ati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be wr itten after the de-
vice has resumed erasing.
Notes:
1. See Table 4 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
20977C-6
14 Am29LV081
PRELIMINARY
Table 4. Am29LV081 Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read op eration.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be v erified (in autoselect mode) or
erased. Address bits A19–A13 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. All address bits are don’t cares for unlock and command
cycles, except when SA or PA required.
5. No unlock or command cycles required when read ing array
data.
6. The Reset command is requ ired to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a
read cycle.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Sus pend command is valid on ly during a
sector erase operation.
10. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2-4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Auto-
select
(Note 7)
Manufacturer ID 4 XXX AA XXX 55 XXX 90 X00 01
Device ID 4 XXX AA XXX 55 XXX 90 X01 38
Sector Protect Verify
(Note 8) 4XXX AA XXX 55 XXX 90 (SA)
X02 00
XXX XXX XXX 01
Program 4 XXX AA XXX 55 XXX A0 PA PD
Chip Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 XXX 10
Sector Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 SA 30
Erase Sus pend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30
Cycles
Am29LV081 15
PRELIMINARY
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and R Y/BY# . Tabl e 5 and the f ollo wing subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# P olling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se-
quence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is a ctive f or ap-
proximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When t he Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Po lling produces a “1” on DQ7.
This is analogous t o the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an er ase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active f or approximately 100 µs, then t he de-
vice returns to reading array data. If not all selected
sectors are protec ted, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid dat a at DQ7–
DQ0 on the
following
read cycles . This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted lo w. Figure 16, Data#
Polling Timings (During Embedded Algor ithms), in the
“AC Characteristics” section illustrates this.
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
20977C-7
Figure 4. Data# Polling Algorithm
16 Am29LV081
PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the outpu t is low (Busy ), the de vice is activ ely er asing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 5 shows the outputs for RY/BY#. Figures 12, 13,
14 and 15 sho ws RY/BY# f or read, reset, progr am, and
erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete ,
or whether the dev ice has entered the Erase Sus pend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read c ycles.) When the operation is
complete, DQ6 stops toggling.
After an er ase command sequence is written, if all sec-
tors selected f or er asing are protected , DQ6 toggles f or
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the de vice is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then retur ns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 5 shows the outputs for Toggle Bit I on DQ6.
Refer to Figure 5 for the toggle bit algorithm, and to the
Figure 17 in the “AC Characteristics” section for the
timing diagram. Figure 18 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used w ith DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the Embedded Er ase algo rithm is in progr ess),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pu lse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode info rmation. Ref er t o Tab le 5 to c ompare output s
for DQ2 and DQ6.
Figure 5 shows the toggle bit algorithm in flowchart
for m, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsecti on.
Refer to Figure 17 f or the toggle bit timing diagr am. Fig-
ure 18 shows the dif ferences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the follo wing discussion. Whene v er
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the second read, the system would com-
pare the new value of the toggle bit with the first. If the
toggle bit is not toggling , the device has c ompleted the
program or erase operation. The system can read arra y
data on DQ7–DQ0 on the follo wing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
Am29LV081 17
PRELIMINARY
The remaining scenario is that the system initially de-
termines that the toggle bit is togglin g and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successiv e read cycles , de-
termining the stat us as described in the previous par a-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it re turns to determine
the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exc eeded a specified inter nal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the pro gram or er ase cycle w as
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
dev ice halts t he operat ion, and when the oper ation has
exceeded the timing limits , DQ5 produces a “1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to deter mine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure , the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0”
to1.The system may ignore DQ3 if t he system can
guarantee that the time between additional sector
erase commands will always be less than 50 µs. See
also the “Sector Er ase Command Sequence” section.
After the sector erase command sequence is written,
the system should rea d th e stat us on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence , and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other tha n Er ase Sus pend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the s ystem softw are should chec k the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Tab le 5 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1” . See text.
20977C-8
Figure 5. Toggle Bit Algorith m
(Notes
1, 2)
(Note 1)
18 Am29LV081
PRELIMINARY
Table 5. Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Operation DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) RY/BY#
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector 1 No toggle 0 N/A Toggle 1
Reading within Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
Am29LV081 19
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . .0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1) . . . . . –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot
to VCC +2.0 V for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 6. Maximu m Negative Overshoot
Waveform\
Figure 7. Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . 40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range. . . . .+3.0 V to +3.6 V
VCC for full v oltage range. . . . . . . . . .+2.7 V to +3.6 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20977C-9
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
20977C-10
20 Am29LV081
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
4. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(Note 1) CE# = VIL, OE# = VIH 5 MHz 10 16 mA
1 MHz 2 4
ICC2 VCC Active Write Current
(Notes 2 and 4) CE# = VIL, OE# = VIH 20 30 mA
ICC3 VCC Standby Current VCC = VCC max;
CE#, RESET# = VCC±0.3 V 0.2 5 µA
ICC4 VCC Standby Current During Reset VCC = VCC max;
RESET# = VSS ± 0.3 V 0.2 5 µA
ICC5 Automatic Sleep Mode (Note 3) VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V 0.2 5 µA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VID Voltage for Autoselect and
Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO Low VCC Lock-Out V oltage (Note 4) 2.3 2.5 V
Am29LV081 21
PRELIMINARY
DC CHARACTERISTICS (Continued)
Zero Power Flash
Note: Addresses are switching at 1 MHz
20977C-11
Figure 8. ICC1 Current vs. Time (Showin g Active and Au tomatic Sleep Currents)
25
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
Note: T = 25
°
C
20977C-12
Figure 9. Typical ICC1 vs. Frequency
15
10
5
0
1 2345
3
.
6
V
2.7 V
Frequency in MHz
Supply Current in mA
22 Am29LV081
PRELIMINARY
TEST CONDITIONS Table 6. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 k
CL6.2 k
3.3 V
Device
Under
Test
20977C-13
Figure 10. Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition -90R,
-100 -120,
-150 Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap aci tan ce) 30 100 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement
reference levels 1.5 V
Output timing measurement
reference levels 1.5 V
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput
20977C-14
Figure 11. Input Waveforms and Measurement Levels
Am29LV081 23
PRELIMINARY
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 10 and Table 6 for test specifications.
Parameter
Description
Speed Option
JEDEC Std Test Setup -90R -100 -120 -150 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 90 100 120 150 ns
tAVQV tACC Address to Output Delay CE# = VIL
OE# = VIL Max 90 100 120 150 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 120 150 ns
tGLQV tOE Output Enable to Output Delay Max 40 40 50 55 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 30 30 30 40 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 30 30 30 40 ns
tOEH Output Enable
Hold Time (Note 1)
Read Min 0 ns
Toggle and
Data# Po llin g Min 10 ns
tAXQX tOH Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1) Min 0 ns
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
RY/BY#
RESET#
tDF
tOH
20977C-15
Figure 12. Read Operations Timings
24 Am29LV081
PRELIMINARY
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested.
Parameter
Description All Speed OptionsJEDEC Std Test Setup Unit
tREADY RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note) Max 20 µs
tREADY RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH RESET# High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
20977C-16
Figure 13. RESET# Timings