PRELIMINARY
Publicati on# 20977 Rev: CAmendment/+1
Issue Date: March 1998
Refer to AMD’s Website (www.amd.com) for the latest information.
Am29LV081
8 Megabit (1 M x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Optimized architecture for Miniature Card and
mass storage applications
Single power supply operation
Full v olt age r ange: 2.7 to 3.6 volt read and write
operations for battery-powered applications
Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibi lity with high
performance 3.3 volt microprocessors
High performan c e
Full voltage range: ac cess times as fast as 100
ns
Regulated voltage range: access times as fast
as 90 ns
Ultra low po wer consumption (typical values at
5 MHz)
200 nA Automatic Sleep mode current
200 nA standby mode current
10 mA read current
20 mA program/erase current
Flexible sector architecture
Sixteen 64 Kby te sectors
Supports full chip erase
Sector Protection features:
A hardware method of locking a sector (using
programming equipment) to prevent any
program or erase operations within that sector
Temporary Sector Unprotect feature allows code
changes in prev iously locked sectors
Embe dded Algorith ms
Embedded Erase algorithm automatically
preprogr ams and erases the ent ire chip or any
combination of designated sectors
Embedded Program algorithm automatically
writes and verifies data at specif ied addresses
Typical 1,000,000 write cycles per sector
(100,000 cycles minimum guaranteed)
Package option
40-pin TSOP
Compatibility with JEDEC standards
Pinout and software compatible with single-
power supply Flash
Superior inadvertent write protection
Data# Polling and toggle bits
Provides a software method of detecting
program or erase operation completion
Ready/ Busy# pin (RY/BY#)
Provides a hardware method of detec ting
program or erase cycle completion
Erase Suspend/Erase Resume
Suspends an erase operati on to read dat a from,
or progr am data to, a sector that is not being
erased, then res umes the erase operation
Hardware reset pin (RESET#)
Hardware method t o reset the device to reading
array data
2 Am29LV081
PRELIMINARY
GENERAL DESCRIPTION
The Am29LV081 is an 8 Mbit, 3.0 volt-only Flash
memory organized as 1,048,576 bytes. The device is
offered in a 40-pin T SOP package. The byte-wide (x8)
data appears on DQ7–DQ0. This device requires only
a single, 3.0 v olt V CC supply to perf orm read, program,
and erase operations. A standard EPROM pro-
grammer can also be used to program and erase the
device.
The standard device offers access times of 90, 100,
120, and 150 ns, allo wing hi gh speed microprocessors
to oper ate without wait states. To eliminate b us c onten-
tion the device has separate chip enable (CE#), write
enable ( WE#) and output enable (OE#) controls.
The de vice requires only a single 3.0 volt power sup-
ply for both read and write functions. Inter nally gener-
ated and regulated voltages are provided for the
program and erase operations.
The de vice is entirely command set compatib le with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the er ase and programming circuitry. Write cycles
also internally latch addresses and data neede d f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM de vices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
De vice erasure occurs by e xecuting the erase command
sequence. This initiates the Embedded Erase algo-
rithm—an inter nal algorithm th at automatica lly prep ro-
grams the array (if it is not already pr ogrammed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits . After a program or erase cycle has
been completed, the de v ice is ready to read arr ay data
or accept another command.
The sector erase arc hitecture all ows memory sector s
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
or y. This is achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure . True backgro und eras e can thus be achie ved.
The hardware RESET # pin terminates any operation
in progress and resets the internal state machine to
reading arr a y data. The RESET# pin ma y be tied to the
system reset circuitr y. A s ystem reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The de vice off ers tw o power-saving f eatures. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also plac e the de v ice into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
Am29LV081 3
PRELIMINARY
PRODUCT SELECTOR GUIDE
Note: S ee “AC Characterist ics for full specifications.
BLOCK DIAGRAM
Family Part Number Am29LV081
Speed Options Regulated Voltage Range: VCC =3. 0–3 .6 V -90R
Full Voltage Range: VCC = 2.7–3.6 V -100 -120 -150
Max access time, ns (tACC)90 100 120 150
Max CE# access time, ns (tCE)90 100 120 150
Max OE# access time, ns (tOE)40 40 50 55
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
CE#
OE#
STB
STB
DQ0
DQ7
Sector Switches
RY/BY#
RESET#
Data
Y-Gating
Cell Matrix
Address Latch
A0–A19
20977C-1
4 Am29LV081
PRELIMINARY
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
9
10
11
12
13
14
15
40
25
39
38
37
36
35
34
33
32
31
30
29
28
27
26
24
23
22
21
A16
A5
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A4
A3
A2
A1
A17
DQ0
VSS
NC
A19
A10
DQ7
DQ6
DQ5
OE#
VSS
CE#
A0
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
1
16
2
3
4
5
6
7
8
17
18
19
20
9
10
11
12
13
14
15
40
25
39
38
37
36
35
34
33
32
31
30
29
28
27
26
24
23
22
21
A16
A5
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A4
A3
A2
A1
A17
DQ0
VSS
NC
A19
A10
DQ7
DQ6
DQ5
CE#
VSS
CE#
A0
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
20977C-2
Reverse TSOP
Standard TSOP
Am29LV081 5
PRELIMINARY
PIN CONFIGURATION
A0–A19 = 20 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
VCC = 3.0 volt -only single power supply
(see Product Selector Guide for speed
options and vo ltage s upply toler anc es)
VSS = De vice ground
NC = Pin not connec ted internally
LOGIC SYMBOL
20977C-3
20 8
DQ0–DQ7
A0–A19
CE#
OE#
WE#
RESET#
RY/BY#
6 Am29LV081
PRELIMINARY
ORDERING INFORMATION
Standard Prod ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid C ombi-
nation) is form ed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm a vailability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am29LV081
8 Megabit (1 M x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
CE-90RAm29LV081
OPTIONAL PROCESSING
Blank = Standard Pro ces sin g
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
F = 40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
SPEED OPTION
See Product Selector Guide and Valid Combinations
Valid Combinations
Am29LV081-90R
VCC = 3.0–3.6 V EC, EI, FC, FI
Am29LV081-100 EC, EI, EE,
FC, FI, FE
Am29LV081-120
Am29LV081-150
Am29LV081 7
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The regi st er is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels the y require , and t he resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV081 Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0
±
0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Note: Addresses are A19–A0.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and select s the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at VIH.
The internal state machine is set for reading array
data upo n d e v ice power-up, or af ter a har dw ar e r eset .
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert v alid addresses on the device addr ess inputs pro-
duce v alid data on the de vice data outputs . The de vice
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 12 for the timing diagram. ICC1 in
the DC Characteristics table repres ents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
An erase oper at ion can er ase one sect or, multiple sec-
tors, or the entire device. Tab l e 2 indicat es the address
space that each sector occupies. A “sector address”
consists of th e address bits required to uniquely select
a sector. See the “Command Definitions” section for
details on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autos elect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections f or more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tabl es and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or prog ram opera tion, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Sta ndard read cycle timings and I CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the de vice,
it can place the device in the standby mode. In this
mode, current con sumption is g reat ly reduced, and the
Operation CE# OE# WE# RESET# Addresses (See Note) DQ0–DQ7
Read L L H H AIN DOUT
Write L H L H AIN DIN
Standby VCC ±
0.3 V XX V
CC ±
0.3 V X High-Z
Output Disable L H H H X High-Z
Reset X X X L X High-Z
Temporary Sector Unprotect X X X VID XX
8 Am29LV081
PRELIMINARY
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are he ld at VIH, b ut not within
VCC ± 0.3 V, the device will be in the standb y mode, b ut
the standby current will be greater . The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics table, ICC3 and ICC4 repre-
sents the standby current specific ations.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energ y consumption. The dev ice automatically enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# cont rol signals. Standard addres s
access timings provide new data w hen addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC5 in the DC
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin pro vides a har dware method of reset-
ting the device to readi ng arr a y data. When the s ystem
drives the RESET# pin t o VIL f or at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the de vice is ready
to accept another comm and sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
dra ws CMOS standby current (ICC4). If RESET# is held
at VIL b ut not within VSS±0.3 V, the s tandby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read th e boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset oper at ion is complete . If RESET# i s
asserted when a program or er ase operation is not e x-
ecuting (RY/BY# pin is “1”), the reset operation is
completed wi thin a time of tREADY (not during Embed-
ded Algorithms). The system can read data tRH after
the RESET # pi n r e tu rns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 13 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the de vice is
disabled. The output pins are plac ed in the h igh imped-
ance state.
Am29LV081 9
PRELIMINARY
Table 2. Am29LV081 Sector Address Table
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended f or programming equipment
to automatically match a de vice to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the c ommand register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in Tab le
3. In addition, when verifying sector protection, the sec-
tor address must appear on the appropriate highest
order address bits (see Table 2). Table 3 s how s the re-
maining addres s bits that are don’t care. When all nec-
essary bits hav e been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 4. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
Table 3. Am29LV081 Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
A19 A18 A17 A16 A15 A14 A13 Sector Size Address Range
SA00000XXX 64 Kbytes 00000h-0FFFFh
SA10001XXX 64 Kbytes 10000h-1FFFFh
SA20010XXX 64 Kbytes 20000h-2FFFFh
SA30011XXX 64 Kbytes 30000h-3FFFFh
SA40100XXX 64 Kbytes 40000h-4FFFFh
SA50101XXX 64 Kbytes 50000h-5FFFFh
SA60110XXX 64 Kbytes 60000h-6FFFFh
SA70111XXX 64 Kbytes 70000h-7FFFFh
SA81000XXX 64 Kbytes 80000h-8FFFFh
SA91001XXX 64 Kbytes 90000h-9FFFFh
SA101010XXX 64 Kbytes A0000h-AFFFFh
SA111011XXX 64 Kbytes B0000h-BFFFFh
SA121100XXX 64 Kbytes C0000h-CFFFFh
SA131101XXX 64 Kbytes D0000h-DFFFFh
SA141110XXX 64 Kbytes E0000h-EFFFFh
SA151111XXX 64 Kbytes F0000h-FFFFFh
Description CE# OE# WE#
A19
to A13
A12
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL 01h
Device ID: Am29LV081 L L H X X V ID XLXLH 38h
Sector Protec tion Verif icat ion L L H SA X VID XLXHL
01h
(protected)
00h
(unprotected)
10 Am29LV081
PRELIMINARY
Sector Protection/Unprotection
The hardware sector protection feature disables both
progr am and er ase opera tions in an y sect or. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMDs ExpressFlash™ Service. Contact an
AMD representative for details.
It is possib le to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Sector protection/unprotection must be implemented
using progr amming equipment.The procedure requires
a high voltage (VID) on address pin A9 and OE#. De-
tails on t his method are pro vid ed in a supp lement, pub-
lication number 21225. Contact an AMD r epresentati ve
to request a copy.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sect ors to change data in-s ystem. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, for merly protected
sectors can be progr ammed or er ased b y sele cting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 19 shows the timing diagrams, for this feature.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 4 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
pow er-down transitions , or from system noise .
Low V CC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
pow er-up and power-do wn. The command register and
all internal program/er ase circuits are disabled, and the
dev ice resets . Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protecti on
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical In hibit
Write c ycles are inhibi ted by holding any one of OE#
= VIL, CE# = VIH or WE# = VIH. To initiat e a wr ite cy-
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power
up, the device does not accept commands on the
rising edge of WE#. The inter nal state machine is
automatically reset to reading array data on
power-up.
Figure 1. Temporary Sector Unprotect Operation
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
20977C-4
Am29LV081 11
PRELIMINARY
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates de vice op-
erations. Table 4 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Charac teristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
The system
must
issue the reset command to re-en-
abl e the de vice f or reading arr ay data if DQ5 goes high,
or while in the autoselect mode. See the “Res et Com-
mand” se ctio n , next.
See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more infor mation.
The Read Operations table provides the read param e-
ters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Addres s bits are don’t c are
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the aut oselect mode , the re set command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command retur ns the device to read-
ing array data (also applies during Erase Suspend).
See the applicable “AC Characteristics” section for pa-
rameters, and to the Figure 13 for the timing waveforms.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the man uf acturer and devices c odes,
and determine whether or not a sector is protected.
Table 4 shows the address and data requirements . This
method is an alternativ e to that shown in Tabl e 3, which
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrie v es the manuf ac-
turer code. A read cycle at address XX01h returns the
device code . A read cycle containing a sector address
(SA) and t he a ddr ess 02h i n it, retu rns 01h if t hat sec-
tor is protected, or 00h if it is unprotected. Refer to
Table 2 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading arra y data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated b y writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is
not
required to provide fur ther
controls or timings. The device autom atically provides
internally generated progr am pulses and v erify the pro-
grammed cell margin. Table 4 shows the address and
data requirements for the byte program command se-
quence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
12 Am29LV081
PRELIMINARY
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the de vice has res et to read-
ing array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempt ing to do so ma y halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. Howe ver, a succeeding read will show that the
data is still “0”. Only erase operations can con vert a “0”
to a “1”.
Figure 2 illustrates the algorithm for the program oper-
ation. See the Eras e/Program Operations table in “AC
Characteristics” for parameters, and to Figure 14 for
timing diagrams.
Note: See Table 4 for program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six b us cy cle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up c ommand. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Eras e
algorithm. The device does
not
require the system to
preprogr am prior to erase. The Embedded Erase algo-
rithm automatically preprogr ams and verifies the entire
memor y for an all zero data pattern prior to electrical
erase. The system is not required to provide any c on-
trols or timings during these operations. Table 4 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Not e that a hardware
reset during the chip erase operation imm ediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated b y writing two un-
lock cycles, fo llowed by a set-up com mand. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 4 shows the address and data
requirements f or the sector eras e command sequence.
The device does
not
require the system to preprogram
the memory prior to er ase. The Embedded Erase algo-
rithm automatically progr ams and verifies the s ector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
ma y be done in any sequence , and the number of sec-
tors ma y be from one sector to al l sectors. The time be-
tween these additional cycles mus t be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The inte rrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be les s than 50 µs, the
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
20977C-5