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STA508
February 2006
1FEATURES
■MULTIPOWER BCD TECHNOLOGY
■MINIMUM INPUT OUTPUT PULSE WIDTH
DISTORTION
■200mΩ RdsON COMPLEMENTARY DMOS
OUTPUT STAGE
■CMOS COMPATIBLE LOGIC INPUTS
■THERMAL PROTECTION
■THERMAL WARNING OUTPUT
■UNDER VOLTAGE PROTECTION
2 DESCRIPTION
STA508 is a monolithic quad half bridge stage in Mul-
tipower BCD Technology. The device can be used as
dual bridge or reconfigured, by connecting CONFIG
pin to Vdd pin, as single bridge with double current
capability, and as half bridge (Binary mode) with half
current capability.
The device is particularly designed to make the out-
put stage of a stereo All-Digital High Efficiency
(DDX™) amplifier capable to deliver 80 + 80W @
THD = 10% at V
cc
35V output power on 8
Ω
load.
In single BTL configuration is also capable to deliver
a peak of 160W @THD = 10% at V
CC
= 35V on 4
Ω
load. The input pins have threshold proportional to V
L
pin voltage.
40V 4.5A QUAD POWER HALF BRIDGE
Figure 2. Block Diagram
L18 22µH
L19 22µH
C30
1µF
C20
100nF
C99
100nF
C101
100nF
C107
100nF
C106
100nF
C23
470nF
C55
1000µF
C21
100nF
C58
100nF
C58
100nF
R57
10K
R59
10K
R63
20
R98
6
R100
6
C53
100nF
C60
100nF
C31
1µF
C52
330pF
R104
20
C109
330pF
15
M3
IN1A
IN1A
VL
CONFIG
PWRDNPWRDN
FAULT
TRI-STATE
TH_WAR
TH_WAR
+3.3V
IN1B
VDD
VDD
VSS
VSS
VCCSIGN
VCCSIGN
GND-Reg
GND-Clean
IN2A
IN1B
IN2A
IN2B
PROTECTIONS
&
LOGIC
REGULATORS
29
23
24
25
27
26
28
30
21
22
33
34
35
36
M2
M5
M4
17
16
OUT1A
GND1A
OUT1A
VCC1A
14
12
10
11
OUT1B
GND1B
OUT1B
VCC1B
13
L113 22µH
L112 22µH
C32
1µF
+VCC
C108
470nF
C33
1µF
7
M17
M15
M16
M14
8
9
OUT2A
GND2A
OUT2A
VCC2A
6
4
2
3
OUT2B
GND2B
D00AU1148B
OUT2B
VCC2B
5
19
31
20
GNDSUB 1
IN2B 32
C110
100nF
C111
100nF
R103
6
R102
6
8Ω
8Ω
Rev. 4
Fi
gure 1.
P
ac
k
age
Table 1. Order Codes
Part Number Package
STA508 PowerSO36
PowerSO36
STA508
2/10
Table 2. Pin Description
N° Pin Description
1 GND-SUB Substrate Ground
2 ; 3 OUT2B Output Half Bridge 2B
4V
CC 2B Positive Supply
5 GND2B Negative Supply
6 GND2A Negative Supply
7V
CC 2A Positive Supply
8 ; 9 OUT2A Output Half Bridge 2A
10 ; 11 OUT1B Output Half Bridge 1B
12 VCC1B Positive Supply
13 GND1B Negative Supply
14 GND1A Negative Supply
15 VCC1A Positive Supply
16 ; 17 OUT1A Output Half Bridge 1A
18 NC Not Connected
19 GND-clean Logical Ground
20 GND-Reg Ground for Regulator Vdd
21 ; 22 Vdd 5V Regulator Referred to Ground
23 VLHigh Logical State Setting Voltage
24 CONFIG Configuration pin
25 PWRDN Stand-by pin
26 TRI-STATE Hi-Z pin
27 FAULT Fault pin Advisor
28 TH-WAR Thermal Warning Advisor
29 IN1A Input of Half Bridge 1A
30 IN1B Input of Half Bridge 1B
31 IN2A Input of Half Bridge 2A
32 IN2B Input of Half Bridge 2B
33 ; 34 VSS 5V Regulator Referred to +VCC
35 ; 36 VCC Sign Signal Positive Supply
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STA508
Table 3. FUNCTIONAL PIN STATUS
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
(**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
Figure 3. PIN CONNECTION
Table 4. THERMAL DATA
PIN NAME Logical value IC -STATUS
FAULT 0 Fault detected (Short circuit, or Thermal ..)
FAULT (*) 1 Normal Operation
TRI-STATE 0 All powers in Hi-Z state
TRI-STATE 1 Normal operation
PWRDN 0 Low absorpion
PWRDN 1 Normal operation
THWAR 0 Temperature of the IC =130°C
THWAR(*) 1 Normal operation
CONFIG 0 Normal Operation
CONFIG(**) 1 OUT1A = OUT1B ; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)
Symbol Description Value Unit
Rth j-case Thermal Resistance Junction-case max 1.5 °C/W
GND-SUB
OUT2B
OUT2B
VCC2B
GND1B
VCC1A
GND1A
OUT1A
OUT1AGND-Reg
VDD
VDD
CONFIG
VSS
VSS
VCCSign
VCCSign
18
16
17
15
6
5
4
3
2
21
22
31
32
33
35
34
36
20
1
19 N.C.GND-Clean
D01AU1273
OUT1B
VCC1B
OUT1B
PWRDN
FAULT
TRI-STATE
9
8
7
28
29
30
OUT2ATH_WAR
1027
GND2B
OUT2A
VCC2A
IN1A
IN2B
IN1B
14
12
11
23
25
26
GND2AIN2A
1324
VL
STA508
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Table 5. ABSOLUTE MAXIMUM RATINGS
Table 6. ELECTRICAL CHARACTERISTCS (V
L
= 3.3V; V
CC
= 30V; T
amb
= 25°C ; f
sw
=384 unless
otherwise specified)
Symbol Parameter Value Unit
VCC DC Supply Voltage (Pin 4,7,12,15) 40 V
Vmax Maximum Voltage on pins 23 to 32 5.5 V
Ptot Power Dissipation (Tcase = 70°C) 50 W
Top Operating Temperature Range -40 to 90 °C
Tstg, TjStorage and Junction Temperature -40 to 150 °C
Symbol Parameter Test conditions Min. Typ. Max. Unit
RdsON Power Pchannel/Nchannel
MOSFET RdsON
Id=1A 200 270 mΩ
Idss Power Pchannel/Nchannel
leakage Idss
VCC =35V 50 µA
gNPower Pchannel RdsON Matching Id=1A 95 %
gPPower Nchannel RdsON
Matching
Id=1A 95 %
Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 4 10 20 ns
Dt_d High current Dead Time (dinamic) L=22µH; C = 470nF; RL = 8 Ω
Id=3.5A; see fig. 3
50 ns
td ON Turn-on delay time Resistive load 100 ns
td OFF Turn-off delay time Resistive load 100 ns
trRise time Resistive load; as fig.4 25 ns
tfFall time Resistive load; as fig. 4 25 ns
VCC Supply voltage operating voltage 10 36 V
VIN-High High level input voltage V
L
/2
+300mV
V
VIN-Low Low level input voltage V
L
/2
-
300mV
V
IIN-High High level Input current Pin Voltage = V
L
1µA
IIN-Low Low level input current Pin Voltage = 0.3V 1 µA
I
PWRDN-H
High level PWRDN pin input
current
VL = 3.3V 35 µA
VLLow logical state voltage VL (pin
PWRDN, TRISTATE) (note 1)
VL = 3.3V 0.8 V
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STA508
Table 7.
Notes: 1. The following table explains the VLow, VHigh variation with V
L
Note 2: See relevant Application Note AN1994
Table 8.
Logic Truth Table (see fig. 5)
VHHigh logical state voltage VH (pin
PWRDN, TRISTATE) (note 1)
VL = 3.3V 1.7 V
IVCC-
PWRDN
Supply CURRENT from Vcc in
Power Down
PWRDN = 0 3 mA
IFAU LT Output Current pins
FAULT -TH-WARN when
FAULT CONDITIONS
Vpin = 3.3V 1 mA
IVCC-hiz Supply Current from Vcc in Tri-
state
VCC = 30V; Tri-state = 0 22 mA
IVCC Supply Current from Vcc in
operation
both channel switching)
VCC =30V;
Input Pulse width = 50% Duty;
Switching Frequency = 384KHz;
No LC filters;
50 mA
IVCC-q Isc (short circuit current limit)
(note 2)
4.5 6 9 A
VUV Undervoltage protection threshold 7 V
t
pw-min
Output minimum pulse width No Load 70 150 ns
VLVLow min VHigh max Unit
2.7 0.7 1.5 V
3.3 0.8 1.7 V
5 0.85 1.85 V
TRI-STATE INxA INxB Q1 Q2 Q3 Q4 OUTPUT
MODE
0xxOFFOFFOFFOFFHi-Z
1 0 0 OFF OFF ON ON DUMP
101OFFONONOFFNEGATIVE
1 1 0 ON OFF OFF ON POSITIVE
1 1 1 ON ON OFF OFF Not used
Symbol Parameter Test conditions Min. Typ. Max. Unit
Table 6. ELECTRICAL CHARACTERISTCS (continued)
STA508
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Figure 4. Test Circuit.
Figure 5.
Figure 6.
Low current dead time = MAX(DTr,DTf)
OUTxY
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
t
DTfDTr
Duty cycle = 50%
INxY OUTxY
gnd
+Vcc
M58
M57
R 8Ω
+
-V67 =
vdc = Vcc/2
D03AU1458
INxA INxB
+VCC
Q1
Q3
Q2
Q4
OUTxA
GND
OUTxB
D00AU1134
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Rload=8Ω
Q2
OUTB
DTout(B) DTin(B)
DTout(A)
C71 470nF C70
470nF
C69
470nF
Iout=4A
Iout=4A
Q4
Q1
Q3
M64
INB
M63
D03AU1517
M58
INA
M57
DTin(A)
Duty cycle=A Duty cycle=B
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
L68 22µL67 22µ
OUTA
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STA508
Figure 7. Typical Single BTL Configuration
Figure 8. Typical Quad Half Bridge Configuration
For more information refer to the application notes AN1456 and AN1661
10µH
10µH
100nF
FILM
100nF
X7R
100nF
X7R
1µF
X7R
2200µF
63V
470nF
FILM
100nF
FILM
100nF
10K
10K 6.2
1/2W
6.2
1/2W
100nF
X7R
100nF
X7R
Add.
IN1A
IN1A
V
L
CONFIG
PWRDN
nPWRDN
FAULT
TRI-STATE
TH_WAR
TH_WAR
+3.3V
100nF
100nF
X7R
IN1B
V
DD
V
DD
V
SS
V
SS
V
CC
SIGN
V
CC
SIGN
GND-Reg
GND-Clean
IN1B
IN2A
29
23 N.C.
24
25
27
26
28
30
21
22
33
34
35
36
17
16
18
OUT1A
GND1B
OUT1A
V
CC
1B
10
13
11 OUT1B
GND1A
OUT1B
14
32V
330pF
22Ω
1/2W
4Ω
GND2A
6
2
12
V
CC
1A
15
V
CC
2B
4
V
CC
2A
7
3OUT2B
GND2B
D03AU1514
OUT2B
5
19
31
20
GNDSUB 1
IN2B 32
8
9OUT2A
OUT2A
1µF
X7R
32V
L11 22µH
L12 22µH
C51
1µF
C71
100nF C91
1µF
C81
100nF
C31 820µF
C21
2200µF
C58
100nF
C58
100nF
R57
10K
R59
10K
R41
20
R61
5K
R62
5K
R51
6
C53
100nF
C60
100nF
C61
100nF
15
M3
IN1A
IN1A
VL
CONFIG
PWRDNPWRDN
FAULT
TRI-STATE
TH_WAR
TH_WAR
+3.3V
IN1B
VDD
VDD
VSS
VSS
VCCSIGN
VCCSIGN
GND-Reg
GND-Clean
IN2A
IN1B
IN2A
IN2B
PROTECTIONS
&
LOGIC
REGULATORS
29
23
24
25
27
26
28
30
21
22
33
34
35
36
M2
M5
M4
17
16
OUTPL
PGND1P
OUTPL
VCC1P
14
12
10
11
OUTNL
PGND1N
OUTNL
VCC1N
13
C52
1µF
+VCC
C62
100nF
7
M17
M15
M16
M14
8
9
OUTPR
PGND2P
OUTPR
VCC2P
6
4
2
3
OUTNR
PGND2N
D03AU1474
OUTNR
VCC2N
5
19
31
20
GNDSUB 1
IN2B 32
C72
100nF C92
1µF
C82
100nF
R52
6
C41
330pF
R42
20
C42
330pF
C32 820µF
L13 22µH
L14 22µH
C73
100nF C93
1µF
C83
100nF
C33 820µF
R43
20
R53
6
C74
100nF C94
1µF
C84
100nF
R54
6
C43
330pF
R44
20
C44
330pF
C34 820µF
R63
5K
R64
5K
R65
5K
R66
5K
R67
5K
R68
5K
4Ω
4Ω
4Ω
4Ω
STA508
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Figure 9. Power SO36 (SLUG UP) Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
M. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.25 3.43 0.128 0.135
A2 3.1 3.2 0.122 0.126
A4 0.8 1 0.031 0.039
A5 0.2 0.008
a1 0.030
-0.040
0.0011
-0.0015
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D 15.8 16 0.622 0.630
D1 9.4 9.8 0.37 0.38
D2 1 0.039
E 13.9 14.5 0.547 0.57
E1 10.9 11.1 0.429 0.437
E2 2.9 0.114
E3 5.8 6.2 0.228 0.244
E4 2.9 3.2 0.114 1.259
e0.65 0.026
e3 11.05 0.435
G 0 0.075 0 0.003
H 15.5 15.9 0.61 0.625
h 1.1 0.043
L 0.8 1.1 0.031 0.043
N 10˚ 10˚
s8˚8˚
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
DI
PowerSO36 (SLUG UP)
7183931 D
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STA508
Table 9. Revision History
Date Revision Description of Changes
September 1994 1 First Issue
June 2004 2 Note 2: See relevant Application Note AN1994
November 2004 3 Changed Vcc from 9 min to 10 min
February 2006 4 Changed T
op
value on Table 5.
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STA508
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