2016-2017 Microchip Technology Inc. DS70005258B-page 467
dsPIC33EPXXXGS70X/80X FAMILY
INDEX
A
Absolute Maximum Ratings .............................................. 375
AC Characteristics ............................................................ 387
ADC Specifications ................................................... 428
Analog Current Specifications................................... 427
Analog-to-Digital Conversion Requirements............. 430
Auxiliary PLL Clock ................................................... 389
CANx I/O Requirements ........................................... 426
Capacitive Loading Requirements on
Output Pins ....................................................... 387
DMA Module Requirements...................................... 433
External Clock Requirements ................................... 388
High-Speed PWMx Requirements ............................ 397
I/O Requirements...................................................... 391
I2Cx Bus Data Requirements (Master Mode) ........... 423
I2Cx Bus Data Requirements (Slave Mode) ............. 425
Input Capture x Requirements .................................. 395
Internal FRC Accuracy.............................................. 390
Internal LPRC Accuracy............................................ 390
Load Conditions ........................................................ 387
OCx/PWMx Module Requirements ........................... 396
Output Compare x Requirements ............................. 396
PLL Clock.................................................................. 389
Reset, WDT, OST, PWRT Requirements ................. 392
SPI1, SPI2 and SPI3 Master Mode (Full-Duplex,
CKE = 0, CKP = x, SMP = 1) Requirements..... 401
SPI1, SPI2 and SPI3 Master Mode (Full-Duplex,
CKE = 1, CKP = x, SMP = 1) Requirements..... 400
SPI1, SPI2 and SPI3 Master Mode (Half-Duplex,
Transmit Only) Requirements........................... 399
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 0, CKP = 0, SMP = 0) Requirements .... 409
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 0, CKP = 1, SMP = 0) Requirements .... 407
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 1, CKP = 0, SMP = 0) Requirements .... 403
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 1, CKP = 1, SMP = 0) Requirements .... 405
SPI3 Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) Requirements .................... 413
SPI3 Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) Requirements .................... 412
SPI3 Master Mode (Half-Duplex,
Transmit Only) Requirements........................... 411
SPI3 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) Requirements.................... 421
SPI3 Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) Requirements.................... 419
SPI3 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) Requirements.................... 415
SPI3 Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) Requirements.................... 417
Temperature and Voltage Specifications .................. 387
Timer1 External Clock Requirements ....................... 393
Timer2/Timer4 External Clock Requirements ........... 394
Timer3/Timer5 External Clock Requirements ........... 394
UARTx I/O Requirements ......................................... 427
AC/DC Characteristics
DACx Specifications ................................................. 431
High-Speed Analog Comparator Specifications........ 430
PGAx Specifications ................................................. 432
Analog-to-Digital Converter. See ADC.
Arithmetic Logic Unit (ALU)................................................. 30
Assembler
MPASM Assembler .................................................. 372
MPLAB Assembler, Linker, Librarian........................ 372
B
Bit-Reversed Addressing.................................................... 56
Example...................................................................... 57
Implementation ........................................................... 56
Sequence Table (16-Entry) ........................................ 57
Block Diagrams
16-Bit Timer1 Module ............................................... 169
ADC Module ............................................................. 274
Addressing for Table Registers .................................. 61
CALL Stack Frame ..................................................... 52
CANx Module ........................................................... 308
CLCx Input Source Selection ................................... 261
CLCx Logic Function Combinatorial Options............ 260
CLCx Module............................................................ 259
Connections for On-Chip Voltage Regulator ............ 355
Constant-Current Source.......................................... 345
CPU Core ................................................................... 22
Data Access from Program Space
Address Generation............................................ 58
Dedicated ADC Cores 0-3 ........................................ 275
DMA Controller ........................................................... 91
dsPIC33EPXXGS70X/80X Family.............................. 11
High-Speed Analog Comparator x............................ 334
High-Speed PWM Architecture................................. 189
Hysteresis Control .................................................... 336
I2Cx Module ............................................................. 246
Input Capture x......................................................... 177
Interleaved PFC.......................................................... 18
MCLR Pin Connections .............................................. 16
Multiplexing Remappable Outputs for RPn .............. 138
Off-Line UPS .............................................................. 20
Oscillator System...................................................... 104
Output Compare x Module ....................................... 181
Peripheral to DMA Controller...................................... 89
PGAx Functions........................................................ 342
PGAx Module ........................................................... 341
Phase-Shifted Full-Bridge Converter.......................... 19
PLL Module .............................................................. 105
Programmer’s Model .................................................. 24
PSV Read Address Generation.................................. 49
PTG Module ............................................................. 214
Recommended Minimum Connection ........................ 16
Remappable Input for U1RX .................................... 136
Reset System ............................................................. 69
Security Segments for dsPIC33EP128GS70X/80X
(Dual Partition Modes)...................................... 359
Security Segments for dsPIC33EP64GS70X/80X
(Dual Partition Modes)...................................... 358
Security Segments for
dsPIC33EPXXXGS70X/80X............................. 358
Shared ADC Core..................................................... 275
Shared Port Structure............................................... 125
Simplified Conceptual of High-Speed PWM ............. 190
SPIx Master, Frame Master Connection .................. 243
SPIx Master, Frame Slave Connection .................... 244
SPIx Master/Slave Connection
(Enhanced Buffer Modes)................................. 243
SPIx Master/Slave Connection (Standard Mode)..... 242
SPIx Module (Enhanced Mode)................................ 231
SPIx Module (Standard Mode) ................................. 230