ams Datasheet Page 1
[v1-04] 2014-Oct-31 Document Feedback
AS5047D
14-bit On-Axis Magnetic Rotary
Position Sensor with 11-bit Decimal &
Binary Incremental Pulse Count
The AS5047D is a high-resolution rotary position sensor for fast
absolute angle measurement over a full 360-degree range. This
new position sensor is equipped with revolutionary integrated
dynamic angle error compensation (DAEC™) with almost 0
latency and offers a robust design that suppresses the influence
of any homogenous external stray magnetic field.
A standard 4-wire SPI serial interface allows a host
microcontroller to read 14-bit absolute angle position data
from the AS5047D and to program non-volatile settings
without a dedicated programmer.
Incremental movements are indicated on a set of ABI signals
with a maximum resolution of 2000 steps / 500 pulses per
revolution in decimal mode and 2048 steps / 512 pules per
revolution in binary mode. The resolution of the ABI signal is
programmable and can be reduced to 32 steps per revolution,
or 8 pulses per revolution.
Brushless DC (BLDC) motors are controlled through a standard
UVW commutation interface with a programmable number of
pole pairs from 1 to 7. The absolute angle position is also
provided as PWM-encoded output signal
The AS5047D is available as a single die in a compact 14-pin
TSSOP package.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of AS5047D, 14-bit On-Axis Magnetic
Rotary Position Sensor with 11-bit Decimal & Binary
Incremental Pulse Count are listed below:
Figure 1:
Added Value of Using the AS5047D
Benefits Features
Easy to use – saving costs on DSP DAEC™ Dynamic angle error compensation
Good resolution for motor & position control 14-bit core resolution
Simple optical encoder replacement ABI programmable decimal and binary pulse-count:
500, 400, 300, 200, 100, 50, 25, 8, 512, 256 ppr
No programmer needed (via SPI command) Zero position, configuration programmable
Versatile choice of the interface Independent output interfaces: SPI, ABI, UVW, PWM
General Description
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AS5047D − General Description
Applications
The AS5047D is ideally suited to support BLDC motor
commutation for the most challenging industrial applications
such as factory automation, building automation, robotics,
PMSM (permanent magnet synchronous motor) and stepper
motors closed loop in as well optical encoder replacement.
Block Diagram
The functional blocks of this device for reference are
shown below:
Figure 2:
AS5047D Block Diagram
Lower system costs (no shielding) Immune to external stray field
Benefits Features
VDD3V3
A/D
Volatile Memory
SPI
LDO
AS5047D
VDD
GND
CSn
MOSI
SCL
MISO
I/PWM
A
B
W / PWM
U
V
Analog
Front-End
UWV
ATAN
(CORDIC)
AGC
OTP
INTERPOLATOR
Hall
Sensors
PWM Decoder
Selectable
on I or W
ABI
Dynamic Angle
Error
Compensation
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AS5047D − Pin Assignment
Figure 3:
TSSOP-14 Pin Assignment
Figure 4:
Pin Description
Pin Number Pin Name Pin Type Description
1 CSn Digital input SPI chip select (active low)
2CLKDigital inputSPI clock
3 MISO Digital output SPI master data input, slave output
4 MOSI Digital input SPI master data output, slave input
5 Test Test pin (connect to ground)
6 B Digital output Incremental signal B
7 A Digital output Incremental signal A
Pin Assignment
AS5047D
CSn
CLK
MISO
MOSI
TEST
B
A
I / PWM
GND
VDD3V
VDD
U
V
W / PWM
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AS5047D − Pin Assignment
Note(s) and/or Footnote(s):
1. Floating state of a digital input is not allowed.
2. If SPI is not used, an Pull up resistor on CSn is required.
3. If SPI is not used, an Pull down resistor on CLK is required.
8 W/PWM Digital output Commutation signal W or PWM
9 V Digital output Commutation signal V
10 U Digital output Commutation signal U
11 VDD Power supply 5V power supply voltage for on-chip regulator
12 VDD3V3 Power supply 3.3V on-chip low-dropout (LDO) output. Requires an
external decoupling capacitor (1uF)
13 GND Power supply Ground
14 I Digital output Incremental signal I (index) or PWM
Pin Number Pin Name Pin Type Description
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AS5047D − Absolute Maximum Ratings
Stresses beyond those listed under
“Absolute Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only. Functional operation
of the device at these or any other conditions beyond those
indicated under “Electrical Characteristics” is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Figure 5:
Absolute Maximum Ratings
Symbol Parameter Min Max Units Note
VDD5 DC supply voltage at VDD pin -0.3 7.0 V
VDD3 DC supply voltage at VDD3V3
pin -0.3 5.0 V
VSS DC supply voltage at GND pin -0.3 0.3 V
Vin Input pin voltage VDD+0.3 V
Iscr Input current
(latch-up immunity) -100 100 mA Norm: AEC-Q100-004
ESD Electrostatic discharge ±2 kV Norm: AEC-Q100-002
PtTotal power dissipation
(all supplies and outputs) 150 mW
Ta5V0 Ambient temperature 5V0 -40 125 °C In the 5.0V power supply mode
only
Ta3V3 Ambient temperature 3V3 -40 125 °C In the 3.3V power supply mode if
NOISESET = 0
TaProg Programming Temperature 5 45 °C Programming @
Roomtemperature (25°C ± 20°C)
Tstrg Storage temperature -55 150 °C
Tbody Package body temperature 260 °C Norm: IPC/JEDEC J-STD-020
Humidity non-condensing 5 85 %
Moisture sensitivity level 3 Represents a maximum floor
lifetime of 168h
Absolute Maximum Ratings
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AS5047D − Electrical Characteristics
All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or SQC (Statistical
Quality Control) methods.
Figure 6:
Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
VDD Positive supply voltage 5.0V operation mode 4.5 5.0 5.5 V
VDD3V3 Positive supply voltage 3.3V operation mode; only
from -40 to 125°C 3.0 3.3 3.6 V
VDD_Burn Positive supply voltage
Supply voltage required
for programming in 3.3V
operation
3.3 3.5 V
VREG Regulated Voltage Voltage at VDD3V3 pin if
VDD ≠ VDD3V3 3.2 3.4 3.6 V
VporON Internal POR-ON level 3V operation. Pin VDD5 &
VDD3 shorted 2.3 2.85 V
VporOFF Internal POR-OFF level 3V operation. Pin VDD5 &
VDD3 shorted 2.05 2.65 V
Vporh Internal POR hysteresis 150 300 mV
IDD Supply current 15 mA
VIH High-level input
voltage 0.7×VDD V
VIL Low-level input voltage 0.3×VDD V
VOH High-level output
voltage VDD-0.5 V
VOL Low-level output
voltage VSS+0.4 V
I_Out Current on digital
output 1mA
C_L Capacitive load on
digital output 50 pf
Electrical Characteristics
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AS5047D − Magnetic Characteristics
Figure 7:
Magnetic Specifications
Note(s) and/or Footnote(s):
1. it is possible to operate the AS5047D below 35mT with reduced noise performance.
Figure 8:
System Specifications
Symbol Parameter Conditions Min Max Unit
Bz
Orthogonal magnetic field
strength, normal operating
mode
Required orthogonal component of the
magnetic field strength measured at the
die's surface along a circle of 1.1mm
35 70 mT
Symbol Parameter Conditions Min Typ Max Units
RES Core resolution 14 bit
RES_ABI Resolution of the ABI
interface
Programmable with register
setting (ABIRES)32 2048 Steps per
revolution
INLOPT @
25°C
Non-linearity, optimum
placement of the
magnet
±0.8 Deg
INLOPT+TEMP
Non-linearity optimum
placement of the
magnet over the full
Temperature Range
±1 Deg
INLDIS+TEMP
Non-linearity @
displacement of
magnet and
temperature -40°C to
150°C
Assuming N35H Magnet
(D=8mm, H=3mm) 500um
displacement in x and y
z-distance @ 2000um
±1.2 Deg
ONL
RMS output noise
(1 sigma). Not tested,
guaranteed by design.
Orthogonal component for
the magnetic field within the
specified range (Bz),
NOISESET = 0
0.068 degree
ON_PWM
RMS output noise
(1 sigma) on PWM
interface
Orthogonal component for
the magnetic field within the
specified range (Bz)
0.068 degree
tdelay System propagation
delay –core Reading angle via SPI 90 110 μs
Magnetic Characteristics
System Characteristics
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AS5047D − Timing Characteristics
Reference magnet: N35H, 8mm diameter; 3mm thickness.
Figure 9:
Timing Specifications
tdelay_
DAEC
System propagation
delay after dynamic
angle error correction.
At ABI and UVW interfaces 1.5 1.9 μs
tsampl Sampling rate Refresh rate at SPI 225 250 275 ns
DAE1700 Dynamic angle error At 1700 RPM constant speed 0.02 degree
DAEmax Dynamic angle error At 14500 RPM constant
speed 0.18 degree
DAEacc
Dynamic angle error at
constant acceleration
(25krad/s²)
25k radians/s² constant
acceleration 0.175 degree
MS Maximum speed 14500 RPM
Symbol Parameter Conditions Min Typ Max Units
tpon Power-on time Not tested, guaranteed by
design. 10 ms
Symbol Parameter Conditions Min Typ Max Units
Timing Characteristics
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AS5047D − Detailed Description
The AS5047D is a Hall-effect magnetic sensor using a CMOS
lateral technology. The lateral Hall sensors convert the
magnetic field component perpendicular to the surface of the
chip into a voltage.
The signals from the Hall sensors are amplified and filtered by
the analog front-end (AFE) before being converted by the
analog-to-digital converter (ADC). The output of the ADC is
processed by the hardwired CORDIC (coordinate rotating
digital computer) block to compute the angle and magnitude
of the magnetic vector. The intensity of the magnetic field
(magnitude) is used by the automatic gain control (AGC) to
adjust the amplification level for compensation of the
temperature and magnetic field variations.
The internal 14-bit resolution is available by reading a register
through the SPI interface. The resolution on the ABI output can
be programmed from 2048 to 32 steps per revolution.
The Dynamic Angle Error Compensation block corrects the
calculated angle for latency using a linear prediction
calculation algorithm. At constant rotation speed the latency
time is internally compensated by the AS5047D, reducing the
dynamic angle error at the SPI, ABI and UVW outputs. The
AS5047D allows to switch OFF the UVW output interface to
display the absolute angle as PWM-encoded signal on the
pin W.
At higher speeds, the interpolator fills in missing ABI pulses and
generates the UVW signals with no loss of resolution. The
non-volatile settings in the AS5047D can be programmed
through the SPI interface without any dedicated programmer.
Power Management
The AS5047D can be either powered from a 5.0V supply using
the on-chip low-dropout regulator or from a 3.3V voltage
supply. The LDO regulator is not intended to power any other
loads, and it needs a 1 μF capacitor to ground located close to
the chip for decoupling as shown in Figure 10.
In 3.3V operation, VDD and VREG must be tied together.
Figure 10:
5.0V and 3.3V Power Supply Options
Detailed Description
1µF
100nF
4.5 - 5.5V VDD3V3
GND
VDD
5.0V Operation
LDO
AS5047D
100nF
3.0 – 3.6V VDD3V3
GND
VDD
3.3V Operation
LDO
AS5047D
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AS5047D − Detailed Description
After applying power to the chip, the power-on time (tpon) must
elapse before the AS5047D provides the first valid data.
Dynamic Angle Error Compensation
The AS5047D uses 4 integrated Hall sensors which produce a
voltage proportional to the orthogonal component of the
magnetic field to the die. These voltage signals are amplified,
filtered, and converted into the digital domain to allow the
CORDIC digital block to calculate the angle of the magnetic
vector. Propagation of these signals through the analog
front-end and digital back-end generates a fixed delay between
the time of measurement and the availability of the measured
angle at the outputs. This latency generates a dynamic angle
error represented by the product of the angular speed (ω)and
the system propagation delay (tdelay):
DAE =
ω
x tdelay
The dynamic angle compensation block calculates the current
magnet rotation speed (ω) and multiplies it with the system
propagation delay (tdelay) to determine the correction angle to
reduce this error. At constant speed, the residual system
propagation delay is tdelay_DAEC.
The angle represented on the PWM interface is not
compensated by the Dynamic Angle Error Compensation
algorithm. it is also possible to disable the Dynamic Angle Error
Compensation with the setting DAECDIS. Disabling the
Dynamic Angle Error Compensation gives a noise benefit of
0.016 degree rms.This setting can be advantageous for low
speed (under 100rpm) respectively static positioning
applications.
SPI Interface (slave)
The SPI interface is used by a host microcontroller (master) to
read or write the volatile memory as well as to program the
non-volatile OTP registers. The AS5047D SPI only supports slave
operation mode. It communicates at clock rates up to 10 MHz.
The AS5047D SPI uses mode=1 (CPOL=0, CPHA=1) to exchange
data. As shown in Figure 11, a data transfer starts with the
falling edge of CSn (SCL is low). The AS5047D samples MOSI
data on the falling edge of SCL. SPI commands are executed at
the end of the frame (rising edge of CSn). The bit order is MSB
first. Data is protected by parity.
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AS5047D − Detailed Description
SPI Timing
The AS5047D SPI timing is shown in Figure 11.
Figure 11:
SPI Timing Diagram
Figure 12:
SPI Timing
Parameter Description Min Max Units
tLTime between CSn falling edge and CLK rising edge 350 ns
tclk Serial clock period 100 ns
tclkL Low period of serial clock 50 ns
tclkH High period of serial clock 50 ns
tHTime between last falling edge of CLK and rising
edge of CSn tclk / 2 ns
tCSn High time of CSn between two transmissions 350 ns
tMOSI Data input valid to falling clock edge 20 ns
tMISO CLK edge to data output valid 51 ns
tOZ Release bus time after CS rising edge. 10 ns
CSn
(Input)
CLK
(Input)
MOSI
(Input)
MISO
(Output)
tclk
tL
tMOSI
tMISO tOZ
tOZ
tH
tCSn
tclkL tclkH
Data[15]
Data[15] Data[14]
Data[14]
Data[0]
Data[0]
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AS5047D − Detailed Description
SPI Transaction
An SPI transaction consists of a 16-bit command frame followed
by a 16-bit data frame. Figure 13 shows the structure of the
command frame.
Figure 13:
SPI Command Frame
To increase the reliability of communication over the SPI, an
even parity bit PARC must be generated and sent. A wrong
setting of the parity bit causes the PARERR bit in the error flag
register to be set. The parity bit is calculated from the 16-bit
command frame. The 16-bit command specifies whether the
transaction is a read or a write and the address. Figure 14 shows
the read data frame.
Figure 14:
SPI Read Data Frame
The data is sent on the MISO pin. The parity bit PARD is
calculated by the AS5047D for the 16-bit data frame. If an error
is detected in the previous SPI command frame, the EF bit is set
high. The SPI read is sampled on the rising edge of CSn and the
data is transmitted on MISO with the next read command, as
shown in Figure 15.
Bit Name Description
15 PARC Parity bit (even) calculated on the command frame
14 R/W 0: Write
1: Read
13:0 ADDR Address to read or write
Bit Name Description
15 PARD Parity bit (even) for the data frame
14 EF 0: No command frame error occurred
1: Error occurred
13:0 DATA Data
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AS5047D − Detailed Description
Figure 15:
SPI Read
Figure 16:
SPI Write Data Frame
The parity bit PARD must be calculated from the 16-bit data.
In an SPI write transaction, the write command frame (e.g. Write
ADD[n]) is followed by a data frame (e.g. DATA [x]). In addition
to writing an address in the AS5047D, a write command frame
causes the old contents of the addressed register (e.g. DATA [y])
to be sent on MISO in the following frame. This is followed by
the new contents of the addressed register (DATA [x]) as shown
in Figure 18.
Bit Name Description
15 PARD Parity bit (even)
14 0 Always low
13:0 DATA Data
Read ADD[n] Read ADD[k]
CSn
Read ADD[p]
Data ADD[n] Data ADD[p]
Read ADD[m]
Data ADD[k]
Command CommandCommand Command
Data DataData
MOSI
MISO
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AS5047D − Detailed Description
Figure 17:
SPI Write Transaction
Volatile Registers
The volatile registers are shown in Figure 18. Each register has
a 14-bit address.
Figure 18:
Volatile Register Table
Reading the NOP register is equivalent to a nop (no operation)
instruction for the AS5047D.
Address Name Default Description
0x0000 NOP 0x0000 No operation
0x0001 ERRFL 0x0000 Error register
0x0003 PROG 0x0000 Programming register
0x3FFC DIAAGC 0x0180 Diagnostic and AGC
0x3FFD MAG 0x0000 CORDIC magnitude
0x3FFE ANGLEUNC 0x0000 Measured angle without dynamic angle
error compensation
0x3FFF ANGLECOM 0x0000 Measured angle with dynamic angle error
compensation
Write ADD[n]
CSn
MOSI
MISO
DATA (x)
DATA (y)
Write (ADDm)
DATA (p)
Next command
DATA (y)
DATA (y)
DATA (x)
Command Command Command
Data to write into ADD[n]
Data content of ADD[n] New Data content
of ADD[n] Data content of ADD[m] New Data content
of ADD[m]
Data to write into ADD[n]
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AS5047D − Detailed Description
Figure 19:
ERRFL (0x0001)
Reading the ERRFL register automatically clears its contents
(ERRFL=0x0000).
Figure 20:
PROG (0x0003)
The PROG register is used for programming the OTP memory.
(See programming the zero position.)
Figure 21:
DIAAGC (0x3FFC)
Name Read/Write Bit Position Description
PARERR R 2 Parity error
INVCOMM R 1 Invalid command error: set to 1 by reading or writing
an invalid register address
FRERR R 0 Framing error: is set to 1 when a non-compliant SPI
frame is detected
Name Read/Write Bit Position Description
PROGVER R/W 6 Program verify: must be set to 1 for verifying the
correctness of the OTP programming
PROGOTP R/W 3 Start OTP programming cycle
OTPREF R/W 2 Refreshes the non-volatile memory content with the
OTP programmed content
PROGEN R/W 0 Program OTP enable: enables programming the entire
OTP memory
Name Read/Write Bit Position Description
MAGH R 11 Diagnostics: Magnetic field strength too low; AGC=0xFF
MAGL R 10 Diagnostics: Magnetic field strength too high; AGC=0x00
COF R 9 Diagnostics: CORDIC overflow
LF R 8
Diagnostics: Offset compensation
LF=0:internal offset loops not ready regulated
LF=1:internal offset loop finished
AGC R 7:0 Automatic gain control value
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AS5047D − Detailed Description
Figure 22:
MAG (0x3FFD)
Figure 23:
ANGLE (0x3FFE)
Figure 24:
ANGLECOM (0x3FFF)
Non-Volatile Registers (OTP)
A nonvolatile memory (One-Time Programmable) is used store
the zero position of the magnet and custom settings.
Figure 25:
Non-Volatile Register Table
Figure 26:
ZPOSM (0x0016)
Name Read/Write Bit Position Description
CMAG R 13:0 CORDIC magnitude information
Name Read/Write Bit Position Description
CORDICANG R 13:0 Angle information without dynamic angle error
compensation
Name Read/Write Bit Position Description
DAECANG R 13:0
Angle information with dynamic angle error
compensation
Address Name Default Description
0x0016 ZPOSM 0x0000 Zero position MSB
0x0017 ZPOSL 0x0000 Zero position LSB /MAG diagnostic
0x0018 SETTINGS1 0x0000 Custom setting register 1
0x0019 SETTINGS2 0x0000 Custom setting register 2
0x001A RED 0x0000 Redundancy register
Name Read/Write/Program Bit Position Description
ZPOSM R/W/P 7:0 8 most significant bits of the zero position
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AS5047D − Detailed Description
Figure 27:
ZPOSL (0x0017)
Figure 28:
SETTINGS1 (0x0018)
Name Read/Write/Program Bit Position Description
ZPOSL R/W/P 5:0 6 least significant bits of the zero position
comp_l_error_en R/W/P 6
This bit enables the contribution of
MAGH (Magnetic field strength too high)
to the system_error
comp_h_error_en R/W/P 7
This bit enables the contribution of MAGL
(Magnetic field strength too low) to the
system_error
Name Read/Write/Program Bit Position Description
Factory
Setting R 0 Pre-Programmed to 1
NOISESET R/W/P 1 Noise setting
DIR R/W/P 2 Rotation direction
UVW_ABI R/W/P 3
Defines the PWM Output
(0 = ABI is operating, W is used as PWM
1 = UVW is operating, I is used as PWM)
DAECDIS R/W/P 4
Disable Dynamic Angle Error Compensation
(0 = DAE compensation ON, 1 = DAE
compensation OFF)
ABIBIN R/W/P 5 ABI decimal or binary selection of the ABI
pulses per revolution
Dataselect R/W/P 6
This bit defines which data can be read form
address 16383dec (3FFFhex).
0->DAECANG
1->CORDICANG
PWMon R/W/P 7 enables PWM (setting of UVW_ABI Bit
necessary)
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AS5047D − Detailed Description
Figure 29:
SETTINGS2 (0x0019)
Figure 30:
RED (0x001A)
Name Read/Write/Program Bit Position Description
UVWPP R/W/P 2:0
UVW number of pole pairs
(000 = 1, 001 = 2, 010 = 3, 011 = 4, 100 = 5, 101 =
6, 110 = 7, 111 = 7)
HYS R/W/P 4:3 Hysteresis setting
ABIRES R/W/P 7:5 Resolution of ABI
Name Read/Write/Program Bit Position Description
REDUNDANCY R/W/P 4:0
Redundancy bits. This field enables with
force to high one bit of the Non-Volatile
register map after a non-successful
burning. For more details please refer to
the application note
“AN5000 – AS5147_Redundancy_Bits”
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AS5047D − Detailed Description
ABI Incremental Interface
The AS5047D can send the angle position to the host
microcontroller through an incremental interface. This
interface is available simultaneously with the other interfaces.
By default, the incremental interface is set to work at the highest
resolution 2000 step per revolution, or 500 pulses per
revolution (ppr). It is possible to select between a decimal and
binary pulses per revolution, respectively with the bit ABIBIN
and select the pulses per revolution with the bit ABIRES as
shown in Figure 31.
Figure 31:
ABI Resolution Setting
The phase shift between the signals A and B indicates the
rotation direction: e.g. DIR-Bit = 0, clockwise (A leads, B follows)
or counterclockwise (B leads, A follows). During the start-up
time, after power on to the chip, all three ABI signals are high.
ABIRES ABIBIN Steps per revolution Pulses per revolution
000 0 2000 500
001 0 1600 400
010 0 1200 300
011 0 800 200
100 0 400 100
101 0 200 50
110 0 100 25
111 0 32 8
000 1 2048 512
001 1 1024 256
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AS5047D − Detailed Description
Figure 32:
ABI Signals at 11-Bit Resolution
The Figure 32 shows the ABI signal flow if the magnet rotates
in clockwise direction, placing the magnet on the top of the
AS5047D and looking at the magnet from the top (DIR=0). With
the bit DIR, it is possible to invert the rotation direction.
012345678N-1N-2N-3N-4N-5N-6 1234567 0 N-1 N-2 N-3 N-4
A
B
I
N-7
Steps
Clockwise rotation Counter-clockwise rotation
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AS5047D − Detailed Description
UVW Commutation Interface
The AS5047D can emulate the UVW signals generated by the
three discrete Hall switches commonly used in BLDC motors.
The UVWPP field in the SETTINGS register selects the number
of pole pairs of the motor (from 1 to 7 pole pairs). The UVW
signals are generated with 14-bit resolution.
During the start-up time, after power on of the chip, the UVW
signals are low.
Figure 33:
UVW Signals
The Figure 33 shows the UVW signal flow if the magnet rotates
in clockwise direction, placing the magnet on the top of the
AS5047D and looking at the magnet from the top (DIR=0). With
the bit DIR, it is possible to invert the rotation direction.
U
V
W
Electrical
Angle
0° 60° 180° 240°120° 300° 360°
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AS5047D − Detailed Description
PWM
The PWM can be enabled with the bit setting PWMon. The PWM
encoded signal is displayed on the pin W or the pin I. The bit
setting UVW_ABI defines which output is used as PWM.The
PWM output consists of a frame of 4119 PWM clock periods, as
shown in Figure 34. The PWM frame has the following sections:
• 12 PWM Clocks for INIT
• 4 PWM Clocks for Error detection
• 16 PWM clock periods high
• 4095 PWM clock periods of data
• 8 PWM clock periods low
The angle is represented in the data part of the frame with a
12-bit resolution. One PWM clock period represents 0.088
degree and has a typical duration of 444 ns.
If the embedded diagnostic of the AS5047D detects any error
the PWM interface displays only 12 clock periods high
(0.3% duty-cycle).
Figure 34:
Pulse Width Modulation Encoded Signal
time
0
1
2
3
4
5
6
7
8
4095
4094
4093
4092
4091
4090
4089
data 8 clock pulse
low
16 clock pulse
high
Init
Error_n
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AS5047D − Detailed Description
Hysteresis
The hysteresis can be programmed in the HYS bits if the
SETTINGS2 register and depends on the chosen resolution of
the incremental interface (ABIRES), as shown in the Figure 35.
Figure 35:
Hysteresis Settings
Automatic Gain Control (AGC) and CORDIC
Magnitude
The AS5047D uses AGC to compensate for variations in the
magnetic field strength due to changes of temperature, air gap
between the chip and the magnet, and demagnetization of the
magnet. The automatic gain control value can be read in the
AGC field of the DIAAGC register. Within the specified input
magnetic field strength (Bz), the Automatic Gain Control works
in a closed loop and keeps the CORDIC magnitude value (MAG)
constant. Below the minimum input magnetic field strength,
the CORDIC magnitude decreases and the MAGL bit is set.
Diagnostic Features
The AS5047D supports embedded self-diagnostics.
MAGL: magnetic field strength too high, set if AGC = 0xFF. This
indicates the non-linearity error may be increased.
MAGH: magnetic field strength too low, set if AGC = 0x00. This
indicates the output noise of the measured angle may be
increased.
COF: CORDIC overflow. This indicates the measured angle is not
reliable.
LF: offset compensation completed. At power-up, an internal
offset compensation procedure is started, and this bit is set
when the procedure is completed.
HYS Hysteresis (degree) - ABIRES ≥
1600 steps per revolution
Hysteresis (degree) - ABIRES ≤
1024 steps per revolution
00 0.53 0.7
01 0.35 0.35
10 0.175 no hysteresis
11 no hysteresis 1.05
Page 24 ams Datasheet
Document Feedback [v1-04] 2014-Oct-31
AS5047D − Detailed Description
OCF Error / COF Error
In case of an OCF or COF error, all outputs are changing into a
safe state:
SPI Output: Information in the DIAAGC (0x3FFC) register. The
angle information is still valid.
PWM Output: PWM Clock Period 13 - 16 of the first 16 PWM Clock
Periods = low. Additional there is no angle information valid
(all 4096 clock periods = low)
ABI Output : The state of ABI is frozen to ABI = 111
UVW Output : The state of UVW is frozen to UVW = 000
MAGH Error /MAGL Error
Default diagnostic setting for MAGH error /MAGL error:
In case of a MAGH error or MAGL error, there is no safe state on
the PWM,ABI or UVW outputs if comp_h_error_en= 0 &
comp_h_error_en = 0. The device is operating with the
performance as explained.
The error flags can be read out with the DIAAGC (0x3FFC)
register.
Enhanced diagnosis setting for MAGH error / MAGL error:
In case of a MAGH error or MAGL error, the PWM,ABI or UVW
outputs are going into a safe state if comp_h_error_en= 1 &
comp_h_error_en = 1.
SPI Output: Information in the DIAAGC (0x3FFC) register. The
angle information is still valid, if the MAGH or MAGL error flag
is on.
PWM Output: PWM Clock Period 13 - 16 of the first 16 PWM Clock
Periods = low. Additional there is no angle information valid (all
4096 clock periods = low)
ABI Output : The state of ABI is frozen to ABI = 111
UVW Output : The state of UVW is frozen to UVW = 000
Important: When comp_(h/l)_error_en is enabled a marginal
magnetic field input can cause toggling of MAGH or MAGL
which will lead to toggling of the ABI/UVW outputs between
operational mode and failure mode.
ams Datasheet Page 25
[v1-04] 2014-Oct-31 Document Feedback
AS5047D − Application Information
Burn and Verification of the OTP Memory
Step-by-step procedure to permanently program the
non-volatile memory (OTP):
Figure 36:
Minimum Programming Diagram for the AS5047D in 5 V Operation
Note(s) and/or Footnote(s):
1. In terms of EMC and for remote application, additional circuits are necessary.
Application Information
AS5047D
CSn
CLK
MISO
MOSI
TEST
A
B
GND
VDD3V
VDD
U
V
W
VDD during programming 4.5 – 5.5V
1μF
100nF
Programmer
VDD
GND
I
5V operation
Page 26 ams Datasheet
Document Feedback [v1-04] 2014-Oct-31
AS5047D − Application Information
Figure 37:
Minimum Programming Diagram for the AS5047D in 3.3V Operation
Note(s) and/or Footnote(s):
1. In terms of EMC and for remote application, additional circuits are necessary.
Figure 38:
Programming Parameter
Symbol Parameter Conditions Min Typ Max Units
TaProg Programming
temperature
Programming @ Room
Temperature
(25°C +-20°C
545°C
VDD Positive supply
voltage
5 V operation mode. Supply
voltage during
programming
4.555.5V
VDD Positive supply
voltage
3.3 V operation mode.
Supply voltage during
programming
3.3 3.5 V
IProg Current for
programming
max current during OTP burn
procedure. 100 mA
AS5047D
CSn
CLK
MISO
MOSI
TEST
A
B
GND
VDD3V
VDD
U
V
W
VDD during programming: 3.3V – 3.5V
100nF
Programmer
VDD
GND
I
3.3V operation
ams Datasheet Page 27
[v1-04] 2014-Oct-31 Document Feedback
AS5047D − Application Information
The programming can either be performed in 5V operation
using the internal LDO (1uF on regulator output pin), or in 3V
Operation but using a supply voltage between 3.3V and 3.5V.
1. Power on cycle
2. Write the SETTINGS1 and SETTINGS2 registerswith the
Custom settings for this application (Bit0 of Settings1 is
a factory bit. For programming its mandatory to set this
bit to 0).
3. Position the magnet at the desired zero position
4. Read out the measured angle from the ANGLE register
5. Write ANGLE [5:0] into the ZPOSL register and ANGLE
[13:6] into the ZPOSM register
6. Read reg(0x0016) to reg(0x0019) → Read register step1
7. Comparison of written content (settings and angle) with
content of read register step1 (Removing of Bit0 of
Settings1 from the comparison is mandatory. Bit0 is
preprogrammed)
8. If point 7 is correct, enable OTP read / write by setting
PROGEN = 1 in the PROG register
9. Start the OTP burn procedure by setting PROGOTP = 1
in the PROG register
10. Read the PROG register until it reads 0x0000
(Programming procedure complete)
11. Clear the memory content writing 0x00 in the whole
non-volatile memory
12. Enable OTP read / write by setting PROGEN = 1 in the
PROG register
13. Set the PROGVER = 1 to set the Guard band for the guard
band test(1).
14. Refresh the non-volatile memory content with the OTP
content by setting OTPREF = 1
15. Read reg(0x0016) to reg(0x0019) → Read register step2
16. Comparison of written content (settings and angle) with
content of read register step2.
Mandatory: guard band test (Removing of Bit0 of
Settings1 from the comparison is mandatory. Bit0 is
preprogrammed)
Page 28 ams Datasheet
Document Feedback [v1-04] 2014-Oct-31
AS5047D − Application Information
17. New power on cycle, if point 16 is correct. If point 16
fails, the test with the guard band test1 was not
successful and the device is incorrectly programmed. A
reprogramming is not allowed!
18. Read reg(0x0016) to reg(0x0019) → Read register step3
19. Comparision of written content (settings and angle)
with content of read register step3(Removing of Bit0 of
Settings1 from the comparison is mandatory. Bit0 is
preprogrammed).
20. If point 19 is correct, the programming was successful.
If point 19 fails, device is incorrectly programmed. A
reprogramming is not allowed
1. Guard band test:
- Restricted to temperature range: 25 °C ± 20 °C
- Right after the programming procedure (max. 1 hour with same
- Conditions 25°C ± 20 °C)
- Same VDD voltage
The guard band test is only for the verification of the burned OTP fuses during the programming sequence.
A use of the guard band in other cases is not allowed.
ams Datasheet Page 29
[v1-04] 2014-Oct-31 Document Feedback
AS5047D − Application Information
Figure 39:
OTP Memory Burn and Verification Flowchart
correct
START
Write reg(0x0018)
Write reg(0x0019)
Set the magnet to
the zero position
Write
Reg(0x0017(5:0))= reg(0x3FFF(5:0))
Reg(0x0016(7:0))= reg(0x3FFF(13:6))
Read
Reg(0x0016)
Reg(0x0017)
Reg(0x0018)
Reg(0x0019)
Write
Reg(0x0003)=0x08
Write
Reg(0x0016)=0x00
Reg(0x0017)=0x00
Reg(0x0018=0x00
Reg(0x0019)=0x00
Power-on cycle
Read
Reg(0x0016)
Reg(0x0017)
Reg(0x0018)
Reg(0x0016)
Write
Reg(0x0003)=0x40
Verify 2
correct
Read ANGLE
Write Angle into ZPOSL
and ZPOSM
Read reg(0x3FFF)
Read Register step 1
Comparison of written content
(settings and angle) with content
of Read Register step 1*
Unlock OTParea for read/write
(PROGEN=1)
Read OTP_CTRL
Set Guardband
Refresh memory with OTP
content
Read Register step 2
Comparison of written content (settings and
angle) with content of Read Register step 2*
Mandatory Guardband-Test
Read Register step 3
Verify 1
Clear memory
Start OTP burning procedure
(PROGOTP=1)
Power on cycle
AS5047D settings
Position of the magnet to
the zero position
Write
Reg(0x0003)=0x01
Write
Reg(0x0003)=0x08
Read
Reg(0x0003)
Reg(0x0003)=0x00
NO
OTP burning procedure
complete if Reg(0x0003) =0x00
YES
Unlock OTParea for read/write
(PROGEN=1)
Write
Reg(0003)=0x04
Read
Reg(0x0016)
Reg(0x0017)
Reg(0x0018)
Reg(0x0016)
Guardbandtest fails.
Wrong programming.
Reprogramming not allowed
Not correct
Verify 3
Comparison of written content
(settings and angle) with content
of Read Register step 3*
END
Wrong programming
Reprogramming not
allowed
Not correct
END
Correct
programming and
verification
correct
Not correct
* During the comparison the bit0 of settings1 has to be ignored. This bit is pre-programmed.
Page 30 ams Datasheet
Document Feedback [v1-04] 2014-Oct-31
AS5047D − Application Information
Figure 40:
Minimum Circuit Diagram for the AS5047D
Note(s) and/or Footnote(s):
1. In terms of EMC and for remote application, additional circuits are necessary.
AS5047D
CSn
CLK
MISO
MOSI
TEST
A
B
GND
VDD3V
VDD
U
V
W
4.5 – 5.5V
1µF
100nF
MCU
VDD
GND
I
ams Datasheet Page 31
[v1-04] 2014-Oct-31 Document Feedback
AS5047D − Package Drawings & Markings
The axis of the magnet must be aligned over the center of the
package.
Figure 41:
Package Outline Drawing
Note(s) and/or Footnote(s):
1. Dimensioning and tolerancing conform to ASME Y14.5M - 1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. N is the total number of terminals.
Package Drawings & Markings
Symbol Min Nom Max
A--1.20
A1 0.05 - 0.15
A2 0.80 1.00 1.05
b0.19-0.30
c0.09-0.20
D 4.90 5.00 5.10
E - 6.40 BSC -
E1 4.30 4.40 4.50
e - 0.65 BSC -
L 0.45 0.60 0.75
L1 - 1.00 REF -
Symbol Min Nom Max
R0.09- -
R1 0.09 - -
S0.20- -
Θ10º - 8º
Θ2-12 REF-
Θ3-12 REF-
aaa - 0.10 -
bbb - 0.10 -
ccc - 0.05 -
ddd - 0.20 -
N14
Green
RoHS
Page 34 ams Datasheet
Document Feedback [v1-04] 2014-Oct-31
AS5047D − Ordering & Contact Information
Figure 45:
Ordering Information
Online product information is available at:
www.ams.com/AS5047D
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
Ordering
Code Package Marking Delivery Form Delivery
Quantity
AS5047D-ATST TSSOP-14 AS5047D 13’’ Tape&Reel in dry pack 4500
AS5047D-ATSM TSSOP-14 AS5047D 7’’ Tape&Reel in dry pack 500
Ordering & Contact Information
ams Datasheet Page 35
[v1-04] 2014-Oct-31 Document Feedback
AS5047D − RoHS Compliant & ams Green Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
RoHS Compliant & ams Green
Statement
Page 36 ams Datasheet
Document Feedback [v1-04] 2014-Oct-31
AS5047D − Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141
Unterpremstaetten, Austria-Europe. Trademarks Registered. All
rights reserved. The material herein may not be reproduced,
adapted, merged, translated, stored, or used without the prior
written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
Copyrights & Disclaimer
ams Datasheet Page 37
[v1-04] 2014-Oct-31 Document Feedback
AS5047D − Document Status
Document Status Product Status Definition
Product Preview Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Preliminary Datasheet Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Datasheet Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Datasheet (discontinued) Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
Document Status
Page 38 ams Datasheet
Document Feedback [v1-04] 2014-Oct-31
AS5047D − Revision Information
Note(s) and/or Footnote(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Changes from 1-02 (2014-Jun-27) to current revision 1-04 (2014-Oct-31) Page
Added Notes under Figure 4 3
Updated Figure 6 6
Updated Figure 8 7
Updated Figure 9 8
Updated Figure 13 12
Updated text under ABI Incremental Interface section 19
Updated text under Figure 32 20
Updated text under Figure 33 21
Added Figures 36, 37 and 38 25;26
Revision Information
ams Datasheet Page 39
[v1-04] 2014-Oct-31 Document Feedback
AS5047D − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
2 Block Diagram
3 Pin Assignment
5Absolute Maximum Ratings
6 Electrical Characteristics
7 Magnetic Characteristics
7 System Characteristics
8 Timing Characteristics
9 Detailed Description
9Power Management
10 Dynamic Angle Error Compensation
10 SPI Interface (slave)
11 SPI Timing
12 SPI Transaction
14 Volatile Registers
16 Non-Volatile Registers (OTP)
19 ABI Incremental Interface
21 UVW Commutation Interface
22 PWM
23 Hysteresis
23 Automatic Gain Control (AGC) and CORDIC Magnitude
23 Diagnostic Features
24 OCF Error / COF Error
24 MAGH Error /MAGL Error
25 Application Information
25 Burn and Verification of the OTP Memory
31 Package Drawings & Markings
33 Mechanical Data
34 Ordering & Contact Information
35 RoHS Compliant & ams Green Statement
36 Copyrights & Disclaimer
37 Document Status
38 Revision Information
Content Guide
