NC7WB3125L8X(Preliminary) - Fairchild Semiconductor

May 2000

Revised April 2003

NC7WB3125 TinyLogi c



UHS 2-Bit Low Power Bus Switch

NC7WB3125

TinyLogic UHS 2-Bit Low Power Bus Switch

General Description

The NC7WB3125 is a 2-bit ultra high-speed CMOS FET

bus switch with T TL-compatible act ive LOW cont rol inputs.

The low On Resistance of the switch allows inputs to be

connected to outputs with minimal propagation delay and

without generating additional ground bounce noise. The

device is o rgani zed a s a 2-b it switch with indepe ndent b us

enable (OE) controls. When OE is LOW, the switch is ON

and Por t A is con nected to Port B. W hen OE is HI GH, the

switch is OPEN and a high-impedance state exists

between the two ports. Co ntrol inputs t olerate voltages up

to 5.5V independent of VCC.

Features

■Space saving US8 surface mount package

■MicroPak leadless package

■Typical 3Ω switch resistance at 5.0V VCC

■Minimal propagation delay through the switch

■Power down high impedance input/output

■Zero bou nce i n flow through mod e

■TTL compatible active LOW control inputs

■Contro l inputs are overvoltag e tol erant

■Bus switch replacement for Logic x125 part

Ordering Code:

TinyLogic is a regist ered tradem ark of F airc hild Semiconduc t or Corporation.

MircoPak is a trad em ark of Fairchild Sem icond uc t or Corporation.

Product Package Description Supplied AsOrder Package Code

Numbe r Numbe r Top Mark

NC7WB3125K8X MAB08A WB25 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel

NC7WB3125L8X

(Preliminary) MAC08A T4 8-Lead MicroPak, 1.6 mm Wide 5k Units on Tape and Reel

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NC7WB3125

Logic Diagram

Pin Descriptions

Function Table

Connection Diagrams

(Top View)

Pin One Orientation Diagram

AAA represen t s P roduct Code Top Ma rk - s ee orderin g c ode

Note: Orientation of Top Mark determines Pin One location. Read the top

produc t co de mark lef t to right, Pin On e is th e lower lef t pi n (see dia gram).

Pad Assignments for MicroPak

(Top Thru View)

Pin Name Description

ABus A

BBus B

OE Bus Enable Input

Bus Enable Input OE Function

L B Co nnected to A

H Disconnected

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NC7WB3125

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 3)

Note 1: The “Abso lute Maxim um Ratings ” are those val ues beyond w hich

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Char ac teristi c s tables are not guar anteed at the absolute m ax imum r atings.

The “Re comm ended Operat ing Co ndition s” table will de fine th e cond itions

for actu al device operation.

Note 2: The input and output negative voltage ratings may be exceeded if

the in put and output diode current rat ings are observed.

Note 3: Unused logic inputs must be held HIGH or LOW. They may not

float.

DC Electrical Characteristics

Note 4: Measured by the volta ge drop be tween A an d B pins at th e indicate d c urrent thr ough the switch. On R es istanc e is determi ned by the lower of the

voltages on the tw o (A or B) pins.

Note 5: Per TTL drive n input (VIN = 3.4V, control input only). A and B pins do not contribute to ICC.

Supply Voltage ( VCC)−0.5V to +7.0V

DC Switch V oltage (VS)−0.5V to +7.0V

DC Output Voltage (VIN) (Note 2) −0.5V to +7.0V

DC Input Diode Current

(IIK) VIN < 0V −50 mA

DC Output (IOUT) Current 128 mA

DC VCC or Ground Curre nt

(ICC/IGND)±100 mA

Storage Temperature Range (TSTG)−65°C to +150°C

Junction Temperature under Bias (TJ)+150°C

Junction Lead Temperature (TL)

(Soldering, 10 Seconds) +260°C

Power Dissipation (PD) @ +85°C250 mW

Supply Operating (VCC) 4.0V to 5.5V

Control Input Voltage (VIN) 0V to 5.5V

Switch Input Voltage (VIN) 0V to 5.5V

Output Voltage (VOUT) 0V to 5.5V

Operating Temperature (TA)−40°C to +85°C

Input Rise and Fall Time (tr, tf)

Switch Control Input 0 ns/V to 5 ns

Switch I/O 0 ns/V to DC

Thermal Resistance (θJA)250°C/W

Symbol Parameter VCC TA = −40°C to +85°CUnits Conditions

(V) Min Typ Max

VIK Clamp Diode Voltage 4.5 −1.2 V IIN = −18 mA

VIH HIGH Level Input Voltage 4.0 to 5.5 2.0 V

VIL LOW Level Input Voltage 4.0 to 5.5 0.8 V

VOH HIGH Level Output Voltage 4.0 to 5.5 See Figure 3 V VIN = VCC

IIN Input Leakage Current 5.5 ±1.0 µA0 ≤ VIN ≤ 5.5V

IOFF Switch OFF Leakage Current 5.5 ±1.0 µA0 ≤ A, B ≤ VCC

RON Switch On Resistance 4.5 3 7

Ω

VIN = 0V, IIN = 64 mA

(Note 4) 4.5 3 7 VIN = 0V, IIN = 30 mA

4.5 6 15 VIN = 2.4V, IIN = 15 mA

4.0 10 20 VIN = 2.4V, IIN = 15 mA

ICC Quiescent Supply Current 5.5 3 µAV

IN = VCC or GND

IOUT = 0

∆ ICC Increase in ICC per Input (Note 5) 5.5 1 2.5 mA VIN = 3.4V, One OE Input only,

Other OE = VCC

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NC7WB3125

AC Electrical Characteristi cs

Note 6: This p ara meter is g ua rant eed b y de sign . T he bu s s wit ch co ntrib utes no pro pagat ion del ay o ther than the RC d ela y o f the t ypi cal On Resistance of

the sw it c h and the 5 0 pF load capac it ance, when driven by an id eal voltag e s ource (ze ro output im pedance). The specified lim it is ca lc ulated o n t his basis.

Capacitance

AC Loading and Waveforms

Input driven by 50Ω source te rm inated in 50Ω

CL includes load and stray capacitance

Input PRR = 1.0 MHz ; tW = 500 ns

FIGURE 1. AC Test Circuit

FIGURE 2. AC Waveforms

TA = −40°C to +85°C,

Symbol Parameter VCC CL = 50 pF, RU = RD = 500ΩUnits Conditions Figure

(V) Min Typ Max Number

tPHL, Propagation Delay Bus to Bus 4.0 to 5.5 0.25 ns VI = OPEN Figures

1, 2

tPLH (Note 6)

tPZL, Output Enable Time 4.5 to 5.5 0.8 2.5 4.2 ns VI = 7V for tPZL Figures

1, 2

tPZH 4.0 0.8 3.0 4.6 VI = 0V for tPZH

tPLZ, Output Disable Time 4.5 to 5.5 0.8 3.1 4.8 ns VI = 7V for tPLZ Figures

1, 2

tPHZ 4.0 0.8 2.9 4.4 VI = 0V for tPHZ

Symbol Parameter Typ Max Units Conditions

CIN Control Pin Input Capacitance 2.5 pF VCC = 0V

CI/O (OFF) Port Off Capacitance 6 pF VCC = 5.0V = OE

CI/O (ON) Switch ON Capacitance 12 pF VCC = 5.0V, OE = 0V

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NC7WB3125

DC Characterist ics

FIGURE 3. Typical High Level Output Voltage vs. Supply Voltage

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NC7WB3125

Tape and Reel Specification

TAPE FORMAT for US8

TAPE DIMENSIONS inches (millimeters)

TAPE FORM AT for Micr oPak

TAPE DIMENSIONS inches (millimeters)

Package Tape Number Cavity Cover Tape

Designator Section Cavities Status Status

Leader (Start End) 125 (typ) Empty Sealed

K8X Carrier 250 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

Package Tape Number Cavity Cover Tape

Designator Section Cavities Status Status

Leader (Start End) 125 (typ) Empty Sealed

L8X Carrier 250 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

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NC7WB3125

Tape and Reel Specification (Continued)

REEL DIMENSIONS inches (millimeters)

Tape

Size ABCDN W1 W2 W3

8 mm 7.0 0.059 0.512 0.795 2.165 0.331 + 0.059/−0.000 0.567 W1 + 0.078/−0.039

(177.8) (1.50) (13.00) (20.20) (55.00) (8.40 + 1.50/−0.00) (14.40) (W1 + 2.00/−1.00)

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NC7WB3125

Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

Package Number MAB08A

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NC7WB3125 TinyLogi c



UHS 2-Bit Low Power Bus Switch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

8-Lead Micro Pa k, 1.6 mm Wide

Package Number MAC08A

(Preliminary)

Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circu it patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.