Product Brief The Alchemy Au1000TM Internet Edge Processor A High Performance/Low Power MIPS(R) SOC Overview The Alchemy Au1000 is a high performance, low power, high integration system-on-a-chip (SOC) targeting the Internet Edge market. These devices are Customer Premise Equipment (CPE) products, including both wireless, hand-held enterprise PDAs and remote Internet access products, as well as Internet infrastructure products such as routers and line cards. Product Description Alchemy Semiconductor's Au1000 is a complete SOC based on the MIPS32TM instruction set. Designed for maximum performance at very low power, the Au1000 runs up to 500 MHz. Power dissipation is less than a half watt for the 400 MHz version. Highly integrated with on-chip memory controllers and Internet access peripherals, the Au1000 runs a variety of operating systems, including Windows(R) CE, Linux(R) and VxWorks(R). Moreover, the integration of peripherals with Alchemy Semiconductor's unique, very high performance, MIPS-compatible core provides lower system cost, smaller form factor, lower system power requirement, simpler designs at multiple performance points and thus, shorter design cycles. High Speed MIPS CPU Core 266, 400 or 500 MHz MIPS32 Instruction Set 32-Bit Architecture 16KB Instruction and 16KB Data Caches High Speed Multiply-Accumulate (MAC) and Divide unit 1.25-1.8 V Core, 3.3 V I/O Highly-Integrated System Peripherals GPIO (32 total, 6 dedicated) Two 10/100 Ethernet Controllers USB Device and Host Four UARTs IrDA AC'97 Controller I2S Two SSIs High-Bandwidth Memory Buses 100 MHz SDRAM Controller SRAM/Flash EPROM Controller Low System Power Core MHz Power (mW) 266 <300 400 500 500 900 Power-Saving Modes Idle Sleep Pseudo-static design to 0 Hz Package 324 PBGA 23 mm x 23 mm Operating System Support Microsoft Windows(R) CE Linux(R) VxWorks(R) Development Tool Support Complete MIPS32-Compatible Tool Set Numerous 3rd-Party Compilers, Assemblers and Debuggers The Alchemy Au1000TM Internet Edge Processor (R) A High Performance/Low Power MIPS SOC SDRAM SDRAM Controller 16KB Instruction Cache LCD Controller PCMCIA Bus Unit System Bus Enhanced MIPS-32 CPU Core Fast IrDA 16KB Data Cache EJTAG DMA Controller Ethernet MAC Ethernet MAC 32x16 MAC USB-Host Flash SRAM Controller SRAM ROM Peripheral Bus USB-Device RTC (2) X-Bus Power Mgmt SSI (2) Interrupt Control GPIO (32) I2S AC '97 Controller UART (4) Core MicroArchitecture Highlights Pipeline Scalar 5-stage pipeline Load/Store Adder in I-stage Scalar branch techniques optimized Pipelined register file access in fetch stage Zero Penalty Branch Multiply-Accumulate (MAC) and Divide Unit Max Issue Rate of one 32x16 MAC per clock Max Issue Rate of one 32x32 MAC per every other clock Operates in parallel to CPU pipeline Executes all integer multiply and divide instructions 32 x 16-Bit MAC hardware Caches 16KB Non-Blocking Data Cache 16KB Instruction Cache Instruction/Data Caches are 4-way, set-associative Write-Back with Read-Allocate Cache Management Features Programmable allocation policy Line locking Prefetch instructions (instruction and data) High speed access to on-chip buses EJTAG Support Low Power Consumption MMU Instruction and Data Watch Registers for software breakpoints Separate Interrupt Exception Vector TLB 32 dual-entry fully-associative Variable page sizes 4KB-16MB 4-entry ITB Core MHz Core Voltage 266 1.25 400 1.5 500 1.8 Power-Saving Modes Idle Sleep Pseudo-static design to 0 Hz Power (mW) <300 500 900 Alchemy Semiconductor, Inc. www.alchemysemi.com 7800 Shoal Creek Blvd., Suite 222W Austin, Texas 78757 phone: 512.421.6200 fax: 512.421.6262 (c) Alchemy Semiconductor, Inc., 2000 Au1000, ALCHEMY SEMICONDUCTOR and the ALCHEMY logo are trademarks of Alchemy Semiconductor, Inc. in the United States and foreign countries. All other trademarks are the properties of their respective owners. Rv.02.01.3M