OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM SRAM 32K x 8 SRAM FEATURES * High speed: 10, 12, 15, 20 and 25 * High-performance, low-power, CMOS double-metal process * Single +5V 10% power supply * Easy memory expansion with /C/E and /O/E options * All inputs and outputs are TTL-compatible OPTIONS PIN ASSIGNMENT (Top View) 28-Pin DIP (SA-4) MARKING * Timing 10ns access 12ns access 15ns access 20ns access 25ns access * Packages Plastic DIP (300 mil) Plastic SOJ (300 mil) * 2V data retention (optional) * Low power (optional) * Temperature Commercial (0C to +70C) Industrial (-40C to +85C) Automotive (-40C to +125C) Extended (-55C to +125C) -10 -12 -15 -20 -25 None DJ L P A14 1 28 Vcc A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 DQ8 DQ1 11 18 DQ7 DQ2 12 17 DQ6 DQ3 13 16 DQ5 Vss 14 15 DQ4 28-Pin SOJ (SD-2) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc WE A13 A8 A9 A11 OE A10 CE DQ8 DQ7 DQ6 DQ5 DQ4 None IT AT XT * Part Number Example: MT5C2568DJ-20 L NOTE: Not all combinations of operating temperature, speed, data retention and low power are necessarily available. Please contact the factory for availability of specific part number combinations. GENERAL DESCRIPTION The MT5C2568 is organized as a 32,768 x 8 SRAM using a four-transistor memory cell with a high-speed, low-power CMOS process. Micron SRAMs are fabricated using doublelayer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Micron offers chip enable (/C/E) and output enable (?O/E) with this organization. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (?W/E) and /C/E inputs are both LOW. Reading is accomplished when ?W/E remains HIGH and /C/E and ?O/E go LOW. The device offers a reduced power standby mode MT5C2568 Rev. 2/95 when disabled. This allows system designers to meet low standby power requirements. The "P" version provides a reduction in both operating current (ICC) and TTL standby current (ISB1). The latter is achieved through the use of gated inputs on the ?W/E, ?O/E and address lines, which also facilitates the design of battery backed systems. That is, the gated inputs simplify the design effort and circuitry required to protect against inadvertent battery current drain during power-down, when inputs may be at undefined levels. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL-compatible. 1 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM FUNCTIONAL BLOCK DIAGRAM Vcc GND A DQ8 A A A I/O CONTROL A ROW DECODER A 262,144-BIT MEMORY ARRAY DQ1 CE A A (LSB) OE WE COLUMN DECODER (LSB) A A A A A POWER DOWN A A ?W/E DQ POWER TRUTH TABLE MT5C2568 Rev. 2/95 MODE /O/E /C/E STANDBY X H X HIGH-Z STANDBY READ L L H Q ACTIVE NOT SELECTED H L H HIGH-Z ACTIVE WRITE X L L D ACTIVE 2 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See technical note TN-05-14 for more information. Voltage on VCC Supply Relative to VSS .............. -1V to +7V Storage Temperature (plastic) .................... -55C to +150C Short Circuit Output Current ..................................... 50mA Voltage on Any Pin Relative to VSS ............ -1V to VCC +1V Junction Temperature** ............................................. +150C ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (0C TA 70C; Vcc = 5V 10%) DESCRIPTION SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage CONDITIONS VIH 2.2 VCC+1 V 1 Input Low (Logic 0) Voltage VIL -0.5 0.8 V 1, 2 0V VIN VCC ILI -5 5 A Output(s) disabled 0V VOUT VCC ILO -5 5 A Output High Voltage IOH = -4.0mA VOH 2.4 Output Low Voltage IOL = 8.0mA VOL Input Leakage Current Output Leakage Current Supply Voltage VCC 4.5 V 1 0.4 V 1 5.5 V 1 MAX DESCRIPTION Power Supply Current: Operating Power Supply Current: Standby P CONDITIONS SYMBOL TYP -10 -12 -15 -20 -25 /C/E VIL; VCC = MAX f = MAX = 1/ tRC outputs open ICC 130 200 180 165 150 140 mA 3, 13 P version ICC 100 - - 140 125 120 mA 3, 13 /C/E VIH; VCC = MAX f = MAX = 1/ tRC outputs open ISB1 24 55 50 45 40 35 mA 13 P version ISB1 1.4 - - 4 4 4 mA 13 /C/E VCC -0.2V; VCC = MAX VIN VSS +0.2V or VIN VCC -0.2V; f = 0 ISB2 0.6 5 5 5 5 5 mA 13 P version ISB2 0.4 - - 3 3 3 mA 13 UNITS NOTES version not available with this speed. MT5C2568 Rev. 2/95 3 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM CAPACITANCE DESCRIPTION Input Capacitance CONDITIONS SYMBOL MAX UNITS NOTES TA = 25C; f = 1 MHz CI 6 pF 4 VCC = 5V CO 6 pF 4 Output Capacitance ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (0C TA 70C; VCC = 5V 10%) DESCRIPTION READ Cycle READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Chip Enable to power-up time Chip disable to power-down time Output Enable access time Output Enable to output in Low-Z Output disable to out put in High-Z WRITE Cycle WRITE cycle time Chip Enable to end of write Chip Enable to end of write (P and LP version) Address valid to end of write Address valid to end of write (P and LP version) Address setup time Address hold from end of write WRITE pulse width WRITE pulse width Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z MT5C2568 Rev. 2/95 SYM tRC -10 MIN MAX -12 MIN MAX -15 MIN MAX -20 MIN MAX -25 MIN MAX UNITS NOTES 10 12 15 20 25 tAA 10 10 tACE tOH tLZCE 3 3 tHZCE tPU tCW tCW tAW tAW tAS tAH tWP1 tWP2 tDS tDH tLZWE tHZWE 3 3 0 10 5 0 tHZOE 15 15 6 0 tAOE tWC 3 3 5 tPD tLZOE 12 12 0 0 12 8 8 0 1 8 12 7 0 2 5 6 4 10 25 8 0 7 20 12 12 12 12 0 1 12 15 10 0 2 7 ns ns ns ns ns ns ns ns ns ns ns ns ns 0 0 15 10 12 10 12 0 1 10 12 7 0 2 9 20 8 6 7 3 3 0 0 ns ns ns ns ns ns ns ns ns ns ns 25 25 9 15 8 6 10 7 7 0 1 7 10 6 0 2 3 3 8 12 6 5 20 20 25 15 15 15 15 0 1 15 15 10 0 2 8 7 6, 7 4 4 6 7 6, 7 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM INDUSTRIAL TEMPERATURE SPECIFICATIONS (IT) The following specifications are to be used for Industrial Temperature (IT) MT5C2568 SRAMs. (-40C TA 85C) MAX DESCRIPTION CONDITIONS SYMBOL -10 -12 -15 -20 -25 UNITS NOTES Power Supply Current: Operating /C/E VIL; VCC = MAX f = MAX = 1/ tRC outputs open ICC 210 190 170 160 150 mA Power Supply Current: Standby /C/E VIH; VCC = MAX f = MAX = 1/ tRC outputs open ISB1 65 60 50 45 40 mA /C/E VCC -0.2V; VCC = MAX VIN VSS +0.2V or VIN VCC -0.2V; f = 0 ISB2 6 6 6 6 6 mA 3 DATA RETENTION ELECTRICAL CHARACTERISTICS (L version only) DESCRIPTION CONDITIONS Data Retention Current /C/E (Vcc -0.2V) VIN (VCC -0.2V) or 0.2V SYMBOL MAX UNITS VCC = 2V ICCDR 400 A VCC = 3V ICCDR 600 A NOTES ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Refer to commercial temperature timing parameters for specifications not listed here. (Notes 5, 13) (-40C TA 85C) DESCRIPTION -12 MIN MAX SYM READ Cycle Output hold from address change Chip Enable to output in Low-Z WRITE Cycle Address hold from end of write tOH -15 MIN MAX MIN -20 MAX MIN -25 MAX UNITS NOTES tLZCE 2 2 2 2 2 2 2 2 ns ns tAH 2 2 2 2 ns 7 ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-40C TA 85C) DESCRIPTION Input High (Logic 1) Voltage MT5C2568 Rev. 2/95 CONDITIONS SYMBOL MIN MAX UNITS NOTES VIH 2.3 VCC +1 V 1 5 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM AUTOMOTIVE AND EXTENDED TEMPERATURE SPECIFICATIONS (AT AND XT) The following specifications are to be used for Automotive Temperature (AT) and Extended Temperature (XT) MT5C2568 SRAMs. (-40C TA 125C - AT) (-55C TA 125C - XT) MAX DESCRIPTION CONDITIONS SYMBOL -12 -15 -20 -25 UNITS NOTES Power Supply Current: Operating /C/E VIL; VCC = MAX f = MAX = 1/ tRC outputs open ICC 195 175 165 155 mA 3 Power Supply Current: Standby /C/E VIH; VCC = MAX f = MAX = 1/ tRC outputs open ISB1 60 50 45 40 mA /C/E VCC -0.2V; VCC = MAX VIN VSS +0.2V or VIN VCC -0.2V; f = 0 ISB2 7 7 7 7 mA DATA RETENTION ELECTRICAL CHARACTERISTICS (L version only) DESCRIPTION CONDITIONS Data Retention Current /C/E (Vcc -0.2V) VIN (VCC -0.2V) or 0.2V SYMBOL MAX UNITS VCC = 2V ICCDR 500 A VCC = 3V ICCDR 800 A NOTES ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Refer to commercial temperature timing parameters for specifications not listed here. (Notes 5, 13) (-40C TA 125C - AT; -55C TA 125C - XT; VCC = 5V 10%) DESCRIPTION -12 MIN MAX SYM READ Cycle Output hold from address change Chip Enable to output in Low-Z WRITE Cycle Address hold from end of write tOH -15 MIN MAX MIN -20 MAX MIN -25 MAX UNITS NOTES tLZCE 2 2 2 2 2 2 2 2 ns ns tAH 2 2 2 2 ns 7 ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-40C TA 125C - AT) (-55C TA 125C - XT) DESCRIPTION Input High (Logic 1) Voltage MT5C2568 Rev. 2/95 CONDITIONS SYMBOL MIN MAX UNITS NOTES VIH 2.3 VCC +1 V 1 6 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM AC TEST CONDITIONS +5V +5V 480 480 Input pulse levels ................................... Vss to 3.0V Q Q Input rise and fall times ....................................... 3ns 255 30 pF 5 pF 255 Input timing reference levels ............................. 1.5V Output reference levels ..................................... 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT Output load .............................. See Figures 1 and 2 Fig. 2 OUTPUT LOAD EQUIVALENT NOTES 8. W ? /E is HIGH for READ cycle. 9. Device is continuously selected. All chip enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip enable and write enable can initiate and terminate a WRITE cycle. 13. Typical values are measured at 5V, 25C and 15ns cycle time. 14. Typical currents are measured at 25C. 1. 2. 3. 4. 5. All voltages referenced to VSS (GND). -3V for pulse width < tRC/2. ICC is dependent on output loading and cycle rates. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. tHZCE, tHZOE and tHZWE are specified with CL = 5pF as in Fig. 2. Transition is measured 500mV from steady state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE. DATA RETENTION ELECTRICAL CHARACTERISTICS (L and LP versions only) DESCRIPTION CONDITIONS SYMBOL MIN VDR 2 VCC for Retention Data Data Retention Current L version Data Retention Current LP version MAX UNITS NOTES V /C/E (Vcc -0.2V) VIN (VCC -0.2V) or 0.2V VCC = 2V ICCDR 125 300 A 14 VCC = 3V ICCDR 175 500 A 14 /C/E (Vcc -0.2V) VCC = 2V VCC = 3V ICCDR ICCDR 100 150 300 500 A A 14 14 Chip Deselect to Data Retention Time Operation Recovery Time MT5C2568 Rev. 2/95 TYP 7 tCDR 0 ns 4 tR tRC ns 4, 11 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM , LOW VCC DATA RETENTION WAVEFORM DATA RETENTION MODE 4.5V Vcc 4.5V VDR tCDR CE , tR VDR VIH VIL READ CYCLE NO. 1 8, 9 tRC ADDR VALID tAA tOH Q PREVIOUS DATA VALID ,, DATA VALID READ CYCLE NO. 2 7, 8, 10 tRC CE tAOE tLZOE OE tACE tLZCE DQ HIGH-Z tPU Icc tHZOE , ,, ,, tHZCE DATA VALID tPD DON'T CARE UNDEFINED MT5C2568 Rev. 2/95 8 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM WRITE CYCLE NO. 1 12 (Chip Enable Controlled) tWC , , , , , , , , , , , , , , , , ADDR tAW tAS tCW tAH CE tWP1 WE tDS tDH DATA VALID D HIGH-Z Q WRITE CYCLE NO. 2 12 (Write Enable Controlled) , , , , , , , , , , ,,, , ,, , , tWC ADDR tAW tCW tAH CE tAS tWP1 WE tDS tDH DATA VALID D HIGH-Z Q DON'T CARE UNDEFINED NOTE: MT5C2568 Rev. 2/95 Output enable (?O/E) is inactive (HIGH). 9 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM WRITE CYCLE NO. 3 7, 12, 16 (Write Enable Controlled) , , , , , , , , , , , , , , , , ,,,,, ,, , , tWC ADDR tAW tCW tAH CE tAS tWP2 WE tDS tDH DATA VALID D tHZWE tLZWE HIGH-Z Q DON'T CARE UNDEFINED NOTE: MT5C2568 Rev. 2/95 Output enable (?O/E) is active (LOW). 10 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM 28-PIN PLASTIC DIP 1.453 (36.91) 1.447 (36.75) .291 (7.39) .285 (7.24) PIN #1 INDEX SEATING PLANE PIN 1 .170 (4.32) .155 (3.94) .062 (1.57) .050 (1.27) .100 (2.54) TYP .021 (0.53) .016 (0.41) 1.300 (33.02) NOTE: MT5C2568 Rev. 2/95 .140 (3.56) .120 (3.05) .145 (3.68) .135 (3.43) .330 (8.26) .315 (7.87) .014 (0.36) .008 (0.20) .380 (9.65) .330 (8.38) 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 11 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc. OBSOLETE 3/1/95 MT5C2568 32K x 8 SRAM 28-PIN PLASTIC SOJ .729 (18.52) .723 (18.36) .305 (7.75) .299 (7.59) .340 (8.64) .330 (8.38) .050 (1.27) TYP PIN #1 INDEX .650 (16.51) .038 (0.97) .037 (0.94) MAX DAMBAR PROTRUSION .144 (3.66) .136 (3.45) SEATING PLANE .020 (0.51) .015 (0.38) NOTE: .095 (2.41) .080 (2.03) .280 (7.11) .260 (6.60) .027 (0.69) MIN 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. MT5C2568 Rev. 2/95 12 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1995, Micron Semiconductor, Inc.