1
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
FEATURES
• High speed: 10, 12, 15, 20 and 25
• High-performance, low-power, CMOS double-metal
process
• Single +5V ±10% power supply
• Easy memory expansion with /C/E and /O/E options
• All inputs and outputs are TTL-compatible
OPTIONS MARKING
• Timing
10ns access -10
12ns access -12
15ns access -15
20ns access -20
25ns access -25
• Packages
Plastic DIP (300 mil) None
Plastic SOJ (300 mil) DJ
• 2V data retention (optional) L
• Low power (optional) P
• Temperature
Commercial (0°C to +70°C) None
Industrial (-40°C to +85°C) IT
Automotive (-40°C to +125°C) AT
Extended (-55°C to +125°C) XT
• Part Number Example: MT5C2568DJ-20 L
NOTE: Not all combinations of operating temperature, speed, data retention
and low power are necessarily available. Please contact the factory for availabil-
ity of specific part number combinations.
PIN ASSIGNMENT (Top View)
SRAM 32K x 8 SRAM
28-Pin SOJ
(SD-2)
28-Pin DIP
(SA-4)
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
Vcc
WE
A13
A8
A9
A11
OE
A10
CE
DQ8
DQ7
DQ6
DQ5
DQ4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
A13
A8
A9
A11
OE
A10
CE
DQ8
DQ7
DQ6
DQ5
DQ4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GENERAL DESCRIPTION
The MT5C2568 is organized as a 32,768 x 8 SRAM using
a four-transistor memory cell with a high-speed, low-power
CMOS process. Micron SRAMs are fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Micron offers chip enable (/C/E) and output enable (?O/E) with
this organization. These enhancements can place the out-
puts in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (?W/E) and /C/E inputs are both LOW. Reading is
accomplished when ?W/E remains HIGH and /C/E and ?O/E go
LOW. The device offers a reduced power standby mode
when disabled. This allows system designers to meet low
standby power requirements.
The “P” version provides a reduction in both operating
current (ICC) and TTL standby current (ISB1). The latter is
achieved through the use of gated inputs on the ?W/E, ?O/E and
address lines, which also facilitates the design of battery
backed systems. That is, the gated inputs simplify the
design effort and circuitry required to protect against inad-
vertent battery current drain during power-down, when
inputs may be at undefined levels.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL-compatible.
2
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
FUNCTIONAL BLOCK DIAGRAM
A
A
A
A
A
A
A
A
Vcc GND
A
OE
WE
CE
COLUMN DECODER
ROW DECODER
262,144-BIT
MEMORY ARRAY
I/O CONTROL
(LSB)
DQ1
DQ8
POWER
DOWN
(LSB)
AAAAAA
TRUTH TABLE
MODE /O/E/C/E?W/E DQ POWER
STANDBY X H X HIGH-Z STANDBY
READ L L H Q ACTIVE
NOT SELECTED H L H HIGH-Z ACTIVE
WRITE X L L D ACTIVE
3
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS .............. -1V to +7V
Storage Temperature (plastic).................... -55°C to +150°C
Short Circuit Output Current ..................................... 50mA
Voltage on Any Pin Relative to VSS ............ -1V to VCC +1V
Junction Temperature** ............................................. +150°C
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
**Maximum junction temperature depends upon package
type, cycle time, loading, ambient temperature and airflow.
See technical note TN-05-14 for more information.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(0°C ≤ TA ≤ 70°C; Vcc = 5V ±10%)
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage VIH 2.2 VCC+1 V 1
Input Low (Logic 0) Voltage VIL -0.5 0.8 V 1, 2
Input Leakage Current 0V ≤ VIN ≤ VCC ILI-5 5 µA
Output Leakage Current Output(s) disabled ILO-5 5 µA
0V ≤ VOUT ≤ VCC
Output High Voltage IOH = -4.0mA VOH 2.4 V 1
Output Low Voltage IOL = 8.0mA VOL 0.4 V 1
Supply Voltage VCC 4.5 5.5 V 1
†P version not available with this speed.
DESCRIPTION CONDITIONS SYMBOL TYP -10†-12†-15†-20 -25 UNITS NOTES
Power Supply /C/E ≤ VIL; VCC = MAX
Current: Operating f = MAX = 1/ tRC ICC 130 200 180 165 150 140 mA 3, 13
outputs open
P version ICC 100 - - 140 125 120 mA 3, 13
Power Supply /C/E ≥ VIH; VCC = MAX
Current: Standby f = MAX = 1/ tRC ISB124 55 50 45 40 35 mA 13
outputs open
P version ISB11.4 - - 4 4 4 mA 13
/C/E ≥ VCC -0.2V; VCC = MAX
VIN ≤ VSS +0.2V or ISB20.6 55555mA13
VIN ≥ VCC -0.2V; f = 0
P version ISB20.4 - - 3 3 3 mA 13
MAX
4
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
CAPACITANCE
DESCRIPTION CONDITIONS SYMBOL MAX UNITS NOTES
Input Capacitance TA = 25°C; f = 1 MHz CI6pF4
Output Capacitance VCC = 5V CO6pF4
DESCRIPTION
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (0°C ≤ TA ≤ 70°C; VCC = 5V ±10%)
-10 -12 -15 -20 -25
SYM MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
READ Cycle
READ cycle time tRC 10 12 15 20 25 ns
Address access time tAA 10 12 15 20 25 ns
Chip Enable access time tACE 10 12 15 20 25 ns
Output hold from address change tOH33333ns
Chip Enable to output in Low-Z tLZCE 3 3333ns7
Chip disable to output in High-Z tHZCE 5 6 8 9 9 ns 6, 7
Chip Enable to power-up time tPU00000ns4
Chip disable to power-down time tPD 10 12 15 20 25 ns 4
Output Enable access time tAOE 5 6 8 8 8 ns
Output Enable to output in Low-Z tLZOE00000ns
Output disable to out put in High-Z tHZOE 5 6 6 7 7 ns 6
WRITE Cycle
WRITE cycle time tWC 10 12 15 20 25 ns
Chip Enable to end of write tCW 7 8 10 12 15 ns
Chip Enable to end of write (P and LP version) tCW - - 12 12 15 ns
Address valid to end of write tAW 7 8 10 12 15 ns
Address valid to end of write (P and LP version) tAW - - 12 12 15 ns
Address setup time tAS00000ns
Address hold from end of write tAH11111ns
WRITE pulse width tWP1 7 8 10 12 15 ns
WRITE pulse width tWP2 10 12 12 15 15 ns
Data setup time tDS 6 7 7 10 10 ns
Data hold time tDH00000ns
Write disable to output in Low-Z tLZWE 2 2222ns7
Write Enable to output in High-Z tHZWE 5 6 7 8 10 ns 6, 7
5
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
INDUSTRIAL TEMPERATURE SPECIFICATIONS (IT)
The following specifications are to be used for Industrial Temperature (IT) MT5C2568 SRAMs.
(-40°C ≤ TA ≤ 85°C)
DESCRIPTION CONDITIONS SYMBOL -10 -12 -15 -20 -25 UNITS NOTES
Power Supply /C/E ≤ VIL; VCC = MAX
Current: Operating f = MAX = 1/ tRC ICC 210 190 170 160 150 mA 3
outputs open
Power Supply /C/E ≥ VIH; VCC = MAX
Current: Standby f = MAX = 1/ tRC ISB165 60 50 45 40 mA
outputs open
/C/E ≥ VCC -0.2V; VCC = MAX
VIN ≤ VSS +0.2V or ISB266666mA
VIN ≥ VCC -0.2V; f = 0
MAX
DATA RETENTION ELECTRICAL CHARACTERISTICS (L version only)
DESCRIPTION CONDITIONS SYMBOL MAX UNITS NOTES
Data Retention Current /C/E ≥ (Vcc -0.2V) VCC = 2V ICCDR 400 µA
VIN ≥ (VCC -0.2V)
or ≤ 0.2V VCC = 3V ICCDR 600 µA
DESCRIPTION
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
Refer to commercial temperature timing parameters for specifications not listed here.
(Notes 5, 13) (-40°C ≤ TA ≤ 85°C)
-12 -15 -20 -25
SYM MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
READ Cycle
Output hold from address change tOH2222ns
Chip Enable to output in Low-Z tLZCE 2 2 2 2 ns 7
WRITE Cycle
Address hold from end of write tAH2222ns
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-40°C ≤ TA ≤ 85°C)
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage VIH 2.3 VCC +1 V 1
6
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
AUTOMOTIVE AND EXTENDED TEMPERATURE SPECIFICATIONS (AT AND XT)
The following specifications are to be used for Automotive Temperature (AT) and Extended Temperature (XT) MT5C2568
SRAMs. (-40°C ≤ TA ≤ 125°C - AT) (-55°C ≤ TA ≤ 125°C - XT)
DESCRIPTION CONDITIONS SYMBOL -12 -15 -20 -25 UNITS NOTES
Power Supply /C/E ≤ VIL; VCC = MAX
Current: Operating f = MAX = 1/ tRC ICC 195 175 165 155 mA 3
outputs open
Power Supply /C/E ≥ VIH; VCC = MAX
Current: Standby f = MAX = 1/ tRC ISB160 50 45 40 mA
outputs open
/C/E ≥ VCC -0.2V; VCC = MAX
VIN ≤ VSS +0.2V or ISB27777mA
VIN ≥ VCC -0.2V; f = 0
MAX
DATA RETENTION ELECTRICAL CHARACTERISTICS (L version only)
DESCRIPTION CONDITIONS SYMBOL MAX UNITS NOTES
Data Retention Current /C/E ≥ (Vcc -0.2V) VCC = 2V ICCDR 500 µA
VIN ≥ (VCC -0.2V)
or ≤ 0.2V VCC = 3V ICCDR 800 µA
DESCRIPTION
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
Refer to commercial temperature timing parameters for specifications not listed here.
(Notes 5, 13) (-40°C ≤ TA ≤ 125°C - AT; -55°C ≤ TA ≤ 125°C - XT; VCC = 5V ±10%)
-12 -15 -20 -25
SYM MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
READ Cycle
Output hold from address change tOH2222ns
Chip Enable to output in Low-Z tLZCE 2 2 2 2 ns 7
WRITE Cycle
Address hold from end of write tAH2222ns
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-40°C ≤ TA ≤ 125°C - AT) (-55°C ≤ TA ≤ 125°C - XT)
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage VIH 2.3 VCC +1 V 1
7
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
Q255
480
30 pF
+5V
Fig. 1 OUTPUT LOAD Fig. 2 OUTPUT LOAD
EQUIVALENT EQUIVALENT
Q255
480
5 pF
+5V
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 3ns
Input timing reference levels ............................. 1.5V
Output reference levels..................................... 1.5V
Output load .............................. See Figures 1 and 2
8. ?W/E is HIGH for READ cycle.
9. Device is continuously selected. All chip enables are
held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable and write enable can initiate and
terminate a WRITE cycle.
13. Typical values are measured at 5V, 25°C and 15ns
cycle time.
14. Typical currents are measured at 25°C.
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < tRC/2.
3. ICC is dependent on output loading and cycle rates.
4. This parameter is sampled.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tHZCE, tHZOE and tHZWE are specified with CL =
5pF as in Fig. 2. Transition is measured ±500mV from
steady state voltage.
7. At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than
tLZWE.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L and LP versions only)
DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES
VCC for Retention Data VDR 2V
Data Retention Current /C/E ≥ (Vcc -0.2V) VCC = 2V ICCDR 125 300 µA14
L version VIN ≥ (VCC -0.2V)
or ≤ 0.2V VCC = 3V ICCDR 175 500 µA14
Data Retention Current /C/E ≥ (Vcc -0.2V) VCC = 2V ICCDR 100 300 µA14
LP version VCC = 3V ICCDR 150 500 µA14
Chip Deselect to Data tCDR 0 ns 4
Retention Time
Operation Recovery Time tRtRC ns 4, 11
8
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
DATA RETENTION MODE
tCDR tR
4.5V 4.5V
DRV
DRV
,
,
V
VIH
IL
CE
Vcc
LOW VCC DATA RETENTION WAVEFORM
DON’T CARE
UNDEFINED
,,
,,
tRC
tACE
tLZCE
tAOE
tLZOE
tHZCE
tPU tPD
HIGH-Z
,
CE
OE
DQ
Icc
tHZOE
DATA VALID
READ CYCLE NO. 2 7, 8, 10
READ CYCLE NO. 1 8, 9
tRC
,,
tAA
OH
VALID
PREVIOUS DATA VALID DATA VALID
ADDR
Q
t
9
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
WRITE CYCLE NO. 1 12
(Chip Enable Controlled)
tWC
,
,,
,
,,
,,
tAW
tAS tCW tAH
tWP1
CE
WE
ADDR
D
HIGH-Z
Q
tDH
tDS
DATA VALID
,
,,
,,,
,,
,,
WRITE CYCLE NO. 2 12
(Write Enable Controlled)
,
,,
,,,
,,
tWC
tAW
tCW tAH
tAS tWP1
tDH
tDS
HIGH-Z
CE
WE
ADDR
D
Q
DATA VALID
DON’T CARE
UNDEFINED
,
,
,,
,,
,,
,,
NOTE: Output enable (?O/E) is inactive (HIGH).
10
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
WRITE CYCLE NO. 3 7, 12, 16
(Write Enable Controlled)
,
,,
,,,
,,
,,,,,
,,
tWC
tAW
tCW tAH
tAS tWP2
tHZWE tLZWE
tDH
tDS
HIGH-Z
CE
WE
ADDR
D
Q
DATA VALID
DON’T CARE
UNDEFINED
,
,
,,
,,
,,
,,
NOTE: Output enable (?O/E) is active (LOW).
11
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
28-PIN PLASTIC DIP
.135 (3.43)
.145 (3.68)
.100 (2.54)
TYP .021 (0.53)
.050 (1.27)
.140 (3.56)
.120 (3.05)
.170 (4.32)
.155 (3.94)
.380 (9.65)
.315 (7.87)
SEATING PLANE
.016 (0.41) .008 (0.20)
.014 (0.36)
1.453 (36.91)
1.447 (36.75)
.291 (7.39)
.285 (7.24)
1.300 (33.02)
.330 (8.26)
.330 (8.38)
.062 (1.57)
PIN #1 INDEXPIN 1
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
12
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
28-PIN PLASTIC SOJ
.299 (7.59)
.305 (7.75)
.723 (18.36)
.340 (8.64)
.050 (1.27) TYP
PIN #1 INDEX
.020 (0.51)
.015 (0.38)
.136 (3.45)
.144 (3.66)
.095 (2.41)
.080 (2.03) .027 (0.69)
MIN
.280 (7.11)
SEATING PLANE
.729 (18.52)
.650 (16.51)
.260 (6.60)
.330 (8.38)
.037 (0.94) MAX DAMBAR PROTRUSION
.038 (0.97)
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.