1
MT5C2568 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 2/95 1995, Micron Semiconductor, Inc.
MT5C2568
32K x 8 SRAM
OBSOLETE 3/1/95
FEATURES
• High speed: 10, 12, 15, 20 and 25
• High-performance, low-power, CMOS double-metal
process
• Single +5V ±10% power supply
• Easy memory expansion with /C/E and /O/E options
• All inputs and outputs are TTL-compatible
OPTIONS MARKING
• Timing
10ns access -10
12ns access -12
15ns access -15
20ns access -20
25ns access -25
• Packages
Plastic DIP (300 mil) None
Plastic SOJ (300 mil) DJ
• 2V data retention (optional) L
• Low power (optional) P
• Temperature
Commercial (0°C to +70°C) None
Industrial (-40°C to +85°C) IT
Automotive (-40°C to +125°C) AT
Extended (-55°C to +125°C) XT
• Part Number Example: MT5C2568DJ-20 L
NOTE: Not all combinations of operating temperature, speed, data retention
and low power are necessarily available. Please contact the factory for availabil-
ity of specific part number combinations.
PIN ASSIGNMENT (Top View)
SRAM 32K x 8 SRAM
28-Pin SOJ
(SD-2)
28-Pin DIP
(SA-4)
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
Vcc
WE
A13
A8
A9
A11
OE
A10
CE
DQ8
DQ7
DQ6
DQ5
DQ4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
A13
A8
A9
A11
OE
A10
CE
DQ8
DQ7
DQ6
DQ5
DQ4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GENERAL DESCRIPTION
The MT5C2568 is organized as a 32,768 x 8 SRAM using
a four-transistor memory cell with a high-speed, low-power
CMOS process. Micron SRAMs are fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Micron offers chip enable (/C/E) and output enable (?O/E) with
this organization. These enhancements can place the out-
puts in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (?W/E) and /C/E inputs are both LOW. Reading is
accomplished when ?W/E remains HIGH and /C/E and ?O/E go
LOW. The device offers a reduced power standby mode
when disabled. This allows system designers to meet low
standby power requirements.
The “P” version provides a reduction in both operating
current (ICC) and TTL standby current (ISB1). The latter is
achieved through the use of gated inputs on the ?W/E, ?O/E and
address lines, which also facilitates the design of battery
backed systems. That is, the gated inputs simplify the
design effort and circuitry required to protect against inad-
vertent battery current drain during power-down, when
inputs may be at undefined levels.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL-compatible.