19-3019; Rev 1; 3/04 KIT ATION EVALU LE B A IL A AV Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL Applications Communications SATCOM, LMDS, MMDS, HFC, DSL, WLAN, Point-to-Point Microwave Links Wireless Base Stations Direct Digital Synthesis Instrumentation/ATE 8-Bit Resolution, Dual DAC 300Msps Update Rate Integrated 4x/2x/1x Interpolating Filters Internal PLL Multiplier 2.7V to 3.3V Single Supply Full Output Swing and Dynamic Performance at 2.7V Supply Superior Dynamic Performance: 68dBc SFDR at fOUT = 20MHz Programmable Channel Gain Matching Integrated 1.24V Low-Noise Bandgap Reference Single-Resistor Gain Control Interleave Data Mode Differential Clock Input Modes EV Kit Available--MAX5858AEVKIT Ordering Information PART TEMP RANGE PIN-PACKAGE MAX5856AECM -40C to +85C 48 TQFP-EP* *EP = Exposed paddle. Pin Configuration DVDD DGND AVDD OUTPA OUTNA AGND OUTPB OUTNB AVDD REFR N.C. N.C. TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 DA7/PD DA6/DACEN DA5/F2EN DA4/F1EN DA3/G3 DGND DVDD DA2/G2 DA1/G1 DA0/G0 N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 EP MAX5856A 36 35 34 33 32 31 30 29 28 27 26 25 REF0 REN PLLF PGND PVDD CLKXN CLKXP PLLEN LOCK CW N.C. N.C. 13 14 15 16 17 18 19 20 21 22 23 24 DB7 DB6 DB5 DB4 DB3 DVDD DGND CLK IDE DB2 DB1 DB0 The MAX5856A dual, 8-bit, 300Msps digital-to-analog converter (DAC) provides superior dynamic performance in wideband communication systems. The MAX5856A integrates two 8-bit DAC cores, 4x/2x/1x programmable digital interpolation filters, phase-lock loop (PLL) clock multiplier, and a 1.24V reference. The MAX5856A supports single-ended and differential modes of operation. The MAX5856A dynamic performance is maintained over the entire power-supply operating range of 2.7V to 3.3V. The analog outputs support a compliance voltage of -1.0V to +1.25V. The 4x/2x/1x programmable interpolation filters feature excellent passband distortion and noise performance. Interpolating filters minimize the design complexity of analog reconstruction filters while lowering the data bus and the clock speeds of the digital interface. The PLL multiplier generates all internal synchronized high-speed clock signals for interpolating filter operation and DAC core conversion. The internal PLL helps minimize system complexity and lower cost. To reduce the I/O pin count, the DAC can also operate in interleave data mode. This allows the MAX5856A to be updated on a single 8-bit bus. The MAX5856A features digital control of channel gain matching to within 0.4dB in sixteen 0.05dB steps. Channel matching improves sideband suppression in analog quadrature modulation applications. The on-chip 1.24V bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. The internal reference can be disabled and an external reference may be applied for high-accuracy applications. The MAX5856A features full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.3V single supply. The DAC supports three modes of power-control operation: normal, low-power standby, and complete power-down. In power-down mode, the operating current is reduced to 1A. The MAX5856A is packaged in a 48-pin TQFP with exposed paddle (EP) for enhanced thermal dissipation and is specified for the extended (-40C to +85C) operating temperature range. Features TQFP-EP NOTE: EXPOSED PADDLE CONNECTED TO GND. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5856A General Description MAX5856A Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL ABSOLUTE MAXIMUM RATINGS AVDD, DVDD, PVDD to AGND, DGND, PGND ..........-0.3V to +4V DA7-DA0, DB7-DB0, CW, REN, PLLF, PLLEN to AGND, DGND, PGND........................................................-0.3V to +4V IDE to AGND, DGND, PGND ...................-0.3V to (DVDD + 0.3V) CLKXN, CLKXP to PGND .........................................-0.3V to +4V OUTP_, OUTN_ to AGND.......................-1.25V to (AVDD + 0.3V) CLK, LOCK to DGND...............................-0.3V to (DVDD + 0.3V) REFR, REFO to AGND .............................-0.3V to (AVDD + 0.3V) AGND to DGND, DGND to PGND, AGND to PGND .................................................-0.3V to +0.3V Maximum Current into Any Pin (excluding power supplies) ..........................................50mA Continuous Power Dissipation (TA = +70C) 48-Pin TQFP-EP (derate 36.2mW/C above +70C) ....2.899W Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference, VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25C, guaranteed by production test. TA < +25C, guaranteed by design and characterization. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 8 Bits Integral Nonlinearity INL RL = 0 -0.4 0.15 +0.4 LSB Differential Nonlinearity DNL Guaranteed monotonic, RL = 0 -0.2 0.07 +0.2 LSB Offset Error VOS -0.1 0.03 +0.1 LSB Gain Error (See the Parameter Definitions Section) GE Internal reference (Note 1) -10 1.2 +10 External reference -6.5 0.8 +6.5 4x/2x interpolation modes 300 % DYNAMIC PERFORMANCE Maximum DAC Update Rate fDAC Glitch Impulse fOUT = 5MHz, TA +25C fDAC = 165Msps Spurious-Free Dynamic Range to Input Update Rate Nyquist SFDR fDAC = 300Msps, 2x interpolation Spurious-Free Dynamic Range Within a Window Multitone Power Ratio, 8 Tones, ~300kHz Spacing Total Harmonic Distortion to Nyquist 2 Msps 5 SFDR 65 67 fOUT = 20MHz 68 fOUT = 50MHz 63 fOUT = 70MHz 56 fOUT = 5MHz 68 fOUT = 40MHz 65 fOUT = 60MHz 67 fDAC = 200Msps, 2x interpolation, fOUT = 40MHz, span = 20MHz fDAC = 165Msps, fOUT = 5MHz, span = 4MHz pV-s dBc 67 dBc 68 72 MTPR fDAC = 165Msps, fOUT = 20MHz 65 dBc THD fDAC = 165Msps, fOUT = 5MHz 70 dBc _______________________________________________________________________________________ Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference, VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25C, guaranteed by production test. TA < +25C, guaranteed by design and characterization. Typical values are at TA = +25C.) PARAMETER Noise Spectral Density SYMBOL nD CONDITIONS MIN fDAC = 165Msps, fOUT = 5MHz TYP MAX UNITS -133 dBm/Hz Output Channel-to-Channel Isolation fOUT = 5MHz 80 dB Gain Mismatch Between Channels fOUT = 5MHz 0.05 dB Phase Mismatch Between Channels fOUT = 5MHz 0.15 Degrees 50 pA/Hz Wideband Output Noise ANALOG OUTPUT Full-Scale Output Current Range IFS Output Voltage Compliance Range Output Leakage Current Power-down or standby mode 2 20 mA -1.0 +1.25 V -5 +5 A REFERENCE Reference Output Voltage Output-Voltage Temperature Drift VREFO REN = AGND 1.14 TCVREF Reference Output Drive Capability REN = AVDD Reference Input Voltage Range Reference Supply Rejection Current Gain IFS/IREF 1.24 1.34 V 50 ppm/C 50 A 0.1 1.32 V 0.2 mV/V 32 mA/mA INTERPOLATION FILTER (2x interpolation) fOUT/ 0.5fDAC Passband Width Stopband Rejection -0.005dB 0.398 -0.01dB 0.402 -0.1dB 0.419 -3dB 0.478 0.604fDAC / 2 to 1.396fDAC / 2 74 0.600fDAC / 2 to 1.400fDAC / 2 62 0.594fDAC / 2 to 1.406fDAC / 2 53 0.532fDAC / 2 to 1.468fDAC / 2 14 MHz/ MHz dB Group Delay 18 Data clock cycles Impulse Response Duration 22 Data clock cycles _______________________________________________________________________________________ 3 MAX5856A ELECTRICAL CHARACTERISTICS (continued) MAX5856A Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference, VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25C, guaranteed by production test. TA < +25C, guaranteed by design and characterization. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INTERPOLATION FILTER (4x interpolation) Passband Width fOUT/ 0.5fDAC Stopband Rejection -0.005dB 0.2 -0.01dB 0.201 -0.1dB 0.21 -3dB 0.239 0.302fDAC / 2 to 1.698fDAC / 2 74 0.300fDAC / 2 to 1.700fDAC / 2 63 0.297fDAC / 2 to 1.703 fDAC / 2 53 0.266fDAC / 2 to 1.734fDAC / 2 14 MHz/ MHz dB Group Delay 22 Data clock cycles Impulse Response Duration 27 Data clock cycles LOGIC INPUTS (IDE, CW, REN, DA7-DA0, DB7-DB0, PLLEN) Digital Input Voltage High VIH Digital Input Voltage Low VIL 2 Digital Input Current High IH VIH = 2V -1 Digital Input Current Low IIL VIL = 0.8V -1 Digital Input Capacitance CIN V 0.8 V +1 A +1 3 A pF DIGITAL OUTPUTS (CLK, LOCK) Digital Output-Voltage High VOH ISOURCE = 0.5mA, Figure 1 Digital Output-Voltage Low VOL ISINK = 0.5mA, Figure 1 0.9 x DVDD V 0.1 x DVDD V DIFFERENTIAL CLOCK INPUT (CLKXP, CLKXN) Clock Input Internal Bias PVDD / 2 Differential Clock Input Swing V 0.5 Clock Input Impedance Single-ended clock drive VP-P 5 k TIMING CHARACTERISTICS No interpolation Input Data Rate fDATA 2x interpolation 4x interpolation 4 165 PLL disabled PLL enabled 150 75 150 37.5 75 PLL disabled PLL enabled 75 _______________________________________________________________________________________ Msps Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference, VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25C, guaranteed by production test. TA < +25C, guaranteed by design and characterization. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP No interpolation, PLL enabled Clock Frequency at CLK Input Output Settling Time fCLK ts Output Rise Time MAX UNITS 165 2x interpolation, PLL enabled 75 4x interpolation, PLL enabled 37.5 150 MHz 75 To 0.1% error band (Note 2) 11 ns 10% to 90% (Note 2) 2.5 ns 2.5 ns Output Fall Time 90% to 10% (Note 2) Data-to-CLK Rise Setup Time (Note 3) tDCSR PLL disabled 1.5 PLL enabled 2.2 Data-to-CLK Rise Hold Time (Note 3) tDCHR PLL disabled 0.4 PLL enabled 1.4 Data-to-CLK Fall Setup Time (Note 3) tDCSF PLL disabled 1.8 PLL enabled 2.4 Data-to-CLK Fall Hold Time (Note 3) tDCHF PLL disabled 1.2 PLL enabled 1.3 Control Word to CW Fall Setup Time tCWS 2.5 ns Control Word to CW Fall Hold Time tCWH 2.5 ns CW High Time 5 ns CW Low Time 5 DACEN Rise-to-VOUT Stable PD Fall-to-VOUT Stable Clock Frequency at CLKXP/CLKXN Input tSTB tPDSTB fCLKDIFF CLKXP/CLKXN Differential Clock Input to CLK Output Delay tCXD Minimum CLKXP/CLKXN Clock High Time Minimum CLKXP/CLKXN Clock Low Time External reference ns ns ns ns ns 0.7 s 0.5 ms Differential clock, PLL disabled 300 PLL disabled MHz 4.6 ns tCXH 1.5 ns tCXL 1.5 ns POWER REQUIREMENTS Analog Power-Supply Voltage AVDD Analog Supply Current IAVDD Digital Power-Supply Voltage DVDD 2.7 (Note 4) 44 2.7 3.3 V 47 mA 3.3 V _______________________________________________________________________________________ 5 MAX5856A ELECTRICAL CHARACTERISTICS (continued) MAX5856A Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference, VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25C, guaranteed by production test. TA < +25C, guaranteed by design and characterization. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS fDAC = 60Msps Digital Supply Current (Note 4) IDVDD fDAC = 165Msps fDAC = 200Msps PLL Power-Supply Voltage 2x interpolation 99 4x interpolation 104 No interpolation 53 2x interpolation 147 58 4x interpolation 147 2x interpolation 165 178 4x interpolation 162 175 2.7 3.3 16 fDAC = 165Msps 47 50 fDAC = 200Msps, 2x interpolation or 4x interpolation 55 60 ISTANDBY (Note 5) 4.4 4.8 IPD (Note 5) 1 IPVDD fDAC = 60Msps Total Power Dissipation (Note 4) PTOT fDAC = 165Msps fDAC = 200Msps No interpolation 309 2x interpolation 477 4x interpolation 492 No interpolation 432 2x interpolation 714 4x interpolation 714 2x interpolation 792 4x interpolation 783 Including the internal reference voltage tolerance. Measured single ended with 50 load and complementary output connected to ground. Guaranteed by design, not production tested. Tested with an output frequency of fOUT = 5MHz. All digital inputs at 0 or DVDD. Clock signal disabled. 0.5mA TO OUTPUT PIN 1.6V 5pF 0.5mA Figure 1. Load Test Circuit for CLK Outputs 6 MAX fDAC = 60Msps Power-Down Current Note 1: Note 2: Note 3: Note 4: Note 5: TYP 43 PVDD PLL Supply Current (Note 4) Standby Current MIN No interpolation _______________________________________________________________________________________ UNITS mA V mA mA A 456 mW Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (NO INTERPOLATION, fDAC = 65MHz) 50 80 50 40 AOUT = -12dBFS 60 50 40 30 30 20 20 20 10 10 10 0 0 10 20 30 40 50 60 70 80 90 0 5 0 10 15 20 25 30 35 0 20 30 40 50 60 70 80 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (2x INTERPOLATION, fDAC = 300MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (2x INTERPOLATION, fDAC = 165MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (4x INTERPOLATION, fDAC = 300MHz) PLL DISABLED 90 AOUT = 0dBFS 80 AOUT = -6dBFS 40 AOUT = -12dBFS 30 80 60 50 40 AOUT = -12dBFS 50 40 20 20 20 10 10 10 0 0 30 40 50 60 70 80 5 0 OUTPUT FREQUENCY (MHz) 10 15 20 25 30 35 40 PLL ENABLED 0 5 AOUT = 0dBFS AOUT = -6dBFS 10 15 20 25 30 35 40 OUTPUT FREQUENCY (MHz) 100 PLL DISABLED 90 AOUT = 0dBFS AOUT = -6dBFS 80 70 SFDR (dBc) 70 SFDR (dBc) 0 45 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (4x INTERPOLATION, fDAC = 165MHz) MAX5856A toc07 100 80 AOUT = -12dBFS OUTPUT FREQUENCY (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (4x INTERPOLATION, fDAC = 300MHz) 90 AOUT = -6dBFS 60 30 20 AOUT = 0dBFS 70 30 10 PLL DISABLED 90 MAX5856A toc08 50 100 SFDR (dBc) SFDR (dBc) 70 60 MAX5856A toc05 MAX5856A toc04 AOUT = 0dBFS AOUT = -6dBFS 100 MAX5856A toc06 OUTPUT FREQUENCY (MHz) 70 0 10 OUTPUT FREQUENCY (MHz) PLL ENABLED 80 AOUT = -12dBFS OUTPUT FREQUENCY (MHz) 100 90 AOUT = 0dBFS AOUT = -6dBFS 70 60 AOUT = -12dBFS PLL DISABLED 90 30 0 SFDR (dBc) 100 70 60 40 AOUT = -6dBFS 80 SFDR (dBc) 70 SFDR (dBc) AOUT = 0dBFS AOUT = -6dBFS AOUT = 0dBFS SFDR (dBc) 80 PLL DISABLED 90 MAX5856A toc02 PLL DISABLED 90 100 MAX5856A toc01 100 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (2x INTERPOLATION, fDAC = 300MHz) MAX5856A toc03 SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (NO INTERPOLATION, fDAC = 165MHz) 60 50 40 AOUT = -12dBFS 30 60 50 40 AOUT = -12dBFS 30 20 20 10 10 0 0 0 5 10 15 20 25 30 OUTPUT FREQUENCY (MHz) 35 40 0 3 6 9 12 15 18 21 OUTPUT FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX5856A Typical Operating Characteristics (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.) SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (NO INTERPOLATION, fDAC = 165MHz) 80 AOUT = -6dBFS 60 50 40 TA = +25C 65 60 TA = +85C 55 AOUT = -12dBFS 30 TA = -10C 70 SFDR (dBc) -20 50 20 -15 -40 10 35 60 -50 -60 -70 -100 0 85 -40 -90 40 0 -30 -80 45 10 fCLK = 165MHz fOUT = 9.7MHz AOUT = -6dBFS -10 10 20 30 40 50 60 70 80 90 7.7 8.3 8.9 9.5 10.7 11.3 11.7 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) FFT PLOT FOR DAC UPDATE NYQUIST WINDOW (NO INTERPOLATION, fDAC = 165MHz, fOUT = 10MHz, AOUT = 0dBFS) FFT PLOT FOR DAC UPDATE NYQUIST WINDOW (2x INTERPOLATION, fDAC = 200MHz, fOUT = 10MHz, AOUT = 0dBFS) FFT PLOT FOR DAC UPDATE NYQUIST WINDOW (4x INTERPOLATION, fDAC = 200MHz, fOUT = 10MHz, AOUT = 0dBFS) -20 OUTPUT POWER (dBm) -40 -50 -60 -70 0 -10 -20 OUTPUT POWER (dBm) -20 -30 -10 -30 -40 -50 -60 -70 -30 -40 -50 -60 -70 -80 -80 -90 -90 -90 -100 -100 -100 0 8.25 16.50 33.00 66.00 82.50 49.50 24.75 41.25 57.75 74.25 MAX5856A toc14 0 MAX5856A toc12 0 -10 -80 0 10 20 30 40 50 60 70 80 90 100 OUTPUT FREQUENCY (MHz) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) 8 10.1 TEMPERATURE (C) MAX5856A toc13 SFDR (dBc) 70 75 OUTPUT POWER (dBm) AOUT = 0dBFS FFT PLOT (2MHz WINDOW) 0 MAX5856A toc10 90 80 MAX5856A toc 09 100 MAX5856A toc11 SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE (NO INTERPOLATION, fDAC = 165MHz, fOUT = 5MHz) OUTPUT POWER (dBm) MAX5856A Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL _______________________________________________________________________________________ Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL 8-TONE MTPR PLOT (NO INTERPOLATION, fDAC = 165MHz, fCENTER = 20.0052MHz) -30 -40 -50 -60 -70 2 x fT2 - fT1 2 x fT1 - fT2 -20 0 -30 -40 -50 -60 -70 -10 -50 -60 -70 -90 -90 -100 -100 -100 4.9 5.1 5.3 -80 19.0 18.5 5.5 19.5 20.0 20.5 21.0 21.5 28.5 OUTPUT FREQUENCY (MHz) AOUT = -18dBFS fT3 = 19.4550MHz fT6 = 20.4352MHz BW = 3MHz fT4 = 19.7553MHz fT7 = 20.7050MHz fT1 = 18.9550MHz fT5 = 20.2551MHz fT8 = 20.9451MHz fT2 = 19.2551MHz -40 -50 -60 -70 -30 -40 -50 -60 -70 -90 17.30 33.60 66.20 82.50 49.90 9.15 25.25 41.75 58.05 74.35 OUTPUT FREQUENCY (MHz) -30 -40 -50 -60 -90 -100 -110 -120 -130 -140 -150 15.2 57.2 42.9 85.8 71.5 114.4 143.2 100.1 128.7 30.5 31.0 31.5 PLL ENABLED fDATA = 125MHz PLL ENABLED fDATA = 100MHz PLL ENABLED fDATA = 150MHz -70 -80 -90 28.6 30.0 PHASE NOISE WITH PLL DISABLED AND ENABLED (fOUT = fDATA/4, 2x INTERPOLATION) -100 1.0 29.5 MAX5856A toc20 35.8MHz A: IN-BAND-RANGE B: OUT-OF-BAND RANGE -80 -80 -100 1.00 B NOISE DENSITY (dBm/Hz) -30 A -20 OUTPUT POWER (dBm) OUTPUT POWER (dBm) -20 0 -10 MAX5856A toc19 MTPR = 76dBc MAX5856A toc18 0 29.0 OUTPUT FREQUENCY (MHz) AOUT = -18dBFS fT3 = 29.3936MHz fT6 = 30.5911MHz BW = 3MHz fT4 = 29.6995MHz fT7 = 30.8271MHz fT1 = 28.8866MHz fT5 = 30.2851MHz fT8 = 31.1417MHz fT2 = 29.0912MHz 8-TONE MTPR PLOT FOR DAC UPDATE NYQUIST WINDOW 8-TONE MTPR PLOT FOR NYQUIST WINDOW (4x INTERPOLATION, fDAC = 286.4MHz, fCENTER = 20MHz, (NO INTERPOLATION, fDAC = 165MHz, INPUT TONES SPACING ~300kHz, AOUT = -18dBFS) fCENTER = 19.9569MHz, AOUT = -18dBFS) -10 fT6 fT7 fT8 -40 -90 OUTPUT FREQUENCY (MHz) AOUT = -6dBFS fT1 = 4.9450MHz BW = 1MHz fT2 = 5.0683MHz fT5 -30 -80 4.7 fT1 fT2 fT3 fT4 -20 -80 4.5 MAX5856A toc17 fT2 fT5 fT6 f f T7 T8 OUTPUT POWER (dBm) fT1 fT1 fT2 fT3 fT4 -10 OUTPUT POWER (dBm) OUTPUT POWER (dBm) -20 0 MAX5856A toc15 0 -10 8-TONE MTPR PLOT (4x INTERPOLATION, fDAC = 286.4MHz, fCENTER = 29.9923MHz) MAX5856A toc16 2-TONE IMD PLOT (NO INTERPOLATION, fDAC = 165MHz) PLL DISABLED, fDATA = 75MHz 0 0.5MHz/div 5 OFFSET FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) _______________________________________________________________________________________ 9 MAX5856A Typical Operating Characteristics (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.) 0.06 0.04 -40 0.02 -50 -60 -70 0.03 0 -0.02 -0.04 B -80 RL = 0 0.05 DNL (LSB) -30 INL (LSB) 0.01 -0.01 -0.03 -0.06 -0.05 -0.08 A 5 -0.10 15 1MHz/div -0.07 0 32 64 96 128 160 192 224 256 0 POWER DISSIPATION vs. fDAC 400 350 300 900 800 700 4x INTERPOLATION 600 500 400 1000 2x INTERPOLATION 99 132 4x INTERPOLATION fCLK = 200MHz fOUT = 5MHz 700 600 500 400 NO INTERPOLATION fCLK = 165MHz fOUT = 5MHz 200 0 66 800 300 200 200 2x INTERPOLATION fCLK = 200MHz fOUT = 5MHz 900 300 250 96 128 160 192 224 256 DIGITAL INPUT CODE POWER DISSIPATION vs. SUPPLY VOLTAGE MAX5856A toc25 450 1000 POWER DISSIPATION (mW) NO INTERPOLATION 33 64 POWER DISSIPATION vs. fDAC MAX5856A toc24 500 0 32 DIGITAL INPUT CODE OUTPUT FREQUENCY (MHz) 50 165 100 150 200 250 300 MAX5856A toc26 -90 -100 POWER DISSIPATION (mW) OUTPUT POWER (dBm) -20 RL = 0 0.08 0.07 MAX5856A toc22 A: PLL DISABLED B: PLL ENABLED DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE 0.10 MAX5856A toc21 0 -10 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5856A toc23 FFT PLOT FOR PLL DISABLED AND PLL ENABLED (fOUT = 10MHz, 2x INTERPOLATION) POWER DISSIPATION (mW) 2.7 2.8 fDAC (MHz) 2.9 3.0 3.1 SUPPLY VOLTAGE (V) fDAC (MHz) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE 1.25 1.24 1.23 1.22 1.21 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 1.20 2.7 2.8 2.9 3.0 3.1 SUPPLY VOLTAGE (V) 10 MAX5856A toc28 1.26 1.28 INTERNAL REFERENCE VOLTAGE (V) MAX5856A toc27 1.27 INTERNAL REFERENCE VOLTAGE (V) MAX5856A Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL 3.2 3.3 -40 -15 10 35 60 TEMPERATURE (C) ______________________________________________________________________________________ 85 3.2 3.3 Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL DYNAMIC RESPONSE RISE TIME DYNAMIC RESPONSE FALL TIME MAX5856A toc29 MAX5856A toc30 200mV/div RL = 50 SINGLE ENDED 200mV/div RL = 50 SINGLE ENDED 10ns/div 10ns/div Pin Description PIN NAME 1 DA7/PD 2 FUNCTION Channel A Input Data Bit 7 (MSB)/Power-Down Control Bit: 0: Enter DAC standby mode (DACEN = 0) or power up DAC (DACEN = 1). 1: Enter power-down mode. Channel A Input Data Bit 6/DAC Enable Control Bit: 0: Enter DAC standby mode with PD = 0. DA6/DACEN 1: Power up DAC with PD = 0. X: Enter power-down mode with PD = 1 (X = don't care). 3 DA5/F2EN Channel A Input Data Bit 5/Second Interpolation Filter Enable Bit: 0: Interpolation mode is determined by F1EN. 1: Enable 4x interpolation mode. (F1EN must equal 1.) 4 DA4/F1EN Channel A Input Data Bit 4/First Interpolation Filter Enable Bit: 0: Interpolation disable. 1: Enable 2x interpolation. 5 DA3/G3 6, 19, 47 DGND Digital Ground 7, 18, 48 DVDD Digital Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section. 8 DA2/G2 Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 3 Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 2 9 DA1/G1 Channel A Input Data Bit 1/Channel A Gain Adjustment Bit 1 10 DA0/G0 Channel A Input Data Bit 0/Channel A Gain Adjustment Bit 0 11, 12, 25, 26, 37, 38 N.C. No Connection. Not connected internally. 13 DB7 Channel B Input Data Bit 7 (MSB) 14 DB6 Channel B Input Data Bit 6 ______________________________________________________________________________________ 11 MAX5856A Typical Operating Characteristics (continued) (AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.) Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL MAX5856A Pin Description (continued) 12 PIN NAME 15 DB5 Channel B Input Data Bit 5 FUNCTION 16 DB4 Channel B Input Data Bit 4 17 DB3 Channel B Input Data Bit 3 20 CLK Clock Output/Input. CLK becomes an input when the PLL is enabled. CLK is an output when the PLL is disabled. 21 IDE Interleave Data Mode Enable. When IDE is high, data for both DAC channels is written through port A (bits DA7-DA0). When IDE is low, channel A data is latched on the rising edge of CLK and channel B is latched on the falling edge of CLK. 22 DB2 Channel B Input Data Bit 2 23 DB1 Channel B Input Data Bit 1 24 DB0 Channel B Input Data Bit 0 27 CW Active-Low Control Word Write Pulse. The control word is latched on the falling edge of CW. 28 LOCK PLL Lock Signal Output. High level indicates that PLL is locked to the CLK signal. 29 PLLEN PLL Enabled Input. PLL is enabled when PLLEN is high. 30 CLKXP Differential Clock Input Positive Terminal. Connect to PGND when the PLL is enabled. Bypass CLKXP with a 0.01F capacitor to PGND when CLKXN is in single-ended mode. 31 CLKXN Differential Clock Input Negative Terminal. Connect to PVDD when the PLL is enabled. Bypass CLKXN with a 0.01F capacitor to PGND when CLKXP is in single-ended mode. 32 PVDD PGND PLL Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section. 33 34 PLLF PLL Loop Filter. Connect a 4.12k resistor in series with a 100pF capacitor between PLLF and PGND. 35 REN Active-Low Reference Enable. Connect REN to AGND to activate the on-chip 1.24V reference. 36 REFO Reference I/O. REFO serves as the reference input when the internal reference is disabled. If the internal 1.24V reference is enabled, REFO serves as the output for the internal reference. When the internal reference is enabled, bypass REFO to AGND with a 0.1F capacitor. 39 REFR Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET between REFR and AGND. The output full-scale current is equal to 32 x VREFO / RSET. 40, 46 AVDD Analog Power Supply. See Power Supplies Bypassing, Decoupling, and Layout section. 41 OUTNB Channel B Negative Analog Current Output 42 OUTPB Channel B Positive Analog Current Output 43 AGND Analog Ground 44 OUTNA Channel A Negative Analog Current Output 45 OUTPA Channel A Positive Analog Current Output -- EP PLL Ground Exposed Pad. Connect to the ground plane. ______________________________________________________________________________________ Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL DVDD AVDD PVDD CLKXP CLK CLKXN LOCK MAX5856A PLL CLOCK MULTIPLIER PLLEN PLLF 8 8 DB7-DB0 8 2x DIGITAL INTERPOLATION FILTER 8 2x DIGITAL INTERPOLATION FILTER 8 8 2x DIGITAL INTERPOLATION FILTER 8 2x DIGITAL INTERPOLATION FILTER 8 INPUT REGISTER DA7-DA0 INPUT REGISTER OUTPA 8-BIT 300MHz DAC OUTNA OUTPB 8-BIT 300MHz DAC OUTNB F1EN IDE F2EN CONTROL REGISTER CW DGND PGND Detailed Description The MAX5856A dual, high-speed, 8-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal reconstruction. The MAX5856A combines two DAC cores with 4x/2x/1x programmable digital interpolation filters, a PLL clock multiplier, divide-by-N clock output, and an onchip 1.24V reference. The DAC current outputs can be configured for differential or single-ended operation. The full-scale output current range is adjustable from 2mA to 20mA to optimize power dissipation and gain control. The MAX5856A accepts an input data rate up to 165MHz or a DAC conversion rate up to 300MHz. The inputs are latched on the rising edge of the clock. The outputs are latched on the following rising edge. The two-stage digital interpolation filters are programmable to 4x, 2x, or no interpolation. When operating in 4x interpolation mode, the interpolator increases the DAC conversion rate by a factor of four, providing a four-fold increase in separation between the reconstructed waveform spectrum and its first image. The on-chip PLL clock multiplier generates and distributes all internal, synchronized high-speed clock signals required by the input data latches, interpolation filters, and DAC cores. The on-chip PLL includes phase detector, VCO, prescalar, and charge pump circuits. The PLL can be enabled or disabled through PLLEN. 1.2V REFERENCE AND CONTROL AMPLIFIER REFO REN REFR RSET AGND The analog and digital sections of the MAX5856A have separate power supply inputs (AVDD and DVDD). Also, a separate supply input is provided for the PLL clock multiplier (PVDD). AVDD, DVDD, and PVDD operate from a 2.7V to 3.3V single supply. The MAX5856A features three power modes: normal, standby, and power-down. These modes allow efficient power management. In power-down, the MAX5856A consumes only 1A of supply current. Wake-up time from standby mode to normal DAC operation is 0.7s. Programming the DAC An 8-bit control word routed through channel A's data port programs the gain matching, interpolator configuration, and operational mode of the MAX5856A. The control word is latched on the falling edge of controlword write pulse (CW). The CW signal is asynchronous with CLK and CLKXN/CLKXP; therefore, the conversion clock (CLK or CLKXN/CLKXP) can run uninterrupted when a control word is written to the device. Table 1 illustrates the control word format and function. The gain on channel A can be adjusted to achieve gain matching between two channels in a user's system. The gain on channel A can be adjusted from +0.4dB to -0.35dB in steps of 0.05dB by using bits G3 to G0 (see Table 3). ______________________________________________________________________________________ 13 MAX5856A Functional Diagram MAX5856A Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL Device Power-Up and States of Operation At power-up, the MAX5856A is configured in no-interpolation mode with a gain adjustment setting of 0dB and a fully operational converter. In shutdown, the MAX5856A consumes only 1A of supply current, and in standby the current consumption is 4.4mA. Wake-up time from standby mode to normal operation is 0.7s. Interpolation Filters The MAX5856A features a 2-stage, 2x digital interpolating filter based on 43-tap and 23-tap FIR topology. F1EN and F2EN enable the interpolation filters. F1EN = 1 enables the first filter for 2x interpolation and F2EN = 1 enables the second filter for combined 4x interpolation. To bypass and disable both interpolation filters (no-interpolation mode or 1x mode) set F1EN = F2EN = 0. When set for 1x mode the filters are powered down and consume virtually no current. An illegal condition is defined by: F1EN = 0, F2EN = 1 (see Table 2 for configuration modes). The programmable interpolation filters multiply the MAX5856A input data rate by a factor of two or four to separate the reconstructed waveform spectrum and the first image. The original spectral images, appearing around multiples of the DAC input data rate, are attenuated at least 60dB by the internal digital filters. This feature provides three benefits: 1) Image separation reduces complexity of analog reconstruction filters. 2) Lower input data rates eliminate board-level highspeed data transmission. 3) Sin(x)/x rolloff is reduced over the effective bandwidth. Figure 2 shows an application circuit and Figure 3 illustrates a practical example of the benefits when using the MAX5856A with 4x-interpolation mode. The example illustrates signal synthesis of a 20MHz IF with a 10MHz bandwidth. Three options can be considered to address the design requirements. The tradeoffs for each solution are shown in Table 4. Table 1. Control Word Format and Function MSB LSB PD DACEN F2EN F1EN CONTROL WORD PD DACEN G3 G2 G1 G0 FUNCTION Power-down; The part enters power-down mode if PD = 1. DAC Enable; When DACEN = 0 and PD = 0, the part enters standby mode. F2EN Filter Enable; When F2EN = 1 and F1EN = 1, 4x interpolation is enabled. When F2EN = 0, the interpolation mode is determined by F1EN. F1EN Filter Enable; When F1EN = 1 and F2EN = 0, 2x interpolation is active. With F1EN = 0 and F2EN = 0, the interpolation is disabled. G3 Bit 3 (MSB) of gain adjust word. G2 Bit 2 of gain adjust word. G1 Bit 1 of gain adjust word. G0 Bit 0 (LSB) of gain adjust word. Table 2. Configuration Modes Table 3. Gain Difference Setting MODE PD DACEN F2EN F1EN No interpolation 0 1 0 0 GAIN ADJUSTMENT ON CHANNEL A (dB) G3 G2 G1 G0 2x interpolation 0 1 0 1 +0.4 0 0 0 0 4x interpolation 0 1 1 1 0 1 0 0 0 Standby 0 0 X X -0.35 1 1 1 1 Power-down 1 X X X Power-up 0 1 X X X = Don't care. F1EN = 0, F2EN = 1: illegal condition. 14 ______________________________________________________________________________________ Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL MAX5856A FS ANALOG OUT SPECIFIED OVER ENTIRE SUPPLY RANGE +2.7V TO +3.3V SINGLE SUPPLY +2.7V TO +3.3V SINGLE 8-BIT BUS SAVES I/O PINS DIGITAL BASEBAND OFDM PROCESSOR QAM-MAPPER DATA LATCH 8-BIT BUS INTERPOLATING FILTERS 4X/2X 8 CHA DAC AOUT DATA LATCH 8-BIT BUS INTERPOLATING FILTERS 4X/2X 8 CHB DAC BOUT INTERLEAVE DATA LATCH DIV-4 DIV-2 DIV-1 MAX5856A DATA CLOCK OUT fDATA = 71.6MHz CLOCK SOURCE FDAC = 286.4MHz Figure 2. Typical Application Circuit Table 4. Benefits of Interpolation OPTION SOLUTION ADVANTAGE DISADVANTAGE 1 * No interpolation * 2.6x oversample * fDAC = fDATA = 78MHz * Low data rate * Low clock rate * High-order filter * Filter gain/phase match 2 * No interpolation * 8x oversample * fDAC = fDATA = 240MHz * Push image to fIMAGE = 210MHz * Lower order filter * Filter gain/phase match * High clock rate * High data rate 3 * 4x interpolation * fDAC = 286.4MHz, fDATA = 71.6MHz * Passband attenuation = 0.1dB * Push image to 256MHz * Low data rate * Low-order filter * 60dB image attenuate * Filter gain/phase match * None ______________________________________________________________________________________ 15 MAX5856A Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL IMAGE SEPARATION = 18MHz LESS THAN ONE OCTAVE HIGH ORDER ANALOG FILTER SOLUTION 1 fOUT 20MHz 10MHz IMAGE fDAC - fOUT 48MHz fDAC 78MHz IMAGE fDAC + fOUT 108MHz FREQUENCY AXIS NOT TO SCALE IMAGE SEPARATION = 180MHz HIGH-SPEED CLK = 240MHz LOWER ORDER ANALOG FILTER SOLUTION 2 fOUT 20MHz BW = 10MHz FREQUENCY AXIS NOT TO SCALE IMAGE fDAC IMAGE fDAC - fOUT 240MHz fDAC + fOUT 210MHz 270MHz SIMPLE ANALOG FILTER DIGITAL FILTER ATTENUATION > 60dB SOLUTION 3 fDATA 71.6MHz fOUT 20MHz BW = 10MHz NEW FIRST IMAGE SEPARATION > 3-OCTAVES fDAC IMAGE IMAGE fDAC - fOUT 286MHz fDAC + fOUT 256MHz 316MHz FREQUENCY AXIS NOT TO SCALE Figure 3. MAX5856A in 4x Interpolation Mode This example demonstrates that 4x interpolation with digital filtering yields significant benefits in reducing system complexity, improving dynamic performance, and lowering cost. Data can be written to the MAX5856A at much lower speeds while achieving image attenuation greater than 60dB and image separation beyond three octaves. The main benefit is in analog reconstruction fil- 16 ter design. Reducing the filter order eases gain/phase matching while lowering filter cost and saving board space. Because the data rate is lowered to 71.6MHz, the setup and hold times are manageable and the clock signal source is simplified, which results in improved system reliability and lower cost. ______________________________________________________________________________________ Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL The MAX5856A features an on-chip PLL clock multiplier, which generates all internal, synchronized highspeed clock signals required by the input data latches, interpolation filters, and DAC cores. The on-chip PLL includes a phase detector, VCO, prescalar, and charge-pump circuits. The PLL can be enabled or disabled through PLLEN. To enable PLL, set PLLEN = 1. With the PLL enabled (PLLEN = 1) and 4x/2x interpolation enabled, an external low-frequency clock reference source may be applied to CLK pin. The clock reference source serves as the input data clock. The on-chip PLL multiplies the clock reference by a factor of two (2x) or a factor of four (4x). The input data rate range and CLK frequency are set by the selected interpolation mode. In 2x interpolation mode, the data rate range is 75MHz to 150MHz. In 4x interpolation mode, the data rate range is 37.5MHz to 75MHz. Note: When the PLL is enabled, CLK becomes an input, requiring CLKXP to be pulled low and CLKXN to be pulled high. To obtain the best phase noise performance, disable the PLL function. With the PLL disabled (PLLEN = 0) and 4x/2x interpolation enabled, an external conversion clock is applied at CLKXN/CLKXP. The conversion clock at CLKXN/CLKXP has a frequency range of 0 to 300MHz (see Table 5). This clock is buffered and distributed by the MAX5856A to drive the interpolation filters and DAC cores. In this mode, CLK becomes a divide-by-N (DIVN) output at either a divide-by-two or divide-by-four rate. The DIV-N factor is set by the selected interpola- tion mode. The CLK output, at DIV-N rate, must be used to synchronize data into the MAX5856A data ports. In this mode, keep the capacitive load at the CLK output low (10pF or less at fDAC = 165MHz). With the interpolation disabled (1x mode) and the PLL disabled (PLLEN = 0), the input clock at CLKXN/CLKXP can be used to directly update the DAC cores. In this mode, the maximum data rate is 165MHz. Internal Reference and Control Amplifier The MAX5856A provides an integrated 50ppm/C, 1.24V, low-noise bandgap reference that can be disabled and overridden with an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is connected to AGND, the internal reference is selected and REFO provides a 1.24V (50A) output. Buffer REFO with an external amplifier, when driving a heavy load. The MAX5856A also employs a control amplifier designed to simultaneously regulate the full-scale output current (I FS ) for both outputs of the devices. Calculate the output current as: IFS = 32 x IREF where I REF is the reference output current (I REF = VREFO/RSET) and IFS is the full-scale output current. R SET is the reference resistor that determines the amplifier output current of the MAX5856A (Figure 4). This current is mirrored into the current-source array where IFS is equally distributed between matched current segments and summed to valid output current readings for the DACs. OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS REN AGND 1.24V BANDGAP REFERENCE MAX4040 REFO CCOMP* REFR CURRENTSOURCE ARRAY IREF IFS AGND IREF = VREF RSET RSET AGND MAX5856A *COMPENSATION CAPACITOR (CCOMP 100nF) Figure 4. Setting IFS with the Internal 1.24V Reference and the Control Amplifier ______________________________________________________________________________________ 17 MAX5856A PLL Clock Multiplier and Clocking Modes MAX5856A Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL External Reference Detailed Timing To disable the internal reference of the MAX5856A, connect REN to AVDD. Apply a temperature-stable, external reference to REFO to set the full-scale output (Figure 5). For improved accuracy and drift performance, choose a fixed output voltage reference such as the MAX6520 bandgap reference. The MAX5856A accepts an input data rate up to 165MHz or a DAC conversion rate of up to 300MHz. The inputs are latched on the rising edge of the clock. The outputs are latched on the following rising edge. AVDD 10F REN 0.1F AGND 1.24V BANDGAP REFERENCE AVDD EXTERNAL 1.24V REFERENCE REFO CURRENTSOURCE ARRAY REFR MAX6520 IFS IREF AGND RSET MAX5856A AGND Figure 5. MAX5856A with External Reference Table 5. PLL Clocking Modes PLLEN F2EN F1EN DIFFERENTIAL CLOCK FREQUENCY fCLKDIFF (MHz) CLOCK FREQUENCY fCLK (MHz) DAC RATE fDAC INTERPOLATION MAX SIGNAL BANDWIDTH (MHz) 1 0 0 N/A (tie CLXP low and CLXN high) 0 to 165 (input) fCLK 1x 82 1 0 1 N/A (tie CLXP low and CLXN high) 75 to 150 (input) 2* fCLK 2x 63 1 1 1 N/A (tie CLXP low and CLXN high) 37 to 75 (input) 4* fCLK 4x 31 0 0 0 0 to 165 fCLKDIFF (output) fCLKDIFF 1x 82 0 0 1 0 to 300 fCLKDIFF / 2 (output) fCLKDIFF 2x 63 0 1 1 0 to 300 fCLKDIFF / 4 (output) fCLKDIFF 4x 31 0 1 0 1 1 0 18 Illegal ______________________________________________________________________________________ Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL If the PLL is enabled (PLLEN = 1), then CLK becomes an input and the clock signal may be applied to CLK. In Figure 6, the CLK signal is multiplied by a factor of four by the PLL and distributed to the interpolation filters and DAC cores. In this mode, CLKXP must be pulled low and CLKXN pulled high. CLKXN The MAX5856A can operate with a single-ended clock input used as both data clock and conversion clock. To operate the device in this mode, disable the interpolation filters and enable the PLL (PLLEN = 1). Apply a singleended clock input at CLK. The CLK signal acts as the data synchronization clock and DAC core conversion clock. Though the PLL is enabled, the lock pin (LOCK) is not valid and the PLL is internally disconnected from the interpolating filters and DAC cores. In this mode, CLKXP must be pulled low and CLKXN pulled high. Figure 6 shows the timing for the CW. An 8-bit control word routed through channel A's data port programs the gain matching, interpolator configuration, and operational mode of the MAX5856A. The control word is latched on the falling edge of CW. The CW signal is asynchronous with conversion clocks CLK and CLKXN/CLKXP; therefore, the conversion clock (CLK or CLKXN/CLKXP) can run uninterrupted when a control word is written to the device. 1 tCXD tCXD CLKXP1 tCWH CW tCWS CLK DA0-DA7/ CONTROL WORD DAN DB0-DB7 DBN CONTROL WORD DAN+1 DBN+1 tDCSR tDCHR 1. CLKXP AND CLKXN MUST BE PRESENT ONLY WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND. THE DIAGRAM SHOWS 4x INTERPOLATION. 2. CLK IS AN OUTPUT WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND; OTHERWISE, IT IS AN INPUT. Figure 6. Timing Diagram for Noninterleave Data Mode (IDE = Low) ______________________________________________________________________________________ 19 MAX5856A Figure 6 illustrates the DAC write cycle in 4x interpolation mode. With the interpolation feature enabled, the device can operate with the PLL enabled or disabled. To obtain best phase noise performance, disable the PLL and keep the capacitive load at the CLK output low (10pF or less at fDAC = 165MHz). With the PLL disabled (PLLEN = 0), the clock signal is applied to CLKXP/CLKXN and internally divided by 4 to generate the DAC's CLK signal. The CLK signal is a divide-by-4 output, used to synchronize data into the MAX5856A data ports. The CLKXP/CLKXN signal drives the interpolation filters and DAC cores at the desired conversion rate. MAX5856A Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL CLKXN1 tCXD CLKXP tCXD 1 CLK2 DAN DA0-DA7 tDCSR DBN+1 DAN+1 DAN+2 DBN+2 tDCHR tDCSF tDCHF 1. CLKXP AND CLKXN MUST BE PRESENT ONLY WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND. THE DIAGRAM SHOWS 4x INTERPOLATION. 2. CLK IS AN OUTPUT WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND; OTHERWISE, IT IS AN INPUT. Figure 7. Timing Diagram for Interleave Data Mode (IDE = High) The MAX5856A can operate in interleave data mode by setting IDE = 1. In interleave data mode, data for both DAC channels is written through input port A. Channel B data is written on the falling edge of the CLK signal and then channel A data is written on the following rising edge of the CLK signal. Both DAC outputs (channel A and B) are updated simultaneously on the next rising edge of CLK. In interleave data mode, the maximum input data rate per channel is one-half the rate of noninterleave mode. Interleave data mode is an attractive feature that lowers digital I/O pin count, reduces digital ASIC cost, and improves system reliability (Figure 7). AVDD DVDD PVDD 50 OUTPA DA0-DA7 1/2 MAX5856A VOUTA SINGLE ENDED 100 8 OUTNA 50 Applications Information Differential-to-Single-Ended Conversion The MAX5856A exhibits excellent dynamic performance to synthesize a wide variety of modulation schemes, including high-order QAM modulation with OFDM. Figure 8 shows a typical application circuit with output transformers performing the required differential-to-single-ended signal conversion. In this configuration, the MAX5856A operates in differential mode, which reduces even-order harmonics, and increases the available output power. 50 OUTPB DB0-DB7 1/2 MAX5856A VOUTB SINGLE ENDED 100 8 OUTNB 50 AGND DGND PGND Figure 8. Application with Output Transformer Performing Differential to Single-Ended Conversion 20 ______________________________________________________________________________________ Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL AVDD DVDD PVDD 50 DA0-DA7 OUTPA 1/2 MAX5856A 8 OUTNA 50 50 DB0-DB7 OUTPB 1/2 MAX5856A 8 OUTNB 50 Power Supplies, Bypassing, Decoupling, and Layout Grounding and power-supply decoupling strongly influence the MAX5856A performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5856A. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the power-supply and filter configuration to achieve optimum dynamic performance. Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. Run high-speed signals on lines directly above the ground plane. The MAX5856A has separate analog and digital ground buses (AGND, PGND, and DGND, respectively). Provide separate analog, digital, and clock ground sections on the PC board with only one point connecting the three planes. The ground connection points should be located underneath the device and connected to the exposed paddle. Run digital signals above the digital ground plane and analog/clock signals above the analog/clock ground plane. Digital signals should be kept away from sensitive analog, clock, and reference inputs. Keep digital signal paths short and metal trace lengths matched to avoid propagation delay and data skew mismatch. MAX5856A Differential DC-Coupled Configuration Figure 9 shows the MAX5856A output operating in differential DC-coupled mode. This configuration can be used in communication systems employing analog quadrature upconverters and requiring a baseband sampling, dualchannel, high-speed DAC for I/Q synthesis. In these applications, information bandwidth can extend from 10MHz down to several hundred kilohertz. DC-coupling is desirable in order to eliminate long discharge time constants that are problematic with large, expensive coupling capacitors. Analog quadrature upconverters have a DC common-mode input requirement of typically 0.7V to 1.0V. The MAX5856A differential I/Q outputs can maintain the desired full-scale signal level at the required 0.7V to 1.0V DC common-mode voltage when powered from a single 2.85V (5%) supply. The MAX5856A meets this low-power requirement with minimal reduction in dynamic range while eliminating the need for level-shifting resistor networks. AGND DGND PGND Figure 9. Application with DC-Coupled Differential Outputs The MAX5856A includes three separate power-supply inputs: analog (AV DD ), digital (DV DD ), and clock (PVDD). Use a single linear regulator power source to branch out to three separate power-supply lines (AVDD, DVDD, PVDD) and returns (AGND, DGND, PGND). Filter each power-supply line to the respective return line using LC filters comprising ferrite beads and 10F capacitors. Filter each supply input locally with 0.1F ceramic capacitors to the respective return lines. Note: To maintain the dynamic performance of the Electrical Characteristics, ensure the voltage difference between DV DD , AV DD , and PV DD does not exceed 150mV. Thermal Characteristics and Packaging Thermal Resistance 48-lead TQFP-EP: JA = 27.6C/W Keep the device junction temperature below +125C to meet specified electrical performance. Lower the power-supply voltage to maintain specified performance when the DAC update rate approaches 300Msps and the ambient temperature equals +85C. ______________________________________________________________________________________ 21 MAX5856A Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL The MAX5856A is packaged in a 48-pin TQFP-EP package, providing design flexibility, increased thermal efficiency, and optimized AC performance of the DAC. The EP enables the implementation of grounding techniques necessary to ensure highest performance. In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR)-flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP, ensures the proper attachment and grounding of the DAC. Designing vias into the land area and implementing large ground planes in the PC board design achieve optimal DAC performance. Use an array of 3 x 3 (or greater) vias (0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 48-pin TQFPEP package. Dynamic Performance Parameter Definitions Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of all essential harmonics (within a Nyquist window) of the input signal to the fundamental itself. This can be expressed as: THD = 20 x log (V 2 2 2 2 2 + V 3 + V 4 ... + ...VN / V1 ) where V1 is the fundamental amplitude, and V2 through VN are the amplitudes of the 2nd through Nth order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next-largest spectral component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the DAC's fullscale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. Multitone Power Ratio (MTPR) A series of equally spaced tones are applied to the DAC with one tone removed from the center of the range. MTPR is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequencies), which appears as the largest spur at the frequency of the missing tone in the sequence. This test can be performed with any number of input tones; however, four and eight tones are among the most 22 common test conditions for CDMA- and GSM/EDGEtype applications. Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in dBc of either output tone to the worst 3rd-order (or higher) IMD products. Static Performance Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification -1 LSB guarantees a monotonic transfer function. Offset Error Offset error is the current flowing from positive DAC output when the digital input code is set to zero. Offset error is expressed in LSBs. Gain Error A gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. The ideal current is defined by reference voltage at VREFO / IREF x 32. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value (within the converter's specified accuracy). Glitch Impulse A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. This occurs due to timing variations between the bits. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV-s. Chip Information TRANSISTOR COUNT: 178,376 PROCESS: CMOS ______________________________________________________________________________________ Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL 48L,TQFP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5856A Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)