AM26LS32AC, AM26LS32AI, AM26LS33AC, AM26LS32AM, AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115D - OCTOBER 1980 - REVISED MARCH 2002 D D D D D D D D D AM26LS32AC . . . D, N, OR NS PACKAGE AM26LS32AI, AM26LS33AC . . . D OR N PACKAGE AM26LS32AM, AM26LS33AM . . . J PACKAGE (TOP VIEW) AM26LS32A Devices Meet or Exceed the Requirements of ANSI TIA/EIA-422-B, TIA/EIA-423-B, and ITU Recommendations V.10 and V.11 AM26LS32A Devices Have 7-V Common-Mode Range With 200-mV Sensitivity AM26LS33A Devices Have 15-V Common-Mode Range With 500-mV Sensitivity Input Hysteresis . . . 50 mV Typical Operate From a Single 5-V Supply Low-Power Schottky Circuitry 3-State Outputs Complementary Output-Enable Inputs Input Impedance . . . 12 k Min Designed to Be Interchangeable With Advanced Micro Devices AM26LS32 and AM26LS33 1B 1A 1Y G 2Y 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4B 4A 4Y G 3Y 3A 3B AM26LS32AM, AM26LS33AM . . . FK PACKAGE (TOP VIEW) 1A 1B NC VCC 4B D 1Y G NC 2Y 2A description 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A 4Y NC G 3Y 2B GND NC 3B 3A The AM26LS32A and AM26LS33A devices are quadruple differential line receivers for balanced and unbalanced digital data transmission. The enable function is common to all four receivers and offers a choice of active-high or active-low input. The 3-state outputs permit connection directly to a bus-organized system. Fail-safe design ensures that, if the inputs are open, the outputs always are high. 4 NC - No internal connection Compared to the AM26LS32 and the AM26LS33, the AM26LS32A and AM26LS33A incorporate an additional stage of amplification to improve sensitivity. The input impedance has been increased, resulting in less loading of the bus line. The additional stage has increased propagation delay; however, this does not affect interchangeability in most applications. The AM26LS32AC and AM26LS33AC are characterized for operation from 0C to 70C. The AM26LS32AI is characterized for operation from -40C to 85C. The AM26LS32AM and AM26LS33AM are characterized for operation over the full military temperature range of -55C to 125C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. AM26LS32 and AM26LS33 are trademarks of Advanced Micro Devices, Inc. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 AM26LS32AC, AM26LS32AI, AM26LS33AC, AM26LS32AM, AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115D - OCTOBER 1980 - REVISED MARCH 2002 FUNCTION TABLE (each receiver) DIFFERENTIAL A-B VID VIT IT+ VIT IT IT- VID VIT+ VID VIT IT- X Open ENABLES OUTPUT Y G G H X H X L H H X ? X L ? H X L X L L L H Z H X H X L H H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) logic diagram (positive logic) G G 1A 1B 2A 2B 3A 3B 4A 4B 2 4 12 2 1 6 7 10 9 14 15 POST OFFICE BOX 655303 3 5 11 13 1Y 2Y 3Y 4Y * DALLAS, TEXAS 75265 AM26LS32AC, AM26LS32AI, AM26LS33AC, AM26LS32AM, AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115D - OCTOBER 1980 - REVISED MARCH 2002 schematics of inputs and outputs EQUIVALENT OF EACH DIFFERENTIAL INPUT EQUIVALENT OF EACH ENABLE INPUT VCC TYPICAL OF ALL OUTPUTS VCC 85 NOM VCC 8.3 k NOM 100 k A Input Only 960 NOM 20 k NOM Enable Output Input 960 NOM 100 k B Input Only absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: Any differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W Case temperature for 60 seconds, TC: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the network ground terminal. 2. Differential voltage values are at the noninverting (A) input terminals with respect to the inverting (B) input terminals. 3. The package thermal impedance is calculated in accordance with JESD 51-7. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 125C POWER RATING FK 1375 mW 11.0 mW/C 880 mW 275 mW J 1375 mW 11.0 mW/C 880 mW 275 mW POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 AM26LS32AC, AM26LS32AI, AM26LS33AC, AM26LS32AM, AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115D - OCTOBER 1980 - REVISED MARCH 2002 recommended operating conditions VCC Supply voltage VIH VIL High-level input voltage AM26LS32AC, AM26LS32AI, AM26LS33AC AM26LS32AM, AM26LS33AM MIN NOM MAX 4.75 5 5.25 4.5 5 5.5 2 UNIT V V Low-level input voltage 0.8 AM26LS32A 7 AM26LS33A 15 V VIC Common mode input voltage Common-mode IOH IOL High-level output current -440 A Low-level output current 8 mA AM26LS32AC, AM26LS33AC TA Operating free-air temperature 0 V 70 AM26LS32AI -40 85 AM26LS32AM, AM26LS33AM -55 125 C electrical characteristics over recommended ranges of VCC, VIC, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT IT+ Positive-going g g input threshhold voltage VO = VOHmin min, IOH = -440 440 A VIT IT- Negative-going g g g input threshhold voltage VO = 0 0.45 45 V V, IOL = 8 mA VIK Hysteresis voltage (VIT+ - VIT-) Enable-input clamp voltage VOH High level output voltage High-level Vhys TYP MAX AM26LS32A 0.2 AM26LS33A 0.5 AM26LS32A AM26LS33A -0.2 -0.5 VCC = MIN, VCC =MIN,, VID = 1 V,, VI(G) = 0.8 V, IOH = -440 A Low level output voltage Low-level VCC = MIN,, VID = -1 V,, VI(G) = 0.8 V IOZ Off-state (high impedance state) (high-impedance output current VCC = MAX II Line input current VI = 15 V, VI = -15 V, II(EN) IIH Enable input current IIL rI Low-level enable current Input resistance VI = 0.4 V VIC = -15 V to 15 V, IOS Short-circuit output current VCC = MAX II = -18 mA AM26LS32AC AM26LS33AC AM26LS32AM, AM26LS32AI, AM26LS33AM V mV -1.5 V 2.7 V 2.5 IOL = 4 mA IOL = 8 mA 0.45 VO = 2.4 V 20 VO = 0.4 V -20 0.4 Other input at -10 V to 15 V 1.2 Other input at -15 V to 10 V -1.7 VI = 5.5 V VI = 2.7 V 100 One input to ac ground UNIT V 50 VOL High-level enable current MIN 12 -15 V A mA A 20 A -0.36 mA 15 k -85 mA ICC Supply current VCC = MAX, All outputs disabled 52 70 mA All typical values are at VCC = 5 V, TA = 25C, and VIC = 0. The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold levels only. Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 AM26LS32AC, AM26LS32AI, AM26LS33AC, AM26LS32AM, AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115D - OCTOBER 1980 - REVISED MARCH 2002 switching characteristics, VCC = 5 V, TA = 25C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output tPZH tPZL Output enable time to high level tPHZ tPLZ Output disable time from high level Propagation delay time, high-to-low-level output Output enable time to low level Output disable time from low level MIN pF CL = 15 pF, See Figure 1 CL = 15 pF, pF See Figure 1 CL = 5 pF, pF See Figure 1 TYP MAX 20 35 22 35 17 22 20 25 21 30 30 40 UNIT ns ns ns PARAMETER MEASUREMENT INFORMATION VCC Test Point RL = 2 k 2.5 V S1 From Output Under Test CL (see Note A) Input 0 0 -2.5 V 5 k tPLH See Note B tPHL VOH Output S2 1.3 V 1.3 V VOL S1 and S2 Closed TEST CIRCUIT VOLTAGE WAVEFORMS FOR tPLH, tPHL 5 ns 90% Enable G 1.3 V 5 ns 3V 90% 10% See Note C 90% 90% 10% Output S1 Open S2 Closed 0 See Note C 3V 90% 90% 10% S1 Closed S2 Closed tPZL VOH 1.4 V S1 Closed S2 Closed 1.3 V Output VOLTAGE WAVEFORMS FOR tPHZ, tPZH S1 Closed S2 Open 3V 1.3 V 1.3 V 10% 1.3 V tPHZ 1.3 V 10% 0 0.5 V 3V 90% 1.3 V Enable G 10% tPZH 5 ns 10% 0 1.3 V 1.3 V 90% Enable G 1.3 V 10% Enable G 5 ns tPLZ 0 1.4 V VOL 0.5 V VOLTAGE WAVEFORMS FOR tPLZ, tPZL NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Enable G is tested with G high; G is tested with G low. Figure 1 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 AM26LS32AC, AM26LS32AI, AM26LS33AC, AM26LS32AM, AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115D - OCTOBER 1980 - REVISED MARCH 2002 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 5 5 4 3 VOH - High-Level Output Voltage - V VOH - High-Level Output Voltage - V VID = 0.2 V TA = 25C VCC = 5.25 V VCC = 5 V 2 VCC = 5.5 V VCC = 4.75 V 1 VCC = 4.5 V VCC = 5 V VID = 0.2 mV IOH = -440 A 4 3 2 1 0 0 -10 -20 -30 -40 -50 0 IOH - High-Level Output Current - mA 0 10 VCC = 5.5 V and VCC = 4.5 V applies to M-suffix devices only. 20 30 40 50 60 TA - Free-Air Temperature - C LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 0.5 0.6 VCC = 5 V TA = 25C VID = -0.2 mV 0.5 VOL - Low-Level Output Voltage - V VOL - Low-Level Output Voltage - V 80 Figure 3 Figure 2 0.4 0.3 0.2 0.1 0 VCC = 5 V VID = -0.2 V IOL = 8 mA 0.4 0.3 0.2 0.1 0 0 15 20 25 10 IOL - Low-Level Output Current - mA 5 30 0 10 Figure 4 6 70 20 30 40 50 60 TA - Free-Air Temperature - C Figure 5 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 70 80 AM26LS32AC, AM26LS32AI, AM26LS33AC, AM26LS32AM, AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115D - OCTOBER 1980 - REVISED MARCH 2002 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs ENABLE G VOLTAGE OUTPUT VOLTAGE vs ENABLE G VOLTAGE 5 5 VID = 0.2 V TA = 25C Load = 8 k to GND 4.5 VCC = 5.5 V 4 4 VCC = 5 V 3.5 VO - Output Voltage - V VO - Output Voltage - V VCC = 5 V VID = 0.2 V Load = 8 k to GND 4.5 VCC = 4.5 V 3 2.5 2 1.5 TA = 70C TA = 25C TA = 0C 3.5 3 2.5 2 1.5 1 1 0.5 0.5 0 0 0 0.5 1 1.5 2 2.5 0 3 0.5 1 1.5 2 2.5 3 Enable G Voltage - V Enable G Voltage - V Figure 6 Figure 7 OUTPUT VOLTAGE vs ENABLE G VOLTAGE OUTPUT VOLTAGE vs ENABLE G VOLTAGE 6 6 VCC = 5.5 V VCC = 5 V 5 5 VO - Output Voltage - V VO - Output Voltage - V VCC = 4.5 V 4 3 2 1 0 0.5 1 TA = 70C 3 2 1 VID = -0.2 V Load = 1 k to VCC TA = 25C 0 TA = 0C TA = 25C 4 1.5 2 2.5 3 VCC = 5 V VID = -0.2 V Load = 1 k to VCC 0 0 0.5 Enable G Voltage - V 1 1.5 2 2.5 3 Enable G Voltage - V Figure 9 Figure 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 AM26LS32AC, AM26LS32AI, AM26LS33AC, AM26LS32AM, AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115D - OCTOBER 1980 - REVISED MARCH 2002 TYPICAL CHARACTERISTICS AM26LS32A AM26LS33A OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 5 5 VO - Output Voltage - V 4 VCC = 5 V, IO = 0, TA = 25C 4.5 4 VIC = -7 V 3.5 VIC = 0 VO - Output Voltage - V 4.5 VCC = 5 V IO = 0 TA = 25C VIC = 7V 3 2.5 2 VIT- VIT+ 1.5 VIT- VIT+ VIT- VIT+ 2 0.5 100 VIT- VIT- VIT+ 1.5 0.5 50 VID - Differential Input Voltage - mV VIT- VIT+ 0 -200 -150 -100 -50 150 200 VIC = 15 V 2.5 1 0 VIC = 0 3 1 0 -200 -150 -100 -50 VIC = -15 V 3.5 0 VIT+ 50 100 150 200 VID - Differential Input Voltage - mV Figure 11 Figure 10 INPUT CURRENT vs INPUT VOLTAGE 4 3 I I - Input Current - mA 2 1 0 VCC = 0 -1 -2 VCC = 5 V The Unshaded Area Shows Requirements of Paragraph 4.2.1 of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B. -3 -4 -25 -20 -15 -10 -5 0 5 10 15 VI - Input Voltage - V Figure 12 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 20 25 AM26LS32AC, AM26LS32AI, AM26LS33AC, AM26LS32AM, AM26LS33AM QUADRUPLE DIFFERENTIAL LINE RECEIVERS SLLS115D - OCTOBER 1980 - REVISED MARCH 2002 APPLICATION INFORMATION 1/4 AM26LS31AC 1/4 AM26LS32AC Data In RT 1/4 AM26LS32AC Data Out 1/4 AM26LS33AC Data Out Data Out RT equals the characteristic impedance of the line. Figure 13. Circuit With Multiple Receivers POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated Product Folder: AM26LS33A, Quadruple Differential Line Receiver Contact Us Buy About TI TI Worldwide my.TI Advanced Search Keyword Part Number PRODUCT FOLDER | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY/PKG | SAMPLES | APPLICATION NOTES | MORE LITERATURE AM26LS33A, Quadruple Differential Line Receiver DEVICE STATUS: ACTIVE PARAMETER NAME AM26LS33A Receivers Per Package 4 Receiver (Vth) (mV) 500 Supply Voltage(s) (V) 5 Receiver tpd (ns) 35 ICC (max) (mA) 70 Footprint AM26LS32 FEATURES Back to Top AM26LS32A Devices Meet or Exceed the Requirements of ANSI TIA/EIA-422-B, TIA/EIA-423-B, and ITU Recommendations V.10 and V.11 AM26LS32A Devices Have 7-V Common-Mode Range With 200-mV Sensitivity AM26LS33A Devices Have 15-V Common-Mode Range With 500-mV Sensitivity Input Hysteresis . . . 50 mV Typical Operate From a Single 5-V Supply Low-Power Schottky Circuitry 3-State Outputs Complementary Output-Enable Inputs Input Impedance . . . 12 k Min Designed to Be Interchangeable With Advanced Micro Devices AM26LS32TM and AM26LS33TM AM26LS32 and AM26LS33 are trademarks of Advanced Micro Devices, Inc. DESCRIPTION Back to Top The AM26LS32A and AM26LS33A devices are quadruple differential line receivers for balanced and unbalanced digital data transmission. The enable function is common to all four receivers and offers a choice of active-high or active-low input. The 3-state outputs permit connection directly to a bus-organized system. Fail-safe design ensures that, if the inputs are open, the outputs always are high. Compared to the AM26LS32 and the AM26LS33, the AM26LS32A and AM26LS33A incorporate an additional stage of amplification to improve sensitivity. The input impedance has been increased, resulting in less loading of the bus line. The additional stage has increased propagation delay; however, this does not affect interchangeability in most applications. The AM26LS32AC and AM26LS33AC are characterized for operation from 0C to 70C. The AM26LS32AI is characterized for operation from -40C to 85C. The AM26LS32AM and AM26LS33AM are characterized for operation over the full military temperature range of -55C to 125C. TECHNICAL DOCUMENTS Back to Top To view the following documents, Acrobat Reader 4.0 is required. To download a document to your hard drive, right-click on the link and choose 'Save'. DATASHEET Back to Top Full datasheet in Acrobat PDF: am26ls33a.pdf (145 KB,Rev.D) (Updated: 03/13/2002) APPLICATION NOTES Back to Top file:///G|/imaging/BITTING/CPL/20030422/04212003_9/TXII/042120003_HTML/am26ls33a.html (1 of 3) [22-Apr-03 12:27:44 PM] Product Folder: AM26LS33A, Quadruple Differential Line Receiver Analog Applications Journal (Rev. A) (SLYT010A - Updated: 03/17/2000) Back to Top MORE LITERATURE Enhanced Plastic Portfolio Brochure (SGZB004, 387 KB - Updated: 08/19/2002) QML Class V Space Products Military Brief (Rev. A) (SGZN001A, 257 KB - Updated: 10/07/2002) Back to Top SAMPLES ORDERABLE DEVICE PACKAGE INDUSTRY (TI) PINS TEMP (C) STATUS AM26LS33ACD SOIC (D) 16 0 TO 70 AM26LS33ACN PDIP (N) 16 0 TO 70 DSCC NUMBER PRODUCT CONTENT SAMPLES ACTIVE View Product Content Request Samples ACTIVE View Product Content Request Samples Back to Top PRICING/AVAILABILITY/PKG DEVICE INFORMATION Updated Daily ORDERABLE DEVICE STATUS 59627802004M2A ACTIVE TI INVENTORY STATUS As Of 08:00 AM GMT, 17 Apr 2003 PACKAGE TYPE | PINS LCCC (FK) | TEMP (C) 20 -55 TO 125 DSCC NUMBER PRODUCT CONTENT View Contents BUDGETARY PRICING QTY | $US 1KU | 12.37 STD PACK QTY IN STOCK 1 1426* IN PROGRESS QTY | DATE LEAD TIME 7 WKS REPORTED DISTRIBUTOR INVENTORY As Of 08:00 AM GMT, 17 Apr 2003 DISTRIBUTOR COMPANY | REGION Avnet | Americas Avnet-SILICA | Europe 59627802004MEA ACTIVE CDIP (J) | 16 -55 TO 125 View Contents 1KU | 5.01 1 188* 312 | 27 May 7 WKS 59627802004MFA ACTIVE CFP (W) | 16 -55 TO 125 View Contents 1KU | 10.01 1 0* 450 | 27 May 7 WKS AM26LS33ACD AM26LS33ACDR ACTIVE ACTIVE SOIC (D) SOIC (D) | | 16 16 0 TO 70 0 TO 70 View Contents View Contents 1KU 1KU | 0.50 | 0.50 40 2500 1839* 7500* >10k | 13 May 410 | 28 Apr 4 WKS 2 WKS >10k | 13 May AM26LS33ACN ACTIVE PDIP (N) | 16 0 TO 70 View Contents 1KU | 0.50 25 0* 6482 | 30 Apr >10k | 10 Jun file:///G|/imaging/BITTING/CPL/20030422/04212003_9/TXII/042120003_HTML/am26ls33a.html (2 of 3) [22-Apr-03 12:27:44 PM] 4 WKS IN STOCK 520 16 None Reported View Distributors Avnet | Americas 433 EBV | Europe Electronik 13 EBV | Europe Electronik >1k Avnet | Americas >1k Insight | Americas >1k Arrow | Americas >1k DigiKey | Americas 340 Arrow | Americas >1k DigiKey | Americas >1k EBV | Europe Electronik Avnet | Americas >1k >1k Arrow | Americas >1k DigiKey | Americas >1k PURCHASE Product Folder: AM26LS33A, Quadruple Differential Line Receiver AM26LS33AMFKB ACTIVE LCCC (FK) | 20 -55 TO 125 5962View Contents 7802004M2A 1KU | 12.37 1 138* AM26LS33AMJ ACTIVE CDIP (J) | 16 -55 TO 125 View Contents 1KU | 4.29 1 99* ACTIVE CDIP (J) 16 5962View Contents -55 TO 125 7802004MEA ACTIVE CFP (W) 16 5962View Contents -55 TO 125 7802004MFA AM26LS33AMJB | 1KU | 5.01 1 7 WKS 901 | 27 May 80* 7 WKS 7 WKS Insight | Americas 575 Newark | Americas Electronics 188 None Reported View Distributors Avnet | Americas Avnet-SILICA | Europe 24 EBV | Europe Electronik 25 Avnet-SILICA | Europe AM26LS33AMWB | 1KU | 10.01 1 46* Table Data Updated on: 4/17/2003 Products | Applications | Support | my.TI (c) Copyright 1995-2002 Texas Instruments Incorporated. All rights reserved. Trademarks | Privacy Policy | Terms of Use file:///G|/imaging/BITTING/CPL/20030422/04212003_9/TXII/042120003_HTML/am26ls33a.html (3 of 3) [22-Apr-03 12:27:44 PM] 7 WKS 373 None Reported View Distributors 4