FUNCTIONAL BLOCK DIAGRAMS
REV. A
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a
+3 V, Voltage Monitoring
␮P Supervisory Circuits
FEATURES
Precision Supply-Voltage Monitor
+2.63 V (ADM706P/R, ADM708R)
+2.93 V (ADM706S, ADM708S)
+3.08 V (ADM706T, ADM708T)
100 ␮A Quiescent Current
200 ms Reset Pulsewidth
Debounced Manual Reset Input (MR)
Independent Watchdog Timer—1.6 sec Timeout
(ADM706x)
Reset Output
Active High (ADM706P)
Active Low (ADM706R/S/T)
Both Active High and Active Low (ADM708R/S/T)
Voltage Monitor for Power-Fail or Low Battery Warning
Guaranteed RESET Valid with VCC = 1 V
Superior Upgrade for MAX706P/R/S/T, MAX708R/S/T
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Critical ␮P Monitoring
Automotive Systems
Battery Operated Systems
Portable Instruments
GENERAL DESCRIPTION
The ADM706P/R/S/T and the ADM708R/S/T microprocessor
supervisory circuits are suitable for monitoring either 3 V or 3.3 V
power supplies.
The ADM706P/R/S/T provide the following functions:
1. Power-supply monitoring circuitry which generates a Reset
output during power-up, power-down and brownout condi-
tions. The reset output remains operational with V
CC
as low
as 1 V.
2. Independent watchdog monitoring circuitry which is acti-
vated if the watchdog input has not been toggled within
1.6 seconds.
3. A 1.25 V threshold detector for power fail warning, low bat-
tery detection, or to monitor an additional power supply.
4. An active low debounced manual reset input (MR).
The ADM706R, ADM706S, ADM706T are identical except for
the reset threshold monitor levels which are 2.63 V, 2.93 V, and
3.08 V respectively. The ADM706P is identical to the ADM706R
in that the reset threshold is 2.63 V. It differs only in that it has
an active high reset output.
ADM706P/R/S/T, ADM708R/S/T
The ADM708R/S/T provide the same functionality as the
ADM706R/S/T and only differ in that:
1. A watchdog timer function is not available.
2. An active high reset output (RESET) in addition to the
active low (RESET) output is available.
All parts are available in 8-lead DIP and narrow SOIC packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
1.25V
VREF*
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI) POWER FAIL
OUTPUT (PFO)
WATCHDOG
OUTPUT(WDO)
RESET,
(P = RESET)
*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
ADM706
RESET &
WATCHDOG
TIMEBASE
RESET
GENERATOR
MR
VCC
70mA
VCC
1.25V
VREF*
POWER FAIL
INPUT (PFI) POWER FAIL
OUTPUT (PFO)
RESET
*VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
ADM708
RESET
GENERATOR
MR
VCC
70mA
VCC
RESET
Parameter Min Typ Max Units Test Conditions/Comments
V
CC
Operating Voltage Range 1.0 5.5 V
Supply Current 100 200 µAV
CC
< 3.6 V
150 350 µAV
CC
< 5.5 V
Reset Threshold (V
RST
) 2.55 2.63 2.70 V ADM70_P/R
2.85 2.93 3.00 V ADM70_S
3.00 3.08 3.15 V ADM70_T
Reset Threshold Hysteresis 20 mV
Reset Pulsewidth 160 200 280 ms ADM70_P/R, V
CC
= 3 V
160 200 280 ms ADM70_S/T, V
CC
= 3.3 V
200 ms V
CC
= 5.0 V
RESET Output Voltage ADM70_R/S/T
V
OH
0.8 × V
CC
VV
RST
(max) < V
CC
< 3.6 V, I
SOURCE
= 500 µA
V
OL
0.3 V V
RST
(max) < V
CC
< 3.6 V, I
SINK
= 1.2 mA
V
OH
V
CC
–1.5 V V 4.5 V < V
CC
< 5.5 V, I
SOURCE
= 800 µA
V
OL
0.4 V 4.5 V < V
CC
< 5.5 V, I
SINK
= 3.2 mA
V
OL
0.3 V V
CC
= 1 V, I
SINK
= 100 µA
RESET Output Voltage ADM706P
V
OH
V
CC
–0.6 V V V
RST
(max) < V
CC
< 3.6 V, I
SOURCE
= 215 µA
V
OL
0.3 V V
RST
(max) < V
CC
< 3.6 V, I
SINK
= 1.2 mA
V
OH
V
CC
–1.5 V V 4.5 V < V
CC
< 5.5 V, I
SOURCE
= 800 µA
V
OL
0.4 V 4.5 V < V
CC
< 5.5 V, I
SINK
= 3.2 mA
RESET Output Voltage ADM708_
V
OH
0.8 × V
CC
VV
RST
(max) < V
CC
< 3.6 V, I
SOURCE
= 500 µA
V
OL
0.3 V V
RST
(max) < V
CC
< 3.6 V, I
SINK
= 500 µA
V
OH
V
CC
–1.5 V V 4.5 V < V
CC
< 5.5 V, I
SOURCE
= 800 µA
V
OL
0.4 V 4.5 V < V
CC
< 5.5 V, I
SINK
= 1.2 mA
Watchdog Timeout Period 1.00 1.60 2.25 sec ADM70_P/R; V
CC
= 3 V. ADM70_S/T,
V
CC
= 3.3 V
WDI Pulsewidth V
IL
= 0.4 V, V
IH
= (V
CC
) × (0.8)
100 ns V
RST
(max) < V
CC
< 3.6 V
50 ns 4.5 V < V
CC
< 5.5 V
WDI Input Threshold ADM706_
V
IL
0.6 V V
RST
(max) < V
CC
< 3.6 V
V
IH
0.7 × V
CC
VV
RST
(max) < V
CC
< 3.6 V
V
IL
0.8 V V
CC
= 5.0 V
V
IH
3.5 V V
CC
= 5.0 V
WDI Input Current –1.0 0.02 1.0 µA WDI = 0 V or V
CC
WDO Output Voltage
V
OH
0.8 × V
CC
VV
RST
(max) < V
CC
< 3.6 V, I
SOURCE
= 500 µA
V
OL
0.3 V V
RST
(max) < V
CC
< 3.6 V, I
SINK
= 500 µA
V
OH
V
CC
–1.5 V V 4.5 V < V
CC
< 5.5 V, I
SOURCE
= 800 µA
V
OL
0.4 V 4.5 V < V
CC
< 5.5 V, I
SINK
= 1.2 mA
MR Pull Up Current MR = 0 V
25 70 250 µAV
RST
(max) < V
CC
< 3.6 V
100 250 600 µA 4.5 V < V
CC
< 5.5 V
MR Pulsewidth
500 ns V
RST
(max) < V
CC
< 3.6 V
150 ns 4.5 V < V
CC
< 5.5 V
MR Input Threshold
V
IL
0.6 V V
RST
(max) < V
CC
< 3.6 V
V
IH
0.7 × V
CC
VV
RST
(max) < V
CC
< 3.6 V
V
IL
0.8 V 4.5 V < V
CC
< 5.5 V
V
IH
2.0 V 4.5 V < V
CC
< 5.5 V
ADM706P/R/S/T, ADM708R/S/T–SPECIFICATIONS
REV. A–2–
(VCC = 2.70 V to 5.5 V (ADM70_P/R),
VCC = 3.00 V to 5.5 V (ADM70_S), VCC = 3.15 V to 5.5 V (ADM70_T), TA = TMIN to TMAX unless otherwise noted.)
ORDERING GUIDE
Temperature Package
Model Range Options
ADM706PAN –40°C to +85°C N-8
ADM706PAR –40°C to +85°C SO-8
ADM706RAN –40°C to +85°C N-8
ADM706RAR –40°C to +85°C SO-8
ADM706SAN –40°C to +85°C N-8
ADM706SAR –40°C to +85°C SO-8
ADM706TAN –40°C to +85°C N-8
ADM706TAR –40°C to +85°C SO-8
ADM708RAN –40°C to +85°C N-8
ADM708RAR –40°C to +85°C SO-8
ADM708SAN –40°C to +85°C N-8
ADM708SAR –40°C to +85°C SO-8
ADM708TAN –40°C to +85°C N-8
ADM708TAR –40°C to +85°C SO-8
Parameter Min Typ Max Units Test Conditions/Comments
MR to Reset Output Delay 750 ns V
RST
(max) < V
CC
< 3.6 V
250 ns 4.5 V < V
CC
< 5.5 V
PFI Input Threshold 1.2 1.25 1.3 V ADM70_P/R; V
CC
= 3 V. ADM70_S/T,
V
CC
= 3.3 V, PFI falling
PFI Input Current –25 0.01 25 nA
PFO Output Voltage
V
OH
0.8 × V
CC
VV
RST
(max) < V
CC
< 3.6 V, I
SOURCE
= 500 µA
V
OL
0.3 V V
RST
(max) < V
CC
< 3.6 V, I
SINK
= 1.2 mA
V
OH
V
CC
–1.5 V V 4.5 V < V
CC
< 5.5 V, I
SOURCE
= 800 µA
V
OL
0.4 V 4.5 V < V
CC
< 5.5 V, I
SINK
= 3.2 mA
ADM706P/R/S/T, ADM708R/S/T
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V
CC
+ 0.3 V
Input Current
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 727 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . . 470 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>5 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods of time may affect device reliability.
REV. A –3–
REV. A–4–
ADM706P/R/S/T, ADM708R/S/T
PIN FUNCTION DESCRIPTIONS
Pin No. Pin No.
Mnemonic ADM706 ADM708 Function
MR 1 1 Manual Reset Input. When taken below 0.6 V a RESET is generated. MR can be
driven from TTL, CMOS logic or from a manual reset switch as it is internally
debounced. An internal 70 µA pull-up current holds the input high when floating.
V
CC
2 2 Power Supply Input.
GND 3 3 0 V. Ground reference for all signals.
PFI 4 4 Power Fail Input. PFI is the noninverting input to the Power Fail Comparator.
When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected
to GND.
PFO 5 5 Power Fail Output. PFO is the output from the Power Fail Comparator. It goes
low when PFI is less than 1.25 V.
WDI 6 N/A Watchdog Input. WDI is a three level input. If WDI remains either high or low
for longer than the watchdog timeout period, the watchdog output WDO goes
low. The timer resets with each transition at the WDI input. Either a high-to-low
or a low-to-high transition will clear the counter. The internal timer is also
cleared whenever reset is asserted. The Watchdog Timer is disabled when WDI is
left floating or connected to a three-state buffer.
NC N/A 6 No Connect.
RESET 7 (R/S/T Only) 7 Logic Output. RESET goes low for 200 ms when triggered. It can be triggered
either by V
CC
being below the reset threshold or by a low signal on the manual
reset (MR) input. RESET will remain low whenever V
CC
is below the reset
threshold. It remains low for 200 ms after V
CC
goes above the reset threshold or
MR goes from low to high. A watchdog timeout will not trigger RESET unless
WDO is connected to MR.
RESET 7 (P Only) 8 Logic Output. RESET is an active high output suitable for systems which use
active high RESET logic. It is the inverse of RESET.
WDO 8 N/A Logic Output. The Watchdog Output, WDO, goes low if the internal watchdog
timer times out as a result of inactivity on the WDI input. It remains low until
the watchdog timer is cleared. WDO also goes low during low line conditions.
Whenever V
CC
is below the reset threshold, WDO remains low. As soon as V
CC
goes above the reset threshold, WDO goes high immediately.
PIN CONFIGURATIONS
MR
VCC
GND
PFI
WDO
RESET
WDI
PFO
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
ADM706
P
MR
VCC
GND
PFI
NC = NO CONNECT
RESET
RESET
NC
PFO
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
ADM708
R/S/T
MR
VCC
GND
PFI
WDO
RESET
WDI
PFO
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
ADM706
R/S/T
REV. A –5–
ADM706P/R/S/T, ADM708R/S/T
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
1.25V
VREF*
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI) POWER FAIL
OUTPUT (PFO)
WATCHDOG
OUTPUT(WDO)
RESET,
(P = RESET)
*VOLTAGE REFERENCE = 2.63V
(
P/R
)
, 2.93V
(
S
)
, 3.08V
(
T
)
ADM706
RESET &
WATCHDOG
TIMEBASE
RESET
GENERATOR
MR
VCC
70mA
VCC
Figure 1. ADM706 Functional Block Diagram
1.25V
VREF*
POWER FAIL
INPUT (PFI) POWER FAIL
OUTPUT (PFO)
RESET
*VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
ADM708
RESET
GENERATOR
MR
VCC
70mA
VCC
RESET
Figure 2. ADM708 Functional Block Diagram
CIRCUIT INFORMATION
Power Fail Reset
The reset output provides a reset (RESET or RESET) output
signal to the Microprocessor whenever the V
CC
input is below
the reset threshold. The actual reset threshold voltage is depen-
dent on whether a P/R, S, or T suffix device is used. An internal
timer holds the reset output active for 200 ms after the voltage
on V
CC
rises above the threshold. This is intended as a power-on
reset signal for the microprocessor. It allows time for both the
power supply and the microprocessor to stabilize after power-
up. If a power supply brownout or interruption occurs, the reset
line is similarly activated and remains active for 200 ms after the
supply recovers. If another interruption occurs during an active
reset period, then the reset timeout period continues for an ad-
ditional 200 ms.
The reset output is guaranteed to remain valid with V
CC
as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.
The ADM706P provides an active high reset (RESET) signal;
the ADM706R/S/T provides an active low (RESET) signal;
while the ADM708R/S/T provides both RESET and RESET.
Manual Reset
The manual reset input (MR) allows other reset sources such as
a manual reset switch to generate a processor reset. The input is
effectively debounced by the timeout period (200 ms typical).
The MR input is TTL/CMOS compatible so it may also be
driven by any logic reset output. If unused, the MR input may
be tied high or left floating.
VCC
RESET
MR
WDO
VRT VRT
tRS tRS
MR EXTERNALLY
DRIVEN LOW
NOTE: RESET = COMPLEMENT OF RESET
Figure 3.
RESET
,
MR
and
WDO
Timing
Watchdog Timer (ADM706)
The watchdog timer circuit may be used to monitor the activity
of the microprocessor in order to check that it is not stalled in
an indefinite loop. An output line on the processor is used to
toggle the Watchdog Input (WDI) line. If this line is not toggled
within the timeout period (1.6 sec), the watchdog output
(WDO) is driven low. The WDO output may be connected to a
nonmaskable interrupt (NMI) on the processor. Therefore, if
the watchdog timer times out, an interrupt is generated. The in-
terrupt service routine should then be used to rectify the
problem.
The watchdog timer is cleared by either a high-to-low or by a
low-to-high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/RESET going
active. Therefore the watchdog timeout period begins after reset
goes inactive.
When V
CC
falls below the reset threshold, WDO is forced low
whether or not the watchdog timer has timed out. Normally
this would generate an interrupt but it is overridden by RESET/
RESET going active.
The watchdog monitor can be deactivated by floating the
Watchdog Input (WDI). The WDO output can now be used as
a low line output since it will only go low when V
CC
falls below
the reset threshold.
tWP tWD
WDI
WDO
RESET
tRS
RESET EXTERNALLY
TRIGGERED BY MR
tWD tWD
Figure 4. Watchdog Timing
REV. A–6–
ADM706P/R/S/T, ADM708R/S/T
VMID 1. 2 5 R1+R2
R2
Valid RESET Below 1 V V
CC
The ADM70x family of products are guaranteed to provide a
valid reset level with V
CC
as low as 1 V. Please refer to the Typi-
cal Performance Characteristics. As V
CC
drops below 1 V, the
internal transistor will not have sufficient drive to hold it ON so
the voltage on RESET will no longer be held at 0 V. A pull-
down resistor as shown in Figure 7 may be connected externally
to hold the line low if it is required.
ADM70x
GND
RESET
R1
Figure 7.
RESET
Valid Below 1 V
Power-Fail Comparator
The power-fail comparator is an independent comparator which
may be used to monitor the input power supply. The compara-
tor’s inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.
This input may be used to monitor the input power supply via a
resistive divider network. When the voltage on the PFI input drops
below 1.25 V, the comparator output (PFO) goes low indicating
a power failure. For early warning of power failure the compara-
tor may be used to monitor the preregulator input simply by
choosing an appropriate resistive divider network. The PFO output
can be used to interrupt the processor so that a shutdown proce-
dure is implemented before the power is lost.
INPUT
POWER R1
R2
POWER-FAIL
INPUT
1.25V
PFI
PFO
ADM70x
POWER-FAIL
OUTPUT
Figure 5. Power-Fail Comparator
Adding Hysteresis to the Power-Fail Comparator
For increased noise immunity, hysteresis may be added to the
power-fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor
between the PFO output and the PFI input as shown in Figure
6. When PFO is low, resistor R3 sinks current from the sum-
ming junction at the PFI pin. When PFO is high, resistor R3
sources current into the PFI summing junction. This results in
differing trip levels for the comparator. Further noise immunity
may be achieved by connecting a capacitor between PFI and GND.
INPUT
POWER
R1
R2
1.25V
PFI
PFO TO mP NMI
ADM70x
R3
ADM663A +3.3V
VCC
3.3V
PFO
0V 0V VLVIN
VH
Figure 6. Adding Hysteresis to the Power-Fail
Comparator
VH=1.25 1 +R2+R3
R2×R3
R1
VL=1. 2 5 +R11. 2 5
R2
–VCC –1.25
R3
V
CC
RESET
400ms/DIV
Figure 8. ADM706/ADM708
RESET
Output Voltage vs.
Supply Voltage
VCC
RESET
400ms/DIV
Figure 9. RESET Output Voltage vs. Supply Voltage
Typical Performance Characteristics
REV. A –7–
ADM706P/R/S/T, ADM708R/S/T
+1.2V
0V
+3V
1.3V
PFI
PFO
500ns/DIV
VCC = +5V
TA = +258C
Figure 10. PFI Assertion Response Time
+1.3V
+3V
0V
1.2V
PFO
PFI
500ns/DIV
VCC = +5V
TA = +258C
Figure 11. PFI Deassertion Response Time
0V0V
100ns/DIV
VCC = VRT
TA = +258C
RESET +3V
RESET
+3V
Figure 12.
RESET
, RESET Assertion
APPLICATIONS
A typical operating Circuit is shown in Figure 15. The unregu-
lated dc input supply is monitored using the PFI input via the
resistive divider network. Resistors R1 and R2 should be selected
such that when the supply voltage drops below the desired level
(e.g., 5 V) the voltage on PFI drops below the 1.25 V threshold
thereby generating an interrupt to the µP. Monitoring the
preregulator input gives additional time to execute an orderly
shutdown procedure before power is lost.
ADM706
RESET
GND
mP
MR
PFI
WDI
PFO
RESET
VCC
+3.3V
WDO
VCC
UNREGULATED
DC
I/O LINE
INTERRUPT
NMI
MANUAL
RESET
GND
GND
IN OUT
ADM666A
Figure 15. Typical Application Circuit
+3V
0V
0V
+3V
100ns/DIV
VCC = VRT
TA = +258C
RESET RESET
Figure 13.
RESET
, RESET Deassertion
+2V
0V
VCC
RESET
2ms/DIV
TA = +258C
+3V
+3V
Figure 14. ADM706/ADM708
RESET
Response Time
REV. A–8–
ADM706P/R/S/T, ADM708R/S/T
Microprocessor activity is monitored using the WDI input. This
is driven using an output line from the processor. The software
routines should toggle this line at least once every 1.6 seconds.
If a problem occurs and this line is not toggled, then WDO goes
low and a nonmaskable interrupt is generated. This interrupt
routine may be used to clear the problem.
If, in the event of inactivity on the WDI line, a system reset is
required, then the WDO output should be connected to the
input as shown in Figure 16.
ADM706
RESET
GND
I/O LINE
mP
MR
PFI WDI
WDO
RESET
Figure 16.
RESET
from WDO
Monitoring Additional Supply Levels
It is possible to use the power-fail comparator to monitor a
second supply as shown in Figure 17. The two sensing resistors
R1 and R2 are selected such that the voltage on PFI drops below
1.25 V at the minimum acceptable input supply. The PFO output
may be connected to the MR input so that a RESET is gener-
ated when the supply drops out of tolerance. In this case if
either supply drops out of tolerance, a RESET will be generated.
Figure 17. Monitoring 3 V/3.3 V and an Additional
Supply, V
X
␮Ps with Bidirectional RESET
In order to prevent contention for microprocessors with a bidi-
rectional reset line, a current limiting resistor should be inserted
between the ADM70x RESET output pin and the µP reset pin.
This will limit the current to a safe level if there are conflicting
output reset levels. A suitable resistor value is 4.7 kΩ. If the re-
set output is required for other uses, then it should be buffered
as shown in Figure 18.
ADM70x
RESET
GND
mP
RESET
GND
BUFFERED
RESET
+3V/+3.3V
VCC
Figure 18. Bidirectional I-O RESET
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
8-Lead Plastic DIP
(N-8)
PRINTED IN U.S.A. C1998a–0–12/99
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
8
14
5
PIN 1
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
0.430 (10.92)
0.348 (8.84)
0. 195 (4. 95)
0. 115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
88
08
0.0196 (0.50)
0.0099 (0.25) 3 458
85
41
0. 1968 (5.00)
0. 1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC 0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10) 0.0192 (0.49)
0.0138 (0.35)