1/22
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© 2011 ROHM Co., Ltd. All rights reserved.
Memory for Plug & Play
EDID Memory
(For display)
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV
Description
BR24C21F,BR24C21FJ,BR24C21FV are serial EEPROMs that support DDC1TM/DDC2TM interfaces
for Plug and Play displays.
Features
1) Compatible with both DDC1TM/DDC2TM
2) Operating voltage range: 2.5V to 5.5V
3) Page write function: 8bytes
4) Low power consumption
Active (at 5V) : 1.5mA (typ)
Stand-by (at 5V) : 0.1µA (typ)
5) Address auto increment function during Read operation
6) Data security
Write enable feature (VCLK)
Write protection at low Vcc
7) Various packages available: DIP-T8(BR24C21) / SOP8(BR24C21F) / SOP-J8(BR24C21FJ) / SSOP-B8(BR24C21FV)
8) Initial data=FFh
9) Data retention: 10years
10) Rewriting possible up to 100,000 times
Absolute maximum ratings (Ta=25)
Parameter Symbol Rating Unit
Supply Voltage VCC -0.3+6.5 V
Power Dissipation Pd
800 (DIP-T8) *1
mW
450 (SOP8) *2
450 (SOP-J8) *3
350 (SSOP-B8) *4
Storage Temperature Tstg -65 +125
Operating Temperature Topr -40+85
Terminal Voltage - -0.3VCC+0.3 V
* Reduce by 8.0 mW/C over 25C (*1), 4.5mW/ (*2,3), and 3.5mW/ (*4)
Memory cell characteristics
Parameter Symbol Rating Unit
Supply Voltage VCC 2.55.5 V
Input Voltage VIN 0VCC V
Recommended operating conditions
Parameter Limits Unit
Min. Typ. Max.
Write/Erase Cycle 100,000 - - Cycle
Data Retention 10 - - Year
No.11002ECT02
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
2/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
Electrical characteristics - DC (Unless otherwise specified, Ta=-40℃~+85℃、VCC=2.5V5.5V)
Parameter Symbol Limits Unit Condition
Min. Typ. Max.
“H” Input Voltage 1 VIH1 0.7VCC - - V SCL, SDA
“L” Input Voltage 1 VIL1 - - 0.3VCC V SCL, SDA
“H” Input Voltage 2 VIH2 2.0 - - V VCLK
“L” Input Voltage 2 VIL2 - - 0.8 V VCLK, VCC4.0V
“L” Input Voltage 3 VIL3 - - 0.2VCC V VCLK, VCC4.0V
“L” Output Voltage VOL - - 0.4 V SDA, IOL=3.0mA
Input Leakage Current ILI -1 - 1 µA SCL, VCLK, VIN=0VVCC
Output Leakage Current ILO -1 - 1 µA SDA, VOUT=0VVCC
Operating Current ICC - - 3.0 mA VCC=5.5V, fSCL=400kHz
Standby Current ISB - 10 100 µA VCC=5.5V, SDA=SCL=VCC,VCLK=GND *1
Note: This IC is not designed to be radiation-resistant
*1 Transmit-Only Mode - After power on, the BR24C21/F/FJ/FV is in Standby mode and does not provide the clock to the VCLK pin.
After the clock is provided to VCLK, the device is switched from Standby to Transmit-Only Mode, and the operating current flows.
Bi-directional Mode - The BR24C21/F/FJ/FV is in Standby mode after each command is performed.
Electrical characteristics - AC (Unless otherwise specified, Ta=-40℃~+85,VCC=2.5V5.5V)
Parameter Symbol
Fast-mode
VCC=2.5V5.5V
Standard-mode
VCC=2.5V5.5V Unit
Min. Typ. Max. Min. Typ. Max.
Clock Frequency fSCL - - 400 - - 100 kHz
Data Clock High Period tHIGH 0.6 - - 4.0 - - µs
Data Clock Low Period tLOW 1.3 - - 4.7 - - µs
SDA and SCL Rise Time tR - - 0.3 - - 1.0 µs
SDA and SCL Fall Time tF - - 0.3 - - 0.3 µs
Start Condition Hold Time tHD:STA 0.6 - - 4.0 - - µs
Start Condition Setup Time tSU:STA 0.6 - - 4.7 - - µs
Input Data Hold Time tHD:DAT 0 - - 0 - - ns
Input Data Setup Time tSU:DAT 100 - - 250 - - ns
Output Data Delay Time(SCL) tPD - - 0.9 - - 3.5 µs
Stop Condition Setup Time tSU:STO 0.6 - - 4.0 - - µs
Bus Free Time tBUF 1.3 - - 4.7 - - µs
Write Cycle Time tWR - - 10 - - 10 ms
Noise Spike Width (SDA and SCL) tI - - 0.1 - - 0.1 µs
AC OPERATING CHARACTERISTICS (Transmit-Only Mode)
Output Data Delay Time(VCLK) tVPD - - 1.0 - - 2.0 µs
VCLK High Period tVHIGH 0.6 - - 4.0 - - µs
VCLK Low Period tVLOW 1.3 - - 4.7 - - µs
VCLK Setup Time tVSU 0 - - 0 - - µs
VCLK Hold Time tVHD 0.6 - - 4.0 - - µs
Mode Transition Time tVHZ - - 0.5 - - 1.0 µs
Transmit-Only Powerup Time tVPU 0 - - 0 - - µs
Noise Spike Width (VCLK) tVI - - 0.1 - - 0.1 µs
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
3/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
Block diagram
Pin layout diagram
Fig.2 Pin Layout
Pin Name I/O Functions
VCC - Power Supply
GND - Ground (0V)
N.C. - No Connection
SCL IN Serial Clock Input for Bi-directional Mode
SDA IN/OUT
Slave and Word Address,
Serial Data Input, Serial Data Output *1
VCLK IN
Clock Input (Transmit-Only Mode)
Write Enable (Bi-directional Mode)
*1 An open drain output requires a pull-up resistor.
8
7
6
5 4
3
2
1
SDA
SCL
VCLK
VCC
GND
N.C. 1 Kbit EEPROM ARRAY
ADDRESS
DECODER
SLAVEWORD
ADDRESS REGISTER
DATA
REGISTER
CONTROL LOGIC
HIGH VOLTAGE VCC LEVEL DETECT
7bit
7bit
8bit
ACK
START STOP
N.C.
N.C.
Fig.1 Block Diagram
VCC VCLK
(入力)
SCL SDA
入出
BR24C21
BR24C21F
BR24C21FJ
BR24C21FV
GND N.C. N.C.
N.C.
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
4/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
Synchronous data timing
Transmit-only mode
After power is on, the BR24C21/F/FJ/FV is in Transmit-Only Mode. In this mode data can be output by providing the clock
to the VCLK pin.
When the power is on, the SCL pin needs to be set to VCC(High level).
SDA is at high-impedance during input of the first 9 clocks. At the 10th rising clock edge of VCLK data is output. After
power on, the output data is as follows:
00h address data 01h address data 02h address data
The address is incremented by one, after every 9 clocks of VCLK. All addresses are output in this mode.
When the counter reaches the last address, the next output data is 00h address data. (See Fig. 6)
In this mode, the NULL bit (High data) is output between the address data and the next address data. (See Fig. 7)
The read operation is in Transmit-Only Mode and can be started after the power is stabilized.
SD
A
SCL
D0 ACK
STOP CONDITION START CONDITION
tWR
WRITE DATA(n)
Fig.4 Write Cycle Timing
tVHD
SCL
tVSU WRITE COMMAND
START BIT STOP BIT
VCLK
SDA
Fig.5 Write Enable Timing
SDA
(IN)
SCL
SDA
(OUT)
tHD:STA tHD:DAT
tSU:DAT
tBUF t
PD
tLOW
tHIGH tR t
F
Fig.3 Synchronous Data Timing
SDA
SCL
tSU:STA tSU:STO
tHD:STA
START BIT STOP BIT
SDA data is latched into the chip at the rising edge of the SCL clock.
Output data toggles at the falling edge of the SCL clock.
Fig.6 Transmit Only Mode Fig.7 Null Bit
101
tVPU
D7 D6 D5 D4 D3
VCLK
SCL
SDA
Vcc
00h ADDRESS DATA
9
SDA
VCLK
NULL BIT
DATA=1
D0D1 D7 D6
ADDRESS n
DATA
ADDRESS n+1
DATA
tVPD
tVHIGH tVLOW
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
5/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
Bi-directional mode
Bi-directional Mode and Recovery Function
The BR24C21/F/FJ/FV can be switched from Transmit-Only Mode to Bi-directional Mode by providing a valid High to Low
transition at the SCL pin, while the state of SDA is at high-impedance.
After a valid high to low transition on the SCL pin, the BR24C21/F/FJ/FV begins to count the VCLK clock. If the VCLK
counter reaches 128 clocks without the command for Bi-directional Mode, the device reverts to Transmit-Only Mode
(Recovery function). The VCLK counter is reset by providing a valid high to low transition at the SCL pin. After reversal
to Transmit-Only Mode the device begins to output data (00h address data) with the 129th rising clock edge of VCLK.
If the BR24C21/F/FJ/FV is switched from Transmit-Only Mode and receives the command for Bi-directional
Mode and responds with an Acknowledge, it is impossible to revert to Transmit-Only Mode. (Power down is the only
way to revert to Transmit-Only Mode.) Unless the input device code is “1010”, the device does not respond with an
Acknowledge. If the VCLK counter reaches 128 clocks afterwards, it is possible to revert to Transmit-Only Mode for
Recovery function. If the Master generates a STOP condition during the Slave address, before an Acknowledge is input,
it is possible to revert to Transmit-Only Mode.
When the device is switched from Transmit-Only Mode to Bi-direction Mode, the period of tVHZ needs to be held.
Bi-directional Mode
START Condition
All commands are proceeded by the START condition, which is a High to Low transition of SDA when SCL is High.
The BR24C21/F/FJ/FV continuously monitors the SDA and SCL lines for the START condition and will not respond to
any commands until this condition has been met.
(See Fig. 3 Synchronous Data Timing)
STOP Condition
All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is High.
The STOP condition causes the internal write cycle to write data into the memory array after a write sequence.
The STOP condition is also used to place the device into standby power mode after read sequences.
A STOP condition can only be issued after the transmitting device has released the bus.
(See Fig.3 Synchronous Data Timing)
Device Addressing
Following the START condition, the Master outputs the device address of the Slave to be accessed. The most
significant four bits of Slave address are the “device type indentifier,” For the BR24C21/F/FJ/FV this is fixed as
“1010.”
The next three bits of the slave address are inconsequential.
The last bit of the stream determines the operation to be performed. When set to “1”, a READ operation is selected.
When set to “0”, a WRITE operation is initiated.
R/W set to "0" WRITE (This bit is also set to "0" for random read operation)
R/W set to "1" READ
1010
_
R/W
*:Don’t care
Write Protect Function
Write Enable (VCLK)
When using the BR24C21/F/FJ/FV in Bi-directional Mode, the VCLK pin can be used as a write enable pin. Setting
VCLK High allows normal write operations, while setting VCLK low prevents writing to any location in the array.
(See Fig.5 Write Enable Timing)
Changing VCLK from High to Low during the self-timed program operation will not halt programming of the device.
Fig.8 Recovery Mode
Bi-directional
Transition Mode with possibility to
return to Transmit-Only Mode
Transmit-only Transmit-Only
ADDRESS 00h
6D5D
Transmit-only
ADDRESS 00h
Transmit-Only
Bi-directional
Transition Mode with possibility
to retune to Transmit-Only Mode
Fig.9 Mode Change
1n
Transmit-oOnly
10 ***R/W
Bi-directional
Transition Mode with possibility to
return to Transmit-Only Mode
Bi-directional
parmanently
Transmit-only Bi-directional
Transition Mode with possibility
to retune to Transmit-Only Mode
Bi-directional
parmanently
*Don’t care
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
6/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
Bidirectional mode command
Byte Write
When the Master generates a STOP condition, the BR24C21/F/FJ/FV begins the internal write cycle to the nonvolatile array.
Fig.10 Byte Write Cycle Timing
Page Write
If the Master transmits the next data instead of generating a STOP condition during the byte write cycle, the
BR24C21/F/FJ/FV transfers from byte write function to page write function. After receipt of each word, the three lower
order address bits are internally incremented by one, while the high order four bits of the word address remains
constant.
If the master transmits more than eight words, prior to generating the STOP condition, the address counter will “roll
over,” and the previous transmitted data will be overwritten.
Fig.11 Page Write Cycle Timing
Current Read
The BR24C21/F/FJ/FV contains an internal address counter which maintains the address of the last word accessed,
incremented by one. If the last accessed address is address “n” in a Read operation, the next Read operation will
access data from address “n+1” and increment the current address counter. If the last accessed address is address
”n” in a Write operation, the next Read operation will access data from address “n”. If the Master does not transfer an
Acknowledge, but does generate a STOP condition, the current address read operation will only provide a single byte of
data. At this point, the device discontinues transmission.
(See Fig.14 Sequential Read Cycle Timing)
Fig.12 Current Read Cycle Timing
* * WA
6 D7 1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS DATA
VCLK
S
DA
LINE
SLAV
E
ADDRESS
* WA
0 D0
A
C
K
A
C
K
*
*:Don’t care
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS
DATA
n
VCLK
SDA
LINE
A
C
K
A
C
K
*:Don’t care
A
C
K
SLAV
E
ADDRESS
10 0
1
WA
6 D0 D7 D0
WA
0
*
DATA(n+7
)
D7 1 1 0 0
R
E
A
D
S
T
A
R
T
R
/
W
S
T
O
P
DATA
SDA
LINE
SLAVE
ADRESS
D0
A
C
K
A
C
K
*:Don
t
care
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
7/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
Random Read
The Random read operation allows the Master to access any memory location. This operation involves a two-step
process. First, the Master issues a Write command that includes the START condition and the Slave address field
(with R/W set to “0”) followed by the word address of the word to be read. This procedure sets the internal address
counter of the BR24C21/F/FJ/FV to the desired address. After the word address Acknowledge is received by the
Master, the Master immediately re-issues a START condition followed by the Slave address field with R/W set to “1.”
The device will respond with an Acknowledge and then transmit the 8-data bits stored at the addressed location. If the
Master does not acknowledge the transmission but does generate the STOP condition, the IC will discontinue
transmission.
Fig.13 Random Read Cycle Timing
Sequential Read
If the Master does not transfer an Acknowledge and does not generate a STOP condition during the current Read
operation, the BR24C21/F/FJ/FV continues to output the next address data in sequence. For Read operations, all bits
in the address counter are incremented, allowing the entire array to be read during a single operation. When the
counter reaches the top of the array, it will “roll over” to the bottom of the array and continue to transmit data.
If the Master does not acknowledge the transmission but does generate a STOP condition, at this point the device
discontinues transmission.
The sequential Read operation can be performed with both Current Read and Random Read.
Fig.14 Sequential Read Cycle Timing
(Current Read)
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0
1* * * WA
6 * D0
SLAVE
ADDRESS
10 01* *
S
T
A
R
T
D7
R
/
W
R
E
A
D
WA
0
*
*:Dont care
R
E
A
D
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
DATA(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+x)
A
C
K
SLAVE
ADDRESS
10 0
1* * * D0 D7 D0 D7
*:Dont care
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
8/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
BU9882-W,BU9882F-W,BU9882FV-W
Description
BU9882F-W,BU9882FV-W are dual port EEPROMs compatible with the DDC2TM. 2 independent ports allow
2 EDID channels to be read simultaneously.
Features
1) Designed for use with DDC2TM
2) 2-port simultaneous read function
3) Operating voltage range: 2.5V-5.5V
4) Page write function: 8bytes
5) Low power consumption:
Active
(at 5V) : 1.5mA(typ)
Stand-by (at 5V) : 0.1µA(typ)
6) Data security
Write protection with WP
Write protection at low power supply voltage
7) Various package types available: DIP14(BU9882-W) / SOP14(BU9882F-W) / SSOP14(BU9882FV-W)
8) Initial data: FFh
9) Data retention: 10years
10) Rewriting possible up to 100,000 times
Absolute maximum ratings
Parameter Symbol Rating Unit
Supply Voltage VCC -0.3+6.5 V
Power Dissipation Pd
950 (DIP14) *1
mW 450 (SOP14) *2
350 (SSOP14) *3
Storage Temperature Tstg -65 +125
Operating
Temperature Topr -40+85
Terminal Voltage - -0.3VCC+1.0 *4 V
* Reduce by 9.5 mW/C over 25C (*1), 4.5mW/(*2), 3.5mW/(*3).
*4 6.8V (Max.)
Recommended operating conditions
Parameter Symbol Rating Unit
Supply Voltage VCC 2.55.5 V
Input Voltage VIN 0VCC+1.0 V
Memory cell characteristics
Parameter Limits Unit
Min. Typ. Max.
Write/Erase Cycle
100,000 - - Cycle
Data Retention 10 - - Year
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
9/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
Electrical characteristics – DC (Unless otherwise specified, Ta=-40℃~+85,VCC=2.5V5.5V)
Parameter Symbol Limits Unit Condition
Min. Typ. Max.
“H” Input Voltage 1 VIH1 2.0 - - V
“L” Input Voltage 1 VIL1 - - 0.8 V VCC4.0V
“L” Input Voltage 2 VIL2 - - 0.2VCC V VCC4.0V
“L” output Voltage VOL1 - - 0.4 V SDA_PC0/1, IOL=3.0mA *
Input Leakage Current 1 ILI1 -1 - 1 µA SCL_PC0/1,DDCENA, BANKSEL,
VIN=0VVCC+1.0
Input Leakage Current 2 ILI2 -1 - 50 µA
___
WP
Output Leakage Current ILO -1 - 1 µA SDA_PC0/1,SCL/SDA_MON(DDCENA=GND),
VOUT=0VVCC+1.0
Operating Current ICC - 1.5 3.0 mA fSCL=400kHz, VCC=5.5V
tWR=10ms
Standby Current ISB - 0.1 5 µA
SCL/SDA_PC0/1=VCC
SCL/SDA_MON=H-Z
DDCENA=WPB=BANKSEL=GND
DUALPCB=VCC
Note: This IC is not designed to be radiation-resistant
*1 IOL at monitor mode (DDCENAHIGH) is the sum of current flowing from the pull up resistor at the SDA_MON side to the pull up resistance
at SDA_PC0/PC1
Electrical characteristics – AC (Unless otherwise specified, Ta=-40℃~+85℃、VCC=2.5V5.5V)
Parameter Symbol
Fast-mode
VCC=2.5V5.5V
Standard-mode
VCC=2.5V5.5V Unit
Typ.
Min. Typ. Max. Min. Typ. Max.
Clock Frequency fSCL - - 400 - - 100 kHz
Data Clock High Period tHIGH 0.6 - - 4.0 - - µs
Data Clock Low Period tLOW 1.3 - - 4.7 - - µs
SDA and SCL Rise Time tR - - 0.3 - - 1.0 µs
SDA and SCL Fall Time tF - - 0.3 - - 0.3 µs
Start Condition Hold Time tHD:STA 0.6 - - 4.0 - - µs
Start Condition Setup Time tSU:STA 0.6 - - 4.7 - - µs
Input Data Hold Time tHD:DAT 0 - - 0 - - ns
Input Data Setup Time tSU:DAT 100 - - 250 - - ns
Output Data Delay Time(SCL) tPD - - 0.9 - - 3.5 µs
Stop Condition Setup Time tSU:STO 0.6 - - 4.0 - - µs
Bus Free Time tBUF 1.3 - - 4.7 - - µs
Write Cycle Time tWR - - 10 - - 10 ms
Noise Spike Width (SDA and SCL) tI - - 0.1 - - 0.1 µs
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
10/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
Fig.15 Block Diagram
Fig.16 Pin Layout
Block diagram
Pin layout diagram
Pin description
Pin Name I/O Functions
VCC - Power Supply
GND - Ground (0V)
N.C. - No Connection
SCL_PC0 IN
Serial Clock Input, Access to BANK0 at DUAL PORT mode
Access to BANK0 or to BANK1 at SINGLE PORT mode
SDA_PC0 IN/OUT
Slave and Word Address Serial Data Input, Serial Data Output
Access to BANK0 at DUAL PORT mode, Access to BANK0 or to BANK1 at SINGLE PORT mode
SCL_PC1 IN
Serial Clock Input
Access to BANK1 at DUAL PORT mode, Don't Care at SINGLE PORT mode
SDA_PC1 IN/OUT
Slave and Word Address Serial Data Input, Serial Data Output
Access to BANK1 at DUAL PORT mode, Don't Care at SINGLE PORT mode
SCL_MON OUT Serial Clock Output
Connected to SCL_PC0/1 at DDCENA="High", "Hi-Z" output at DDCENA="Low"
SDA_MON OUT Slave and Word Address Serial Data Output
Connected to SCL_PC0/1 DDCENA="High", "Hi-Z" output at DDCENA="Low"
DDCENA IN Control of SCL_MON, SDA_MON
BANKSEL IN
Select a SCL/SDA_MON Connected Port at DUAL PORT mode
Selected a BANK at SINGLE PORT mode
DUALPCB IN Control of DUAL PORT/SINGLE PORT mode
wp
―――
IN Write Protect Control
An open drain output requires a pull-up resistor.
BU9882-W
BU9882F-W
BU9882FV-W
SCL
_
PC0 SDA
_
PC0 N.C. SCL
_
PC1 SDA
_
PC1 N.C. GND
VCC WP DUALPCB BANKSEL DDCENA SCL_MON SDA_MON
1Kbit
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
11/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
SDA
SCL
tSU:STA tSU:STO tHD:STA
START BIT STOP BIT
Synchronous data timing
Fig.17 Synchronous Data Timing
SDA data is latched into the chip at the rising edge of the SCL clock.
The output date toggles at the falling edge of the SCL clock.
Write cycle timing
Fig.18 Write Cycle Timing
Operation notes
DDCENA Operation
When DDCENA is set to High, SCL_PC0/1 and SDA_PC0/1 will be connected to SCL_MON and SDA_MON,
respectively. Therefore, monitoring of the communications between the PC and EEPROM, and the communications of
the MONITOR and PC, is possible.
Selection of PC0/PC1 is determined according to the state of the DUALPCB and BANKSEL inputs.
When DDCENA is Low, the SCL/SDA_MON output is set to "Hi-Z".
DUALPCB BANKSEL SCL_MON,SDA_MON
(CONNECTION PORT)
Low (DUAL PORT) Low PC0 PORT
High PC1 PORT
High (SINGLE PORT) Low PC0 PORT
High
BANKSEL
BANKSEL serves as an input for connection port of SCL/SDA_MON during DUAL PORT mode.
It turns into the BANK selection terminal of internal memory in SINGLE PORT mode.
Only the PC0 port can access the memory in SINGLE PORT mode.
DUALPCB BANKSEL CONNECTION BANK
Low (DUAL PORT) Low PC0 PORTBANK0
PC1 PORTBANK1
High
High (SINGL PORT) Low BANK0
High BANK1
WP
When WP=Low, all data at all addresses are write-protected. The terminal has a built-in pull down resister. Make sure
that WP=High when writing data.
Utilize this function in order to prevent incorrect write command input from the PC, as well as incorrect input during
communication between the PC and monitor.
SDA
(IN)
SCL
SDA
(OUT)
tHD:STA tHD:DAT tSU:DAT
tBUF tPD
tLOW
tHIGH
tR t
F
SDA
SCL
D0 ACK
STOP CONDITION START CONDITION
t
WR
WRITE DATA (n)
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
12/22
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Data Read
The data read function allows simultaneous read from SCL_PC0/1, SDA_PC0/1 in DUAL PORT mode.
Data Write
Write operation is performed using either PC0/1 (SCL or SDA) even when accessed simultaneously in DUAL PORT mode.
Port selection is made by detecting the data D0 of the first byte of the WRITE command input.
After this, the other port is made unavailable for both READ and WRITE commands until the write operation is completed.
Fig.19 Write Cycle Timing
START Condition
All commands are preceeded by the START condition, which is a High to Low transition of SDA when SCL is High. This
IC continuously monitors the SDA and SCL lines for the START condition and will not respond to any commands until
this condition has been met.
STOP Condition
All commands must be terminated by a STOP condition, which is a Low to High transition of SDA when SCL is HIGH.
(See Fig.17)
WRITE Command
Unless a STOP condition is executed, the data will not be written into the memory array.
DEVICE ADDRESSING
Following a START condition, the Master outputs the device address of the slave to be accessed.
The most significant four bits of the Slave address are the "device type indentifier".
For the IC this is fixed as "1010".
The next three bits are "000".
The last bit of the stream determines the operation to be performed.
When set to "1", Read operation is selected ; when set to "0", Write operation is selected.
R/W set to "0" WRITE
R/W set to "1" READ
1010 0 0 0 R/W
0 0 WA
6 D7 1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS DATA
SDA_PC
SLA VE
ADDRESS
0 WA
0 D0
A
C
K
A
C
K
*
*:Don’t care
D0 detected first write o peration
performed throug h the port
During other port is write command.
this ack is no output.
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
13/22
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© 2011 ROHM Co., Ltd. All rights reserved.
0 0 WA
6 D71 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS DATA
SDA
LINE
SLAVE
ADDRESS
0WA
0 D0
A
C
K
A
C
K
*
*:Don’t care
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS
()
DATA(n)
SDA
LINE
A
C
K
A
C
K
*:Don’t care
A
C
K
SLAVE
ADDRESS
10 0
10 0
0 WA
6D0D7 D0
WA
0
*
DATA
(
n+7
)
00D71 10 0
R
E
A
D
S
T
A
R
T
R
/
W
S
T
O
P
DATA
SDA
LINE
SLAVE
ADRESS
0D0
A
C
K
A
C
K
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS
()
SDA
LINE
A
C
K
A
C
K
DATA
(
n
)
A
C
K
SLAVE
ADDRESS
10 0
10 0 0 WA
6 0 D0
SLAVE
ADDRESS
10 010 0
S
T
A
R
T
D7
R
/
W
R
E
A
D
WA
0
*
*:Don’t care
Commands
Byte Write
When the Master generates a STOP condition, the IC begins an internal write cycle to the nonvolatile array.
Fig.20 Byte Write Cycle Timing
Page Write
After the receipt of each word, the three low order address bits are internally increased by one. The four higher order
bits of the address(WA6WA3) remain constant. This IC is capable of eight byte page write operation.
If the master transnmits more than eight words, prior to generating the STOP condition, the address counter will "roll
over", and the previous transmitted data will be overwritten.
Fig.21 Page Write Cycle Timing
Current Read
In case the previous operation is random or current read (which includes sequential read), the internal address counter
is increased by one from the last acceseed address (n). Thus current read outputs the data of the next word address
(n+1).
If the last command is byte or page write, the internal address stays at the last address(n). Thus current read outputs
the data of the word address (n).
If the master does not transfer the Acknowledge, but does generate a stop condition, the current address read operation
only provides a single byte of data.
At this point, the BU9882/F/FV-W discontinues transmission.
Fig.22 Current Read Cycle Timing
Random Read
Random read operation allows the master to access any location.If the master does not transfer the Acknowledge but
does generate a stop condition, the current address read operation only provides a single byte of data. (At 1Kbit all
address read possible).This communication must be terminated by a stop condition, which is a Low to High transition of
SDA when SCL is High
Fig.23 Random Read Cycle Timing
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
14/22
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© 2011 ROHM Co., Ltd. All rights reserved.
R
E
A
D
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
DATA
(
n
)
SDA
LINE
A
C
K
A
C
K
DATA
(
n+x
)
A
C
K
SLAVE
ADDRESS
10 0
10 0 0 D0D7 D0 D7
Sequential Read
During the Current read operation, if an Acknowledge is detected, and no STOP condition is generated by the
master(µ-COM), the device will continue to transmit the data. (It can transmit all data(1Kbit 128word)). If an
Acknowledge is not detected, the devive will terminate further data transmissions and await a STOP condition before
returning to the standby mode. The Sequential Read operation can be performed with both Current Read and
Random Read.
Fig.24 Sequential Read Cycle Timing
Peripheral Circuits
DUAL PORT
DUAL PORTs are used to connect two PCs to one monitor. PC0 is connected to BANK0 and PC1 to BANK1. Each bank
operates as 1Kbit EEPROM.
To Use DUAL PORT
Start the operation of the DUAL PORT by following the instructions below:
1. Set the DUAL PCB to LOW with neither of the ports being operated by commands.
2. Input the command from PC0 or PC1.
Simultaneous Access
<READ OPERATION>
EEPROM data read allows simultaneous access from PC0, PC1 ports.
<WRITE OPERATION>
Write operation is performed for either of PC0/1 even when accessed simultaneously from both.
Port selection is made by detecting the data D0 of the first byte of the WRITE command input.
Write operation is performed only for the port where D0 of the first byte of the write data is detected first.
PC 0 MONITOR
CPU
CC
SD
A
SCL
SDA
SCL
PC 1
SCL_PC0
SDA_PC0
NC
SCL_PC1
SDA_PC1
NC
GND
VCC
WPB
DUALPCB
BANKSEL
DDCENA
SCL_MON
SDA_MON
BANK0
(1kbit)
BANK1
(1kbit)
WP
Fig.25 Example of Peripheral Circuit with Dual Port
Fig.26 Simultaneous Access
of Read O
p
eration
SDA-PC0
BUS
1
1
WA0
*WA6
SDA-PC1
BUS
S
T
A
R
T
1
1
SLAVE
ADDRESS
BANK0 WORD
ADDRESS(W)
Write operation performed
Through the port.
R
/
W
D0
D7
S
T
O
P
No ACK
BANK1 WORD
ADDRESS(W)
D0
D7
S
T
O
P
Fig.27 Simultaneous Access
Of Write Operation
Fig.27 Simultaneous Access
of White O
p
eration
*W
A
6W
A
0
*W
A
6W
A
0
*:Don’t care
S
T
A
R
T
1
1
D0
D7
1
1
D0
D7
A
C
K
A
C
K
S
T
O
P
SLAVE
ADDRESS
Output Data from BANK0
SDA-PC0
BUS
SDA-PC1
BUS
R
/
W
Fig.26 SIMULTANEOUS ACCESS
OF READ OPERATION
Output Data from BANK1
1
1
D0
D7
SDA-PC1
BUS
Output Data from BANK1
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
15/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
SDA
SCL
PC 0 MONITOR
CPU
CC
VCC
WP
DUALPCB
BANKSEL
DDCENA
SCL_MON
SDA_MON
BANK0
(1kbit)
BANK1
(1kbit)
SCL_PC0
SDA_PC0
NC
SCL_PC1
SDA_PC1
NC
GND
MONITOR OUTPUT
BU9882F-W, BU9882FV-W has a monitor output terminal. This allows communication between the PC and monitor CPU.
The monitor output for the use of DUAL PORT can be switched with BANKSEL input, as shown in the table below.
SINGLE PORT
SINGLE PORT is for connecting one PC to one monitor. In this case, it is accessible only from PC0. BANK selection is
made with BANKSEL.
Switching this BANKSEL allows access to the total of 2kbit EEPROM, with BANK0 and BANK1, from PC0.
To use SINGLE PORT
Start the SINGLE PORT operation by following the instructions below:
1. Set the DUAL PCB to High with neither of the ports being operated by commands.
2. Select the BANK with BANKSEL.
3. Input the command from PC0.
BANKSEL input SCL_MON,SDA_MON connection port
Low PC0 PORT
High PC1 PORT
Fig.28 Example of Peripheral Circuit with Single Port
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
16/22
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© 2011 ROHM Co., Ltd. All rights reserved.
Common Application Note
Software Reset
Execute software reset in case the device is at an unexpected state after power up and/or the command input needs to be
reset. The following figures (Fig.29-(a), Fig.29-(b), Fig.29-(c))
During dummy clock, please release SDA BUS (tied to Vcc by pull up resistor).
During that time, the device may pull the SDA line Low for acknowledge or outputting read data. If the master controls the
SDA line High, it will conflict with the device output Low then it makes a current overload. It may cause instantaneous
power down and may damage the device.
Acknowledge Polling
Since the device ignores all input commands during the internal write cycle, no ACK will be returned. When the master sends
the next command following the write command, and the device returns the ACK, it means that the program is completed. If
no ACK is returned, it means that the device is still busy. By using Acknowledge polling, the waiting time is minimized to less
than tWR=5ms. To prevent operating Write or Current Read immediately after Write, first send the slave address (R/W is
"High" or "Low"). After the device returns the ACK, continue word address input or data output, respectively.
Fig.29-(c) Start×9
Fig.29-(b) StartDummy Clock×9Start
COMMAND
COMMAND
COMMAND
COMMAND
COMMAND
COMMAND
1 2 13 14
SCL
Dummy Clock×14 Start×2
SCL
SCL
Fig.29-(a) Dummy Clock×14StartStart
12 3 8 9
7
2
18 9
Dummy Clock×9 Start
Start
Start×9
SDA
SDA
SDA
WORD
ADDRESS
S
T
A
R
T
THE FIRST WRITE COMMAND
A
C
K
H
A
C
K
L
SLAVE
ADDRESS
DATA
WRITE COMMAND
tWR
tWR
THE SECOND WRITE COMMAND
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
O
P
S
T
O
P
A
C
K
H
A
C
K
H
A
C
K
L
A
C
K
L
During the internal write cycle,
no ACK will be returned.
(ACK=High)
SLAVE
ADDRESS
SLAVE
ADDRESS
SLAVE
ADDRESS
After the internal write cycle
is completed ACK will be returned
(ACK=Low). Then input next
Word Address and data.
Fig.30 Successive Write Operation By Acknowledge Polling
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
17/22
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© 2011 ROHM Co., Ltd. All rights reserved.
THE CAPACITANCE OF
BUS LINE (CBUS)
Fig.32 I/O Circuits
Command Cancellation By Start And Stop Condition
During a command input, command is canceled by the successive inputs of start condition and stop condition (Fig.31).
However, during ACK or data output, the device may output the SDA line Low. In such cases, operation of start and stop
condition is impossible, making the reset inoperable. Execute the software reset in the cases. (Fig.29)
Operating the command cancel by start and stop condition during the command of Random Read or Sequential Read or
Current Read, internal address counter is not confirmed. Therefore operation of Current Read after this is not valid.
Operate a Random Read in this case.
Fig.31 Command Cancellation
I/O Circuit
SDA Pin Pull-up Resister
The pull up resister is needed because SDA is NMOS open drain. Choose the correct value of this resister(RPU), by
considering VIL, IL characteristics of a controller which control the device and VOH, IOL characteristics of the device. If
large RPU is chosen, clock frequency needs to be slow. In case of small RPU, the operating current increases.
Maximum Rpu
Maximum value of RPU is determined by following factors:
SDA rise time determined by RPU and the capacitance of bus line(CBUS) must be less than tR.
Other timing must keep the conditions of AC spec.
When SDA bus is High, the voltage
A of SDA bus determined by a total input leak(IL) of the all devices connected to
the bus. RPU must be significantly higher than the High level input of a controller and the device, including a noise
margin 0.2VCC.
VCC-ILRPU-0.2 VCC VIH
RPU 0.8Vcc-VIH
IL
Examples: When VCC=3V IL=10µA VIH=0.7VCC
According to
R
PU 0.8x3-0.7x3
10x10-6
300 [k]
SDA PIN
RPU
A
IL IL
MICRO
COMPUTER
SCL
SDA
1 1 0 0
Start
Condition
Stop
Condition
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
18/22
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Minimum RPU
The minimum value of RPU is determined by following factors:
Meets the condition that VOLMAX=0.4V, IOLMAX=3mA when the output is Low.
VOLMAX=0.4V must be lower than the input Low level of the microcontroller and the EEPROM
including the recommended noise margin of 0.1VCC.
VOLMAX
VIL-0.1 VCC
Examples: VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the controller and
According to
867 [Ω]
RPU 3-0.4
3×10 -3
the EEPROM is VIL=0.3VCC,
and VOL=0.4V
VIL=0.3×3
=0.9
V
so that condition is met
SCL Pin Pull-up Resister
When SCL is controlled by the CMOS output the pull-up resistor at SCL is not required.
However, should SCL be set to Hi-Z, connection of a pull-up resistor between SCL and VCC is recommended.
Several k are recommended for the pull-up resistor in order to drive the output port of the microcontroller.
VCC-VOL
RPU IOL
RPU VCC-VOL
IOL
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
19/22
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© 2011 ROHM Co., Ltd. All rights reserved.
Notes For Power Supply
VCC rises through the low voltage region in which the internal circuit of the IC and the controller are unstable. Therefore,
the device may not work properly due to an incomplete reset of the internal circuit. To prevent this, the device has a P.O.R.
and LVCC feature. At power up, maintain the following conditions to ensure functions of P.O.R and LVCC.
1. "SDA='H'" and "SCL='L' or 'H'".
2. Follow the recommended conditions of tR, tOFF, Vbot for the P.O.R. function during power up.
tOFF
tR
Vbot
0
Fig.33 Vcc rising wave from
V
CC
3. Prevent SDA and SCL from being "Hi-Z".
In case conditions 1 and/or 2 cannot be met, take following actions:
A)If unable to keep condition 1 ( SDA is "Low" during power up):
Control SDA ,SCL to be "High" as shown in figure below.
tLOW
tSU:DAT tDH
A
fter Vcc becoms stable
SCL
VCC
SD
A
Fig.34 SCL="H" and SDA="L"
tSU:DAT
Fi
g
.35 SCL="L" and SDA="L"
A
fter Vcc becoms stable
B)If unable to keep condition 2.
After power becomes stable, execute software reset. (See Fig.29)
C)If unable to keep both conditions 1 and 2.
Follow the instruction A first, then the instruction B.
LVCC Circuit
LVCC circuit inhibits write operation at low voltage, and prevents an inadvertent write. Write operation is inhibited below the
LVCC voltage (Typ.=1.2V).
Vcc NOISE
Bypass Condenser
Noise and surges on power line may cause abnormal function. It is recommended that the bypass condensers (0.1µF) are
attached on the Vcc and GND line beside the device. It is also recommended to attach bypass condensers on the board
close to the connector.
Recommended conditions of tR, tOFF, Vbot
tR tOFF Vbot
Below 10ms Above 10ms Below 0.3V
Below 100ms Above 10ms Below 0.2V
Technical Note
BR24C21,BR24C21F,BR24C21FJ,BR24C21FV,
BU9882-W,BU9882F-W,BU9882FV-W
20/22
www.rohm.com 2011.08 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
Notes for Use
1) Described numeric values and data are design representative values, and the values are not guaranteed.
2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and operating temperature range and so forth are
exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings.
In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and
see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI.
4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltages is lower than that
of GND terminal.
5) Heat design
In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.
6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluated design sufficiently