74VHC4052MTCX_NL - Fairchild Semiconductor

April 1994

Revised April 1999

74VHC4051 • 74VHC4052 • 74VHC4053 8-Channel Analog Multiplexer • Dual 4-Channel Analog Multip lexer • T ripl e

2-Channel Analog Multiplexer

74VHC4051 • 74VHC4052 • 74VHC4053

8-Channel Analog Multiplexer • Dual 4-Channel Analog

Multiplexer • Triple 2-Channel Analog Multiplexer

General Descript ion

These mu ltiplexers are digi tally control led analog switches

implemented in advanced silicon-gate CMOS technology.

These switches have low “on” resistance and low “off” leak-

ages. They are bidirectional switches, thus any analog

input may be use d as an outp ut an d vice- ver sa. A lso the se

switches contain linearization circuitry which lowers the

“on” resistance and increases switch linearity. These

devices allow control of up to ±6V (peak) analog signals

with digit al contr ol si gn als of 0 to 6V. Three suppl y pins are

provided for VCC, ground, an d VEE. This enables the con-

nection of 0–5V logic signals when VCC = 5V and an anal og

input range of ±5V when VEE = 5V. All three devices also

have an inhibit control which when high will disable all

switches to their off state. All analog inputs and outputs

and digital inputs are protected from electr ostatic damage

by diodes to VCC and ground.

VHC4051: This device connects together the outputs of 8

switches, thus achieving an 8 channel Multiplexer. The

binary code placed on the A, B, and C select lines deter-

mines which one of the eight switches is “on”, and con-

nects one of the eight inputs to the common output.

VHC4052: This device connects together the outputs of 4

switches in two sets, thus achieving a pair of 4-channel

multiplexers. The binary code placed on the A, and B

select lines determine which switch in each 4 channel sec-

tion is “on” , c onnecting one of the fo ur inputs in each sec-

tion to its common output. This enables the implementation

of a 4-channel differential multiplexer.

VHC4053: This device conta ins 6 switches whose out puts

are connect ed togeth er in pairs, thus implementin g a triple

2 channel multiplexer, or the equivalent of 3 single-pole-

double throw configur ations. Each of the A, B, o r C select

lines inde pen dently co ntr ols on e pa i r of switche s , sele cting

one of the two switches to be “on”.

Features

■Wide analog input voltage range: ±6V

■Low “on” resistance: 50 typ. (VCC–VEE = 4.5V)

30 typ. (VCC–VEE = 9V)

■Logic le vel translat ion to enable 5V logic wi th ±5V ana-

log signals

■Low quiescen t curre nt: 80 µA maximum

■Matched switch characteristic

■Pin and function compatible with the 74HC4051/ 4052/

4053

Ordering Code:

Surface m ount pa c k ages are als o availa ble on Tape and Re el. Specify by appendi ng the suffix let te r “X” to the ordering co de.

Order Number Package Number Package Description

74VHC4051M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

74VHC4051WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

74VHC4051MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC4051N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

74VHC4052M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

74VHC4052WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

74VHC4052MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC4052N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

74VHC4053M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

74VHC4053WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

74VHC4053MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC4053N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2

74VHC4051 • 74VHC4052 • 74VHC4053

Connection Diagrams

Top View

Truth Tables

4051

4052

4053

Input “ON”

INHCBAChannel

H XXX None

L LLL Y0

LLLH Y1

LLHL Y2

LLHH Y3

LHLL Y4

LHLH Y5

LHHL Y6

L HHH Y7

Inputs “ON” Channels

INH B A X Y

HXXNone None

LLL 0X 0Y

LLH 1X 1Y

LHL 2X 2Y

LHH 3X 3Y

Input “ON” C hannels

INHCBA C B A

H X X X None None None

L L L L CX BX AX

LLLHCX BX AY

L L H L CX BY AX

LLHHCX BY AY

L H L L CY BX AX

LHLHCY BX AY

L H H L CY BY AX

L HHH CY BY AY

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74VHC4051 • 74VHC4052 • 74VHC4053

Logic Diagrams

74VHC4051

74VHC4052

74VHC4053

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74VHC4051 • 74VHC4052 • 74VHC4053

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Absolute Maximum Ratings are those values beyond which dam-

age to the device may occur.

Note 2: Unless ot herwise specified all voltag es are refe renced to ground.

Note 3: P ower Dissipa tion temper ature dera ting — plas tic “N” packa ge: −

12 mW/°C from 65°C to 85°C.

Supply Voltage (VCC)−0.5 to +7.5V

Supply Voltage (VEE)+0.5 to −7.5V

Control Input Voltage (VIN)−1.5 to VCC+1.5V

Switch I/O Vo ltage (VIO)V

EE−0.5 to VCC+0.5V

Clamp Diode Current (IIK, IOK)±20 mA

Output Current, per pin (IOUT)±25 mA

VCC or GND Current, per pin (ICC)±50 mA

Storage Temperature Range

(TSTG)−65°C to +150°C

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 seconds) 26 0°C

Min Max Units

Supply Voltage (V CC)26V

Supply Voltage (VEE)0−6V

DC Input or Output Voltage 0 VCC V

(VIN, VOUT)

Operating T emperature Range

(TA)−40 +85 °C

Input Rise or Fall Times

(tr, t f)

VCC = 2.0V 1000 ns

VCC = 4.5V 500 ns

VCC = 6.0V 400 ns

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74VHC4051 • 74VHC4052 • 74VHC4053

DC Electrical Characteristics (Note 4)

Note 4: F or a power supply of 5V ±10% the worst case on resistances (RON) occurs f or VHC at 4.5V. Thus the 4 .5 V v alues s hould be us ed wh en designing

with this supply. Worst case VIH an d V IL occu r at VCC = 5. 5V an d 4.5V resp ec t iv ely. (T he VIH value at 5. 5V is 3.85V.) T he w orst cas e leakage curre nt occur

for CMO S at th e higher v oltage and so the 5. 5V values s hould be us ed.

Note 5: At suppl y voltages (VCC–VEE) ap proaching 2V the a nalog swit ch on resis tance bec omes ex tremely n on-linear. Therefo re it is rec ommende d that

these dev ic es be used to tran smit digital only when using these s upply vo lta ges.

Note 6: Adjust 0 dB for f = 1 kHz (Null R1/RON Attenuation).

Symbol Parameter Conditions VEE VCC TA = 25°CT

A = −40 to 85°CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level 2.0V 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 V

6.0V 4.2 4.2 V

VIL Maximum LOW Level 2.0V 0.5 0.5 V

Input Voltage 4.5V 1.35 1.35 V

6.0V 1.8 1.8 V

RON Maximum “ON” Resistance VINH = VIL, IS = 2.0 mA GND 4.5V 40 160 200 Ω

(Note 5) VIS = VCC to VEE −4.5V 4.5V 30 120 150 Ω

(Figure 1) −6.0V 6.0V 20 100 125 Ω

VINH = VIL, IS = 2.0 mA GND 2.0V 100 230 280 Ω

VIS = VCC or VEE GND 4.5V 40 110 140 Ω

(Figure 1) −4.5V 4.5V 20 90 120 Ω

−6.0V 6.0V 15 80 100 Ω

RON Maximum “ON” Resistance VINH = VIL GND 4.5V 10 20 25 Ω

Matching VIS = VCC to GND −4.5V 4.5V 5 10 15 Ω

−6.0V 6.0V 5 10 12 Ω

INMaximum Control VIN = VCC or GND ±.05 ±0.5 µA

Input Current VCC = 2 − 6V

ICC Maximum Quiescent VIN = VCC or GND GND 6.0V 4 40 µA

Supply Current IOUT = 0 µA−6.0V 6.0V 8 80 µA

IIZ Maximum Switch “OFF” VOS = VCC or VEE GND 6.0V ±60 ±300 nA

Leakage Current VIS = VEE or VCC −6.0V 6.0V ±100 ±500 nA

(Switch Input) VINH = VIH (Figure 2)

IIZ Maximum Switch “ON” VIS = VCC to VEE GND 6.0V ±0.1 ±1.0 µA

Leakage Current VHC4051 VINH = VIL −6.0V 6.0V ±0.2 ±2.0 µA

(Figure 3)

VIS = VCC to VEE GND 6.0V ±0.050 ±0.5 µA

VHC4052 VINH = VIL −6.0V 6.0V ±0.1 ±1.0 µA

(Figure 3)

VIS = VCC to VEE GND 6.0V ±0.05 ±0.5 µA

VHC4053 VINH = VIL −6.0V 6.0V ±0.5 ±0.5 µA

(Figure 3)

IIZ Maximum Switch VOS = VCC or VEE GND 6.0V ±0.1 ±1.0 µA

“OFF” Leakage VHC4051 VIS = VEE or VCC −6.0V 6.0V ±0.2 ±2.0 µA

Current (Common Pin) VINH = VIH

VOS = VCC or VEE GND 6.0V ±0.05 ±0.5 µA

VHC4052 VIS = VEE or VCC −6.0V 6.0V ±0.1 ±1.0 µA

VINH = VIH

VOS = VCC or VEE GND 6.0V ±0.05 ±0.5 µA

VHC4053 VIS = VEE or VCC −6.0V 6.0V ±0.05 ±0.5 µA

VINH = VIH

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74VHC4051 • 74VHC4052 • 74VHC4053

AC Electrical Characteristics

VCC = 2.0V − 6.0V, VEE = 0V − 6V, CL = 50 pF (unless otherwise specified)

Symbol Parameter Conditions VEE VCC TA=25°CT

A=−40 to 85°CUnits

Typ Guaranteed Limits

tPHL, tPLH Maximum Propagation Delay

Switch In to Out GND 3.3V 25 35 40 ns

GND 4.5V 5 12 15 ns

−4.5V 4.5V 4 8 12 ns

−6.0V 6.0V 3 7 11 ns

tPZL, tPZH Maximum Switch Turn “ON”

Delay RL = 1 kΩGND 3.3V 92 200 250 ns

GND 4.5V 69 87 ns

−4.5V 4.5V 16 46 58 ns

−6.0V 6.0V 15 41 51 ns

tPHZ, tPLZ Maximum Switch Turn “OFF”

Delay GND 3.3V 65 170 210 ns

GND 4.5V 28 58 73 ns

−4.5V 4.5V 18 37 46 ns

−6.0V 6.0V 16 32 41 ns

fMAX Minimum Switch GND 4.5V 30 MHz

Frequency Response −4.5V 4.5V 35 MHz

20 log (VI/VO) = 3 dB

Control to Switch RL = 600Ω,V

IS = 4 VPP 0V 4.5V 1080 mV

Feedthrough Noise f = 1 MHz, VIS = 8 VPP −4.5V 4.5V 250 mV

CL = 50 pF

Crosstalk between RL = 600Ω,V

IS = 4 VPP 0V 4.5 −52 dB

any Two Switches f = 1 MHz VIS = 8 VPP −4.5V 4.5V −50 dB

Switch OFF Signal RL = 600Ω,V

IS = 4 VPP 0V 4.5V −42 dB

Feedthrough f = 1 MHz, VIS = 8 VPP −4.5V 4.5V −44 dB

Isolation VCTL = VIL

THD Sinewave Harmonic RL = 10 kΩ,V

IS = 4 VPP 0V 4.5V 0.013 %

Distortion CL = 50 pF, VIS = 8 VPP −4.5V 4.5V 0.008 %

f = 1 kHz

CIN Maximum Control 5 10 10 pF

Input Capacitance

CIN Maximum Switch Input 15 pF

Input Capacitance 4051 Common 90

4052 Common 45

4053 Common 30

CIN Maximum Feedthrough 5 pF

Capacitance

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74VHC4051 • 74VHC4052 • 74VHC4053

AC Test Circuits and Switching Time Waveforms

FIGURE 1. “ON” Resistance

FIGURE 2. “OFF” Channel Leakage Current FIGURE 3. “ON” Channel Leakage Current

FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output

FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output

FIGURE 6. tPZH, tPHZ Propagation Delay TIme Control to Signal Output

FIGURE 7. Crosstalk: Control Input to Signal Output

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74VHC4051 • 74VHC4052 • 74VHC4053

AC Test Circuits and Switching Time Waveforms (Continu ed )

FIGURE 8. Crosstalk Between Any Two Switches

Typical Performance Characteristics

Typical “On” Resistance

vs Input Voltage

VCC=−VEE

Special Considerations

In c ert ain app l ications the ext ern al lo ad -re si stor cu rr ent ma y in cl ude b oth VCC and sign al lin e com pon en ts. To avoid dr aw-

ing VCC current when sw itch cur ren t flo w s into the an al og switch pins, the volta ge d ro p ac ross the sw itch mus t not exceed

1.2V (calculated from the ON resistance).

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74VHC4051 • 74VHC4052 • 74VHC4053

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

Package Number M16A

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

Package Number M16B

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74VHC4051 • 74VHC4052 • 74VHC4053

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

74VHC4051 • 74VHC4052 • 74VHC4053 8-Channel Analog Multiplexer • Dual 4-Channe l Analog Multiplexer • Triple

2-Channel Analog Multiplexer

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life sup por t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E