2010 Microchip Technology Inc. DS70138G
dsPIC30F3014/4013
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
DS70138G-page 2 2010 Microchip Technology Inc.
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by up dates. I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC , PI Cmi cro, PIC START,
PIC32 logo, rfPIC and UNI/O are registered trademark s of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In- Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PIC DEM .net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance ,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-666-1
Note the following details of the code protection feature on Microch ip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2010 Microchip Technology Inc. DS70138G-page 3
dsPIC30F3014/4013
High-Performance Modified RISC CPU:
• Modified Harvard Architecture
• C Compil er Optim iz ed Inst ruc tio n Set Architecture
• Flexible Addressing modes
• 83 Base Instruc tio ns
• 24 -Bit Wi de Instructions, 16 -Bit Wide Data Path
• Up to 48 Kbytes On-Chip Flash Program Space
• 2 Kbytes of On-Chip Data RAM
• 1 Kbyte of Nonvolatile Data EEPROM
• 16 x 16-Bit Working Register Array
• Up to 30 MIPS Operation:
- DC to 40 MHz External Clock Input
- 4 MHz-10 MHz Oscillator Input with
PLL Active (4x, 8x, 16x)
• Up to 33 Interrupt Sources:
- 8 user-selectable priority levels
- 3 external interrupt sources
- 4 processo r traps
DSP Features:
• Dual Data Fetch
• Modulo and Bit-Reversed modes
• Two 40-Bit Wide Accu mu lat ors with Op tio nal
saturati on Log ic
• 17-Bit x 17-Bit Single-Cycle Hardware
Fract ion al/ I nte ger Mu lti pli er
• All DSP Instructions are Single Cycle
- Multiply-Accumulate (MAC) Operation
• Single-Cycle ±16 Shift
Peripheral Feat ures:
• High-Current Sink/Source I/O Pins: 25 mA/25 mA
• Up to Fiv e 16-Bit T imers/C ounters; Op tionally Pai r
Up
16-Bit Ti mers into 32-Bit Timer modules
• Up to Four 16-Bit Capture Input Functions
• Up to Four 16-Bit Compare/PWM O utput Functions
• Data Converter Interface (DCI) Supports Comm on
Audio Codec Protocols, Inclu ding I2S and AC’97
• 3-Wire SPI module (supports 4 Frame modes)
•I
2C™ module Supports Mu lti-Master/Slave mode
and 7-Bit/10-Bit Addressing
• Up to T w o Addressable UA RT modul es with FIFO
Buffers
• CAN bus module Compliant with CAN 2.0B
Standard
Analog Features:
• 12-Bit Analog-to-Digital Converter (ADC) with:
- 200 ksps co nve rsion rate
- Up to 13 input channels
- Conversion available during Sleep and Idle
• Programmable Low-Voltage Detection (PLVD)
• Programmable Brown-out Reset
S pecial Microcontroller Features:
• Enhanced Flash Program Memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100K (typical)
• Data EEPROM Memory:
- 100,000 erase/write cycle (min .) for
industrial temperature range, 1M (typical)
• Self- Repr ogrammable und er Software Contro l
• Power-on Reset (POR), Power-up Timer (PWR T)
and Oscillator Start-up Timer (OST)
• Flexib le Watchdog Timer (WDT) with On-Chip
Low-Power RC Oscillator for Reliable Operation
• Fail- Safe Cloc k Mo nitor Operation:
- Detects clock failure and switches to on-chip
low-power RC oscillat or
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• Selectable Power Ma nag em ent mo des :
- Sleep, Idle and Alternate Clock modes
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s Reference Manual”
(DS70157).
High-Performance, 16-Bit Digital Signal Controllers
dsPIC30F3014/4013
DS70138G-page 4 2010 Microchip Technology Inc.
CMOS Technology:
• Low-Power, High-Speed Flash Technology
• Wide Operating Voltage Range (2.5V to 5.5V)
• Industrial and Extended Temperature Ranges
• Low-Power Consumption
dsPIC30F3014/4013 Contr oller Family
Pin Diagrams
Device Pins Program Mem ory SRAM
Bytes EEPROM
Bytes Timer
16-Bit Input
Cap
Output
Comp/
Std PWM
Codec
Interface A/D 12-Bit
200 Ksps
UART
SPI
I2C™
CAN
Bytes Instructions
dsPIC30F3014 40/44 24K 8K 2048 1024 3 2 2 — 13 ch 2 1 1 0
ds P I C 30 F 4 013 40/44 48K 16K 2048 1024 5 4 4 AC ’ 9 7 , I 2S 13 ch 2 1 1 1
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6
RF0
RF1
RD2
IC1/INT1/RD8
AN8/RB8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
dsPIC30F3014
MCLR
VDD
Vss
IC2/INT2/RD9
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
OSC2/CLKO/RC15
OSC1/CLKI
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
EMUD2/OC2/RD1
AVDD
AVss
RD3
Vss
VDD
EMUC3/SCK1/RF6
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
EMUC2/OC1/RD0
VDD
U2RX/CN17/RF4
U2TX/CN18/RF5
AN4/CN6/RB4
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
AN5/CN7/RB5
INT0/RA11
Vss
AN3/CN5/RB3
40-Pin PDIP
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6
C1RX/RF0
C1TX/RF1
OC3/RD2
IC1/INT1/RD8
AN8/RB8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
dsPIC30F4013
MCLR
VDD
VSS
IC2/INT2/RD9
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
OSC2/CLKO/RC15
OSC1/CLKI
AN9/CSCK/RB9
AN10/CSDI/RB10
AN11/CSDO/RB11
AN12/COFS/RB12
EMUD2/OC2/RD1
AVDD
AVSS
OC4/RD3
VSS
VDD
EMUC3/SCK1/RF6
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
EMUC2/OC1/RD0
VDD
U2RX/CN17/RF4
U2TX/CN18/RF5
AN4/IC7/CN6/RB4
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
AN5/IC8/CN7/RB5
INT0/RA11
VSS
AN3/CN5/RB3
40-Pin PDIP
2010 Microchip Technology Inc. DS70138G-page 5
dsPIC30F3014/4013
Pin Diagrams (Continued)
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/NT1/RD8
RD2
VDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
NC
VSS
RD3
IC2/INT2/RD9
INT0/RA11
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
MCLR
NC
AVDD
AVSS
AN9/RB9
AN10/RB10
AN12/RB12
EMUC2/OC1/RD0
EMUD2/OC2/RD1
VDD
VSS
RF0
RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
U1RX/SDI1/SDA/RF2
AN4/CN6/RB4
AN5/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
NC
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
dsPIC30F3014
44-Pin TQFP
AN11/RB11
NC
dsPIC30F3014/4013
DS70138G-page 6 2010 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin QFN(1)
dsPIC30F3014
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/INT1/RD8
RD2
VDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
VSS
RD3
IC2/INT2/RD9
INT0/RA11
AN4/CN6/RB4
AN5/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
OSC2/CLKO/RC15
VDD
VDD
VSS
VSS
OSC1/CLKI
EMUC2/OC1/RD0
EMUD2/OC2/RD1
VDD
VDD
VSS
RF0
RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
U1RX/SDI1/SDA/RF2
AN12/RB12
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
MCLR
AN11/RB11
AVDD
AVSS
AN9/RB9
AN10/RB10
NC 44
43
42
41
40
39
38
37
36
35
12
13
14
15
16
17
18
19
20
21
330
29
28
27
26
25
24
23
4
5
7
8
9
10
11
1
232
31
6
22
33
34
Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2010 Microchip Technology Inc. DS70138G-page 7
dsPIC30F3014/4013
Pin Diagrams (Continued)
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/INT1/RD8
OC3/RD2
VDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
NC
VSS
OC4/RD3
IC2/INT2/RD9
INT0/RA11
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
MCLR
NC
AVDD
AVSS
AN9/CSCK/RB9
AN10/CSDI/RB10
AN12/COFS/RB12
EMUC2/OC1/RD0
EMUD2/OC2/RD1
VDD
VSS
C1RX/RF0
C1TX/RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
U1RX/SDI1/SDA/RF2
AN4/IC7/CN6/RB4
AN5/IC8/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
NC
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
dsPIC30F4013
44-Pin TQFP
AN11/CSDO/RB11
NC
dsPIC30F3014/4013
DS70138G-page 8 2010 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin QFN(1)
44
43
42
41
40
39
38
37
36
35
12
13
14
15
16
17
18
19
20
21
330
29
28
27
26
25
24
23
4
5
7
8
9
10
11
1
232
31
dsPIC30F4013
6
22
33
34
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/NT1/RD8
OC3/RD2
VDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
VSS
OC4/RD3
IC2/INT2/RD9
INT0/RA11
AN4/IC7/CN6/RB4
AN5/IC8/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
OSC2/CLKO/RC15
VDD
VDD
VSS
VSS
OSC1/CLKI
EMUC2/OC1/RD0
EMUD2/OC2/RD1
VDD
VDD
VSS
C1RX/RF0
C1TX/RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
U1RX/SDI1/SDA/RF2
AN12/COFS/RB12
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
MCLR
AN11/CSDO/RB11
AVDD
AVSS
AN9/CSCK/RB9
AN10/CSDI/RB10
NC
Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2010 Microchip Technology Inc. DS70138G-page 9
dsPIC30F3014/4013
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 CPU Architecture Overview ........................................................................................................................................................ 15
3.0 Memory O rganization................................................................................................................................................................. 25
4.0 Address G enerator Units............................................................................................................................................................ 37
5.0 Flash Pro g ram Memory....... ............... ........................... ..................... ............................ ............................................................ 43
6.0 Data EEP R OM Memo ry.... ............................ ..................... ........................... ..................... ........................................................ 49
7.0 I/O Ports.............................. ............................ ........................... ........................... ..................................................................... 53
8.0 Interrupts.................................................................................................................................................................................... 59
9.0 Timer1 Module ........................................................................................................................................................................... 67
10.0 Timer2/3 Module .............................. .. .. .... .. ....... .. .... .. .... .. ....... .. .... .. .. .... ....... .. .. .... .. .... ................................................................. 71
11.0 Timer4/5 Module .. .... .. .. .... .. .. ....... .. .... .. .. .... ..... .... .. .. .. .... .. ....... .. .. .... .. .. ....... .. .... .. .. .... .. ................................................................. 77
12.0 Input Capture Module............................. .. ....... .... .. .... .. .... ....... .. .... .. .... .. ....... .... .. .... .. ....... ............................................................ 81
13.0 Output Compa re Module........................ ..................... ..................... ..................... ..................................................................... 85
14.0 I2C™ Module ............................................................................................................................................................................. 91
15.0 SP I Module................................................................................................................................................................................. 99
16.0 U nivers al Asynchr onous Receiver Transmi tter (UART) Module .............................................................................................. 103
17.0 CAN Module............................................................................................................................................................................. 111
18.0 Data Converter Interface (DCI) Module..................................................................... ............... ................................................ 121
19.0 12-bit Analog- to-Digital Converter (ADC) Module .................................................................................................................... 131
20.0 System Inte g ration .... ............... ..................... ..................... ..................... ..................... ............................................................ 141
21.0 Instruction Set Summary.......................................................................................................................................................... 159
22.0 Development Support............................................................................................................................................................... 167
23.0 Electrical Characteristics.......................................................................................................................................................... 171
24.0 Packagin g In fo rmation... ............... ..................... ..................... ..................... ............................................................................. 211
Index ................................................................................................................................................................................................. 219
The Micro chip Web Site............................... ........................... ............................ ............................................................................... 225
Customer Change Notification Service.............................................................................................................................................. 225
Customer Support........................................................................................................... ................................................................... 225
Reader Response.............................................................................................................................................................................. 226
Product Identification System ............................................................................................................................................................ 227
TO OUR VALUED CUS TOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any ques tions or comments regarding this publication, please contact the M arketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
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http://www.microchip.com
You can determ ine the vers ion of a data sheet by e xamining its literature number f ound on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errat a sheet. The errata will specify the revisi on o f
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
dsPIC30F3014/4013
DS70138G-page 10 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 11
dsPIC30F3014/4013
1.0 DEVICE OVERVIEW This document contains specific information for the
dsPIC30F3014/4013 Digital Signal Controller (DSC)
devices. The dsPIC30F3014/4013 devices contain
extensive Digital Signal Processor (DSP) functionality
within a high-performance, 16-bit microcontroller
(MCU) architecture. Figure 1-1 and Figure 1-2 show
device block diagrams for dsPIC30F3014 and
dsPIC30F4013, respectively.
FIGURE 1-1: dsPIC30F3014 BLOCK DIAGRAM
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s Reference Manual”
(DS70157).
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
Power-up
Timer
Oscillator
St art-up Timer
POR/BOR
Reset
Watchdog
Timer
Instruction
Decode and
Control
OSC1/CLKI
MCLR
V
DD
, V
SS
AN4/CN6/RB4
AN12/RB12
Low-Voltage
Detect
UART1,
Timing
Generation
AN5/CN7/RB5
16
PCH PCL
Program Counter
ALU<16>
16
24
24
24
24
X Data Bus
IR
I
2
C™
Timers
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
PCU
12-Bit ADC
U2TX/CN18/RF5
EMUC3/SCK1/RF6
Input
Capture
Module
Output
Compare
Module
EMUD1/SOSCI/T2CK/U1ATX/
PORTB
RF0
RF1
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
PORTD
16
16 16
16 x 16
W Reg Array
Divide
Unit
Engine
DSP
Decode
ROM Latch
16
Y Data Bus
Effective A ddress
X RAGU
X WAGU
Y AGU AN0/V
REF
+/CN2/RB0
AN1/V
REF
-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
OSC2/CLKO/RC15
U2RX/CN17/RF4
AV
DD
, A V
SS
UART2
16
16
16
16
16
PORTC
PORTF
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(1 Kbyte)
RAM X Data
(1 Kbyte)
RAM
Address
Latch Address
Latch
Control Signals
to Various Blocks
EMUC2/OC1/RD0
EMUD2/OC2/RD1
RD2
RD3
IC1/INT1/RD8
IC2/INT2/RD9
16
SPI1
Address Latch
Program Memory
(24 Kbytes)
Data Latch
Data EEPROM
(1 Kbyte)
16
CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/
CN0/RC14
PORTA
INT0/RA11
dsPIC30F3014/4013
DS70138G-page 12 2010 Microchip Technology Inc.
FIGURE 1-2: dsPIC30F4013 BLOCK DIAGRAM
AN8/RB8
AN9/CSCK/RB9
AN10/CSDI/RB10
AN11/CSDO/RB11
Power-up
Timer
Oscillator
S tart-up Timer
POR/BOR
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
MCLR
V
DD
, V
SS
AN4/IC7/CN6/RB4
AN12/COFS/RB12
Low-Voltage
Detect
Timing
Generation
AN5/IC8/CN7/RB5
16
PCH PCL
Program Counter
ALU<16>
16
24
24
24
24
X Data Bus
IR
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
PCU
U2TX/CN18/RF5
EMUC3/SCK1/RF6
EMUD1/SOSCI/T2CK/U1ATX/
PORTB
C1RX/RF0
C1TX/RF1
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
PORTD
16
16 16
16 x 16
W Reg Array
Divide
Unit
Engine
DSP
Decode
ROM Latch
16
Y Data Bus
Effective Address
X RAGU
X WAGU
Y AGU AN0/V
REF
+/CN2/RB0
AN1/V
REF
-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
OSC2/CLKO/RC15
U2RX/CN17/RF4
AV
DD
, A V
SS
16
16
16
16
16
PORTC
PORTF
16
16
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
(1 Kbyte)
RAM X Data
(1 Kbyte)
RAM
Address
Latch Address
Latch
Control Signals
to Various Blocks
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
IC1/INT1/RD8
IC2/INT2/RD9
16
Address Latch
Program Memory
(48 Kbytes)
Data Latch
Data EEPROM
(1 K byte )
16
CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/
CN0/RC14
PORTA
INT0/RA11
UART1,
I
2
C™
DCI
12-Bit ADC
Timers
Input
Capture
Module
Output
Compare
Module
UART2
SPI1
CAN1
2010 Microchip Technology Inc. DS70138G-page 13
dsPIC30F3014/4013
Table 1-1 provid es a bri ef descript ion of dev ic e I/O pin-
out s and the funct ions that may be multiple xed to a port
pin. Mul tiple fu nction s may exist on one po rt pin. Whe n
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name Pin
Type Buffer
Type Description
AN0-AN12 I Analog Analog input channels. AN6 and AN7 are also used for device programming
data and clock inputs, respectively.
AVDD P P Positive supply for analog module. This pin must be connected at all times.
AVSS P P Ground reference for analog module. This pin must be connected at all times.
CLKI
CLKO
I
O
ST/CMOS
—
External clo ck source inp ut. Alw ays ass ocia ted w ith OSC1 pin func tion .
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
CN0-CN7,
CN17-CN18 I ST Input change notification inputs. Can be software programmed for internal
weak pull-ups on all inputs.
COFS
CSCK
CSDI
CSDO
I/O
I/O
I
O
ST
ST
ST
—
Data Converter Interface Frame Synchronization pin.
Data Converter Interface Serial Clock input/output pin.
Data Converter Interface Serial data input pin.
Data Converter Interface Serial data output pin.
C1RX
C1TX I
OST
—CAN1 bus receive pin.
CAN1 bus transmit pin.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Co mmunication Channel da ta input/output pi n.
ICD Tertiar y Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
IC1, IC2, IC7,
IC8 I ST Capture inputs 1,2, 7 and 8.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External inte rrup t 0.
External inte rrup t 1.
External inte rrup t 2.
LVDIN I Analog Low-Voltage Detect Reference Voltage Input pin.
MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an
active-low Reset to the device.
OCFA
OC1-OC4 I
OST
—Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare outputs 1 through 4.
OSC1
OSC2
I
I/O
ST/CMOS
—
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
PGD
PGC I/O
IST
ST In-Circuit Serial Programming data input/output pin.
In-Circuit Serial Programming clock input pin.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
dsPIC30F3014/4013
DS70138G-page 14 2010 Microchip Technology Inc.
RA11 I/O ST PORTA is a bidirectional I/O port.
RB0-RB12 I/O ST PORTB is a bidirectional I/O port.
RC13-RC15 I/O ST PORTC is a bidirectional I/O port.
RD0-RD3,
RD8, RD9 I/O ST PORTD is a bidirectional I/O port.
RF0-RF5 I/O ST PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI 1 slave synchronization.
SCL
SDA I/O
I/O ST
ST Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
SOSCO
SOSCI O
I—
ST/CMOS 32 kHz low-power oscillator crystal output.
32 kHz low- power oscilla tor crystal input. ST buffer when configured in RC
mode; CMOS otherwise.
T1CK
T2CK I
IST
ST Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
O
ST
—
ST
—
UART1 receive.
UART1 transmit.
UART1 alternate receive.
UART1 alternate transmit.
VDD P — Positive supply for logic and I/O pins.
VSS P — Ground reference for logic and I/O pins.
VREF+ I Analo g Analog voltage reference (high) input.
VREF- I Analo g Analog voltage reference (low) input.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin
Type Buffer
Type Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output
I = Input P = Power
2010 Microchip Technology Inc. DS70138G-page 15
dsPIC30F3014/4013
2.0 CPU ARCHITECTURE
OVERVIEW
2.1 Core Overview
This section contains a brief overview of the CPU
architecture of the dsPIC30F.
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (refer to Section 3.1 “Program
Addr ess Space”), and the Most Significant bit (MSb)
is ign ored du ring no rmal program executi on, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are
supported using the DO and REPEAT inst ru cti on s, b oth
of which are int errup tib le at any point.
The working register array consists of 16-bit x 16-bit
register s, each of whi ch can act as dat a, addre ss or off-
set registers. One working register (W15) operates as
a Software Stack P ointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Genera-
tion Unit (AGU). Most instructions operate solely
through the X memory, AGU, which provides the
appearance of a single, unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2 “Data Address Space”). The X and Y
data space boundary is device-specific and cannot be
alter ed by the user . Each dat a word consis ts of 2 bytes,
and mos t instruction s can address data eith er as words
or bytes.
There are two methods of accessing data stored in
program memory:
• The upper 32 Kbytes of data space memory can
be mappe d into the lowe r hal f (us er space) of pro-
gram space at any 16K program word boundary,
defined b y the 8-bit Program S pace V isibility Pag e
(PSVPAG) register. This lets any instruction
access program space as if it were data space,
with a limitation that the access requires an addi-
tional cycle. More over, only the lower 16 bits of
each instruction word can be accessed using this
method.
• Linear indirect access of 32K word pages within
progra m spac e is also possibl e using any w orking
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
Overhead-free circular buffers (Modulo Addressing)
are supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports Bit-Reversed Addressing on
dest inatio n ef fectiv e addres ses to great ly sim plify inp ut
or output data reordering for radix-2 FFT algorithms.
Refer to Section 4.0 “Address Generator Units” for
details on Modulo and Bit-Reversed Addressing.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct, Register
Indirect, Register Offset and Literal Offset Addressing
modes. Instructions are associated with predefined
addressing modes, depending upon their functional
requirements.
For m os t i ns tru c ti o ns , t he c or e i s c apa bl e of e xe c ut i ng
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A+B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core a rithmetic cap ability and throughput. It
features a high-speed, 17 -bit x 17-bit multip lier , a 40-bit
ALU, two 40-bit saturating accumulators and a 40-bit
bidirectional barrel shifter. Data in the accumulator, or
any working register , c an be shif ted up to 15 bits righ t, or
16 bits left in a single cycle. The DSP instructions oper-
ate seamlessly with all o ther instructions and have been
designed for optimal real-time performance. The MAC
class of instructions can concurrently fetch two data
operands from memory while multiplying two W
registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear is for all others. This has been
achieved in a transparent and flexible manner by
dedicating certain working registers to each address
space for the MAC class of ins tructions.
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s Reference Manual”
(DS70157).
dsPIC30F3014/4013
DS70138G-page 16 2010 Microchip Technology Inc.
The core does not support a multi-stage instruction
pipeline. However, a single-stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle with certain
exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are re served ) a nd 54 interrupts . Ea ch in terru pt
is prioritized based on a us er-assigned priori ty between
1 and 7 (1 being the lowest priority and 7 being the
highest), in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities ranging from 8 to 15.
2.2 Pr ogrammer’s Model
The programmer’s model is shown in Figure 2-1 and
consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program Coun-
ter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register asso-
ciated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary h olding register
and can tr ansfer its con tents to or fro m i t s hos t reg is ter
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
•PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
•DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start and popped on loop end.
When a byte operation is performed on a working
register, only the Least Significant Byte of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes can be manipulated through
byte-wide data memory space accesses.
2.2.1 SOFTW ARE STACK POINTER/
FRAME PO INT E R
The dsPIC® DSC devices contain a software stack.
W15 is the dedicated Software Stack Pointer (SP) and
is automatically modified by exception processing and
subrouti ne calls and retur ns. However, W15 can be ref-
erenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the Stack Pointer (e.g., creating
St ac k Frames ).
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedica ted as a S t a ck Fram e Po int er, as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2 STATUS REGISTER
The dsPIC DSC core has a 16-bit STATUS register
(SR), the Least Significant Byte (LSB) of which is
referred to as the SR Low byte (SRL) and the Most
Significant Byte (MSB) as the SR High byte (SRH). See
Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(includ ing the Z bit ), as wel l as the CPU Inter rupt Pri or-
ity Level Status bits, IPL<2:0> and the Repeat Active
Status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a
complete word value which is then stacked.
The upper byte of the STATUS register contains the
DSP adder/subtracter Status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) Status bit.
2.2.3 PROGRAM COUNTER
The program counter is 23 bits wide; bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
Note: In order to protect against misaligned
stack accesses, W15<0> is always clear.
2010 Microchip Technology Inc. DS70138G-page 17
dsPIC30F3014/4013
FIGURE 2-1 : PROGRAMMER’S MODEL
TABPAG
PC22 PC0
7 0
D0D15
Program Counter
Data Table Page Address
STATUS Register
Working Registers
DSP Operand
Registers
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write-Back
W14/Frame Pointer
W15/Stack Pointer
DSP Address
Registers
AD39 AD0AD31
DSP
Accumulators AccA
AccB
PSVPAG
7 0Program Space Visibility Page Address
Z
0
OA OB SA SB
RCOUNT
15 0REPEAT Loop Counter
DCOUNT
15 0DO Loop Counter
DOSTART
22 0 DO Loop Start Address
IPL2 IPL1
SPLIM Stack Pointer Limit Register
AD15
SRL
PUSH.S Shadow
DO Shadow
OAB SAB
15 0Core Configuration Register
Legend
CORCON
DA DC RA N
TBLPAG
PSVPAG
IPL0 OV
W0/WREG
SRH
DO Loop End Address
DOEND
22
C
dsPIC30F3014/4013
DS70138G-page 18 2010 Microchip Technology Inc.
2.3 Di v ide Support
The dsPIC DSC devices feature a 16/16-bit signed
fraction al d iv ide ope rati on , as w ell as 32/1 6-b it a nd 1 6/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
1. DIVF – 16/16 signed fractional divide
2. DIV.sd – 32/16 signed divide
3. DIV.ud – 32/16 unsigned divide
4. DIV.s – 16/16 signed divide
5. DIV.u – 16/16 unsigned divide
The 16/16 divides are sim ilar to the 32/16 (same number
of iterations), but the dividend is eithe r zero-extended or
sign-extended during the first iteration.
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divid e instruction does not automatica lly
set up the RCOUNT value and it must, therefore, be
explic itly and correctl y specifi ed in the REPEAT instruc-
tion, as shown in Table 2-1 (REPEAT will execute the
target instruction {operand value+1} times). The
REPEAT loop count must be setup for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
TABLE 2-1: DIVIDE INSTRUCTIONS
Note: The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
Instruction Function
DIVF Signed fractional divide: Wm/Wn W0; Rem W1
DIV.sd Signed divide: (Wm+1:Wm)/Wn W0; Rem W1
DIV.s Signed divide: Wm/Wn W0; Rem W1
DIV.ud Unsigned divide: (Wm+1:Wm)/Wn W0; Rem W1
DIV.u Unsigned divide: Wm/Wn W0; Rem W1
2010 Microchip Technology Inc. DS70138G-page 19
dsPIC30F3014/4013
2.4 DSP Engine
The DSP engine consists of a high-speed, 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturati on log ic).
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations,
which require no additional d ata. These in structions are
ADD, SUB and NEG.
The dsPIC30F is a single-cycle instruction flow archi-
tecture, therefore, concurrent operation of the DSP
engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
may be used concurrently by the same in struction (e.g.,
ED, EDAC). (See Table 2-2 for DSP instructions.)
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1. Fractional or integer DSP multiply (IF).
2. Signed or unsigned DSP multiply (US).
3. Conventional or convergent rounding (RND).
4. Automatic saturation on/off for AccA (SATA).
5. Automatic saturation on/off for AccB (SATB).
6. Automatic saturation on/off for writes to data
memory (SATDW).
7. Accumulator Saturation mode selection
(ACCSAT).
A block diagram of the DSP engine is shown in
Figure 2-2.
Note: For CORCON layout, see Table 3-3.
TABLE 2-2: DSP INSTRUCTION
SUMMARY
Instruction Algebraic
Operation ACC WB?
CLR A = 0 Yes
ED A = (x – y)2No
EDAC A = A + (x – y)2No
MAC A = A + (x * y) Yes
MAC A = A + x2 No
MOVSAC No change in A Yes
MPY A = x * y No
MPY.N A = – x * y No
MSC A = A – x * y Yes
dsPIC30F3014/4013
DS70138G-page 20 2010 Microchip Technology Inc.
FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM
Zero Backfill
Sign-Extend
Barrel
Shifter
40-Bit Accumulator A
40-Bit Accumulator B Round
Logic
X Data Bus
To/From W Array
Adder
Saturate
Negate
32
32
33
16
16 16
16
40 40
40 40
S
a
t
u
r
a
t
e
Y Data Bus
40
Carry/Borrow Out
Carry/Borrow In
16
40
Multiplier/Scaler
17-Bit
2010 Microchip Technology Inc. DS70138G-page 21
dsPIC30F3014/4013
2.4.1 MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsign ed ope ration an d can m ultiplex its output u sing a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value, which is sign-
extended to 40 bits. Integer data is inherently
represented as a signed two’s complement value,
where the MSB is defined as a sign bit. Generally
speaki ng, the range of an N-bit two ’ s c om pl em ent in te-
ger is -2N-1 to 2N-1 – 1. For a 16-bit integer, the data
range is -32768 (0x8000) to 32767 (0x7FFF) including
‘0’. For a 32-bit integer, the data range is -
2,147,483,648 (0x8000 0000) to 2,147,483,645
(0x7FFF FFFF).
When the multiplier is configured for fractional multipli-
cation, the data is represented as a two’s complement
fraction , where th e MSB is define d as a sig n bit and the
radix po int is im plied to li e just af ter the si gn bit (QX f or-
mat). The range of an N-bit two’s complement fraction
with this implied radix point is -1.0 to (1 – 21-N). For a
16-bit fraction, the Q15 data range is -1.0 (0x8000) to
0.999969482 (0x7FFF) including ‘0’ and has a preci-
sion of 3.01518x10-5. In Fractional mode, the 16x16
multipl y ope ration genera tes a 1.31 p rodu ct, whi ch ha s
a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU multi-
ply instructions, which includes integer 16-bit signed,
unsigned and mixed sign multiplies.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands direct a 16-bit
result, and word operands direct a 32-bit result to the
specified register(s) in the W array.
2.4.2 DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation
dest ina tio n. F or the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
via the barrel shifter prior to accumulation.
2.4.2.1 Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active-high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active-low and the
other input is complemented. The adder/subtracter
generates overflow Status bits, SA/SB and OA/OB,
which are la tched and reflected in the ST ATUS register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulat or data satu ration if selec ted. It uses
the result of the adder, the overflow Status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow. They are:
1. OA:
AccA overflowed into guard bits
2. OB:
AccB overflowed into guard bits
3. SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 over flow and saturation)
4. SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 over flow and saturation)
5. OAB:
Logical OR of OA and OB
6. SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the correspond-
ing overflow trap flag enable bit (OVATE, OVBTE) in
the INTCON1 register (refer to Section 8.0 “Inter-
rupts”) is set. This allows the user to take immediate
action, for example, to correct system gain.
dsPIC30F3014/4013
DS70138G-page 22 2010 Microchip Technology Inc.
The SA and SB bits are modified each time data
passes through the adder/subtracter but can only be
cleared by the user. When set, they indicate that the
accumula tor has overfl owed it s m aximum range (b it 31
for 32-bit saturation or bit 39 for 40-bit saturation) and
will be saturated if saturation is enabled. When
saturation is not enabled, SA and SB default to bit 39
overflow and, thus, indicate that a catastrophic over-
flow has occurred. If the COVTE bit in the INTCON1
register is set, SA and SB bits generate an arithmetic
warning trap when saturation is disabled.
The overflow and saturation Status bits can optionally
be viewed in the STATUS register (SR) as the logical
OR of OA an d OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). Th is allows programm ers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either a ccum ulator has satu rated. T his w ould be us eful
for complex number arithmetic which typically uses
both the accu mu lato rs.
The device supports three saturation and overflow
modes:
1. Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic load s the maximally positive 9.31
(0x7FFFFFFFFF), or maximally negative 9.31
value (0x8000000000) into the target accumula-
tor. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erro-
neous data or unexpected algorithm problems
(e.g., gain calculations).
2. Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally posi-
tive 1.31 value (0x007FFFFFFF), or maximally
negative 1.31 value (0x0080000000) into the
target accumulator. The SA or SB bit is set and
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
3. Bit 39 Catastrophic Overflow:
The bit 39 overflow Status bit from the adder is
used to set the SA or SB bit which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign ). If the COVTE bit in
the INTCON1 register is set, a catastrophic
ove rflow can init iate a trap excepti on.
2.4.2.2 Accumulator ‘Write-Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the acc umulator that is not targeted by the instruction
into dat a spac e memory. The wri te is performe d across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1. W13, Registe r Dire ct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
2. [W13]+=2, Register Indirect with Post-Increment:
The round ed contents of the non-target accumu-
lator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then
incremented by 2 (fo r a wo rd wr ite).
2.4.2.3 Round Logic
The round logi c is a combination al block which perfo rms
a conventional (biased) or convergent (unbiased) round
function during an accumulator write (store). The Round
mode is determined by the state of the RND bit in the
CORCON register . It generates a 16-bit, 1.15 data value,
which is p a ssed to the dat a sp ace write saturation logic.
If rounding is not indicated by the instruction, a truncated
1.15 data value is stored and the least significant word
(lsw) is simply di scarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and ad ds it to the AC CxH word (bi ts 16
through 31 of the accumulator). If the ACCxL word
(bits 0 through 15 of the accumulator) is between
0x8000 and 0xFFFF (0x8000 included), ACCxH is
incremented. If ACCxL is between 0x0000 a nd 0x7FFF,
ACCxH is lef t unc ha nge d. A cons eq uen ce of thi s alg o-
rithm is that over a succession of random rounding
operations, the value tends to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000 . If this is the case, the Least Sig-
nificant bit (LSb) (bit 16 of the accumulator) of ACCxH
is examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’,
ACCxH is not modified. Assuming that bit 16 is
ef fecti vely ran dom in na ture, this sch eme remove s an y
rounding bias that may accumulate.
The SAC and SAC.R instructions store either a trun-
cated (SAC) or rounded (SAC.R) version of the cont ents
of th e ta rget ac cumu la tor to d ata memo ry via th e X bu s
(subject to data saturation, see Section 2.4.2.4 “Data
Space Write Saturation”). Note that for the MAC clas s
of instructions, the accumulator write-back operation
functions in the same manner, addressing combined
MCU (X and Y) data space though the X bus. For this
class of instructions, the data is always subject to
rounding.
2010 Microchip Technology Inc. DS70138G-page 23
dsPIC30F3014/4013
2.4.2.4 Data Space Write Saturation
In addition to adder/subtracter saturation, writes to data
space may also be saturated but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit,
1.15 fractional value from the round logic block as its
input, together with overflow status from the original
source (accumulator) and the 16-bit round adder.
These are combin ed and us ed to selec t the approp riate
1.15 fractional value as output to write to data space
memory.
If the SATDW bit in the CORCON register is set, data
(aft er rou ndi ng or trunc at ion ) is test ed for ove rflo w and
adjusted accordingly. For input data greater than
0x007FFF, data written to memory is forced to the
maximum positive 1.15 value, 0x7FFF. For input data
less than 0xFF8000, data written to memory is forced
to the maximum negative 1.15 value, 0x8000. The
Most Sig nific ant bit (MSb) of t he sou rce (bit 39) is use d
to determine the sign of the operand being tested.
If the SATDW bi t in the CORCON re gister is not set, the
input data is always passed through unmodified under
all cond it ion s.
2.4.3 BARREL SHIFTER
The barrel shifter is capable of performing up to 16-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators, or the X bus (to support multi-bit
shifts of register or memory data).
The shifter requires a signed binary value to determine
both the m agnitude (number of bits) and dir ection of the
shif t operation. A positive value shif ts the operand right.
A nega tive val ue shifts th e operand left. A val ue of ‘0’
does not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit r esu lt fo r DSP sh if t o peratio ns a nd a 16-bit resu lt
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
to 31 for right shifts, and bit positions 0 to 16 for left
shifts.
dsPIC30F3014/4013
DS70138G-page 24 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 25
dsPIC30F3014/4013
3.0 MEMORY ORGANIZATION
3.1 Program Address Space
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA) or data
space EA, when program space is mapped into data
space as defined by Table 3-1. Note that the program
spa ce add ress i s increm ented b y tw o betwee n suc ces-
sive program words in order to provide compatibility
with data space addressing.
FIGURE 3-1: dsPIC30F3 014 PROGRAM
SPACE MEMORY MAP
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE) for al l acces se s othe r than TBLRD/TBLWT,
which use TBLPAG<7> to deter mine user or c onfigura-
tion space a ccess. In Table 3-1, bit 23 allows acces s to
the Device ID, the User ID and the Configuration bits;
otherwise, bit 23 is always clear.
FIGURE 3-2: dsPIC30F4013 PROGRAM
SPACE MEMORY MAP
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s Reference Manual”
(DS70157).
Reset – Target Address
User Memory
Space
User Flash
Program Memory
Configuration Memory
Space
(8K instructions)
Reset – GOTO Instruction
Alternate Vector Table
Reserved
Interrupt V e ctor Table
Vector Tables
000000
00007E
000002
000080
Device Configuration
004000
003FFE
Data EEPROM
(1 Kbyte)
800000
F80000
Registers F8000E
F80010
DEVID (2)
FEFFFE
FF0000
FF0002
Reserved F7FFFE
Reserved
7FFC00
7FFBFE
(Read ‘0’s)
8005FE
800600
UNITID (32 instr.)
8005BE
8005C0
000004
Reserved
7FFFFE
Reserved
000100
0000FE
000084
Reset – Target Address
User Memory
Space
000000
00007E
000002
000080
Device Configuration
User Fl as h
Program Memory
008000
007FFE
Configuration Memory
Space
Data EEPROM
(16K instructions)
(1 Kbyte)
800000
F80000
Registers F8000E
F80010
DEVID (2)
FEFFFE
FF0000
FF0002
Reserved
F7FFFE
Reserved
7FFC00
7FFBFE
(Read ‘0’s)
8005FE
800600
UNITID (32 instr.)
8005BE
8005C0
Reset – GOTO Instruction
000004
Reserved
7FFFFE
Reserved
000100
0000FE
000084
Alterna te Vector Table
Reserved
Interrupt Vector Table
Vector Tables
dsPIC30F3014/4013
DS70138G-page 26 2010 Microchip Technology Inc.
TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION
FIGURE 3-3: DATA ACCESS FROM PROGRAM SPACE ADDRE SS GENERATION
Access Type Access
Space Program Space Address
<23> <22:16> <15> <14:1> <0>
Instruction Access User 0PC<22:1> 0
TBLRD/TBLWT User
(TBLPAG<7> = 0)TBLPAG<7:0> Data EA<15:0>
TBLRD/TBLWT Configuration
(TBLPAG<7> = 1)TBLPAG<7:0> Data EA<15:0>
Program Space Visibilit y User 0PSVPAG<7:0> Data EA<14:0>
0Prog ram Counter
23 bits
1
PSVPAG Reg
8 bits
EA
15 bi ts
Program
Using
Select
TBLPAG Reg
8 bits
EA
16 bit s
Using
Byte
24-bit EA
0
0
1/0
Select
User/
Configuration
Table
Instruction
Program
Space
Counter
Using
Space
Select
Visibility
Note: Program space visibility cannot be used to access bits<23:16> of a word in program memory .
2010 Microchip Technology Inc. DS70138G-page 27
dsPIC30F3014/4013
3.1.1 DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
This arc hit ec ture f etc hes 24 -bi t wide prog ram me mo ry.
Consequently, instructions are always aligned.
However, as the architecture is modified Harvard, data
can also be present in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the rema pping of a 16 K w ord prog ram space page into
the u pp e r half o f da ta space (s ee Section 3.1.2 “Data
Access from Program Memory Using Program
Space Visibility”). The TBLRDL and TBLWTL instruc-
tions offer a direct method of reading or writing the lsw
of any address within program space, without going
through data sp ac e. The TBLRDH and TBLWTH instru c-
tions are th e only metho d whereby the upp er 8 bit s of a
program space word can be accessed as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word-wid e addres s sp aces, residin g side by side, eac h
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH ac cess the sp ace
which contains the MS Data Byte.
Figure 3-3 shows h ow th e EA is created fo r t a ble oper-
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
A set of t able inst ruc tions are prov ide d to move by te or
word-sized data to and from program space. (See
Figure 3-4 and Figure 3-5.)
1. TBLRDL: Table Read Low
Word: Read the lsw of the program address;
P<15:0> maps to D<15:0>.
Byte: Read one of the LSBs of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> m aps to the d estination b yte when byte
select = 1.
2. TBLWTL: Table Writ e Low (r ef er to Section 5.0
“Flash Program Memory” for details on Flash
programming)
3. TBLRDH: Table Read High
Word: Read the most significant word (msw) of
the program address; P<23:16> maps to D<7:0>;
D<15:8> will always be = 0.
Byte: Read one of the MSBs of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
4. TBLWTH: Table Wri te High (refer to Section 5.0
“Flash Program Memory” for details on Flash
Programming)
FIGURE 3-4: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
0
8
16
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
00000000
00000000
00000000
Progra m Mem or y
‘Pha nto m’ Byte
(read as ‘0’)
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
dsPIC30F3014/4013
DS70138G-page 28 2010 Microchip Technology Inc.
FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MSB)
3.1.2 DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space without the need to use special
instruc tio ns (i.e ., TBLRDL/H, TBLWTL/H ins tru cti ons).
Program space access through the data space occurs
if the MSb of the data space, EA, is set and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4 “DSP
Engine”.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetch es are requ ire d.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP ope ration uses p rogram sp ace mapp ing to acces s
this m em ory reg ion , Y d ata space sho uld ty pic al ly co n-
tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) da ta.
Although each dat a sp ace address, 0x8000 and higher ,
maps directly into a corresponding program memory
address (see Figure 3-6), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits shoul d be progra mmed to forc e an illeg al
instruction to maintain machine robustness. Refer to
the “16-bit MCU and DSC Programmer’s Reference
Manual” (DS701 57) fo r deta ils on instructio n enco din g.
Note that by incrementing the PC by 2 for each
program memory word, the 15 LSbs of data space
addresses directly map to the 15 LSbs in the corre-
sponding program space addresses. The remaining
bits are provid ed by the Progra m Space Vi si bil ity Page
register, PSVPAG<7:0>, as shown in Figure 3-6.
For instructions that use PSV which are executed
outside a REPEAT loop:
• The following instructions require one instruction
cycle in addition to the specified execution time:
-MAC class of instructions with data operand
prefetch
-MOV instr ucti ons
-MOV.D instructions
• All ot her instructions require two ins truction cycles
in addition to the specified execution time of the
instruction.
For instructions that use PSV which are executed
inside a REPEAT loop:
• The following instances require two instruction
cycl es in addit ion to the specified execution t ime
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
interrupt
- Execution upon re-entering the loop after an
interr upt is serviced
• Any other iteration of the REPEAT loop allows the
instruc tion acc es si ng da t a, usin g PSV, to execute
in a single cycle.
0
8
16
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
TBLRDH.W
TBLRDH.B (Wn<0> = 1)
TBLRDH.B (Wn<0> = 0)
Note: PSV access is tempor arily disabled during
table reads/writes.
2010 Microchip Technology Inc. DS70138G-page 29
dsPIC30F3014/4013
FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
23 15 0
PSVPAG(1)
15
15
EA<15> =
0
EA<15> = 1
16
Data
Space
EA
Data Space Program Space
8
15 23
0x0000
0x8000
0xFFFF
0x00
0x000100
0x007FFF
Data Read
Upper Half of Data
Space i s Mapped
into Program Space
0x000200
Address
Concatenation
BSET CORCON,#2 ; PSV bit set
MOV #0x00, W0 ; Set PSVPAG register
MOV W0, PSVPAG
MOV 0x8200, W0 ; Access program memory location
; using a data space access
Note: PSVPAG is an 8-bit register, containing bits<22:15> of the program space address (i.e., it defines
the page in program space to which the upper half of data space is being mapped).
The memory map shown here is for a dsPIC30F4013 device.
dsPIC30F3014/4013
DS70138G-page 30 2010 Microchip Technology Inc.
3.2 Data Addres s Space
The core has two data sp aces. The dat a sp ac es can be
considered either separate (for some DSP ins tructions),
or as one unified linear address range (for MCU instruc-
tions). The data spaces are accessed using two Address
Generation Unit s (AGUs) and s ep arate dat a paths.
3.2.1 DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key ele me nt of th is archi tec ture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent Linear
Addressing space, X and Y spaces have contiguous
addresses.
When executing any instruction other than one of
the MAC class of instructions, the X block consists of the
64-Kbyte data address space (including all Y addresses).
When ex ecu tin g one o f the MAC class of instructions, the
X block consists of the 64-Kbyte data address space
excluding the Y address block (for data reads only). In
other wor ds, all oth er ins tru ctio ns r egard th e en tir e da ta
memory as one composite address space. The MAC
clas s instructions extract th e Y address space from data
space and addr ess it usin g EAs sour ced fr om W1 0 and
W1 1. The remaining X data space is addressed using W8
and W9. Both address spaces are concurrently accessed
only with the MAC class instructions.
The data space memory map is shown in Figure 3-7.
FIGURE 3-7: dsPIC30F3014/dsPIC30F4013 DATA SPACE MEMORY MAP
0x0000
0x07FE
0x0BFE
0xFFFE
LSB
Address
16 bits
LSBMSB
MSB
Address
0x0001
0x07FF
0x0BFF
0xFFFF
0x8001 0x8000
Optionally
Mapped
into Program
Memory
0x0FFF 0x0FFE
0x10000x1001
0x0801 0x0800
0x0C01
0x0C00
Near
Data
0x1FFE 0x1 FFF
2 Kbyte
SFR Space
2 Kbyte
SRAM Space
8 Kbyte
Space
X Data
Unimplemented (X)
SFR Space
X Data RAM (X)
Y Data RAM (Y)
2010 Microchip Technology Inc. DS70138G-page 31
dsPIC30F3014/4013
FIGURE 3-8: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE
SFR SPACE
(Y SPACE)
X SPACE
SFR SPACE
UNUSED
X SPACE
X SPACE
Y SPACE
UNUSED
UNUSED
Non-MAC Class Ops (Read/Write) MAC Class Op s ( Re ad )
Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11
MAC Class Ops (Write)
dsPIC30F3014/4013
DS70138G-page 32 2010 Microchip Technology Inc.
3.2.2 DATA SPACES
The X data space is used by all instructions and sup-
ports all addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X dat a sp ace also su pports Modulo Address ing for
all instructions, subject to addressing mode restric-
tions. Bit-Reversed Addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur ac ros s t he Y bu s. T his cl as s of instructio ns ded i-
cates two W regi ster pointers, W10 and W1 1, to alw ays
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write-back, the data
address space is consi dere d a c om bin ati on of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports Modulo Addressing for
automat ed c irc ul ar bu f fe r s. Of c ours e, all othe r ins tru c-
tions ca n access the Y dat a address sp ace thro ugh the
X data path as part of the composite linear spac e.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-7 and is not user-
pro gramma ble. Shou ld an EA poi nt to data outs ide its
own assigned address space, or to a location outside
physic al mem ory, an all zero word/by te is r eturne d. For
example, although Y address space is visible by all
non-MAC instructions using any addressing mode, an
attempt by a MAC instruction to fetch data from that
space using W8 or W9 (X Space Pointers) returns
0x0000.
TABLE 3-2: EFFECT OF INVALID
MEMORY ACCESSES
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
3.2.3 DATA SPACE WIDTH
The core data width is 16 bits. All internal registers are
organ ized as 16-bit wide words. Data space mem ory is
organized in byte addressable, 16-bit wide blocks.
3.2.4 DATA ALI GNMENT
To help maintain backward compatibility with PIC®
MCU devices and improve data space memory usage
efficiency, the dsPIC30F instruction set supports both
word and byte operation s. Data is al igned in dat a mem-
ory and registers as words, but all data space EAs
resolve to bytes. Data byte reads read the complete
word whic h co ntains the byt e, us ing the L Sb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
acces ses are possible fro m the Y data pa th as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
As a conse quence of this byte access ibility, all ef fective
address calc ul atio ns (in cl udi ng tho se ge nerated by th e
DSP operations which are restricted to word-sized
data) a re internally scale d to step through word-aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
All word accesses must be al igned to an even a ddress.
Misaligned word data fetches are not supported so
care must be taken when mixing byte and word
operatio ns, or transla ting from 8-bit MC U code. Should
a misaligned read or write be attempted, an address
error trap is generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then exe-
cuted, allowing the system and/or user to examine the
machine state prior to execution of the address Fault.
FIGURE 3-9: DATA ALIGNMENT
Attempted Operation Data Returned
EA = an unimplemented address 0x0000
W8 or W9 used to access Y data
spa ce in a MAC instruction 0x0000
W10 or W11 used to access X
data space in a MAC instruction 0x0000
15 8 7 0
0001
0003
0005
0000
0002
0004
Byte 1 Byte 0
Byte 3 Byte 2
Byte 5 Byte 4
LSBMSB
2010 Microchip Technology Inc. DS70138G-page 33
dsPIC30F3014/4013
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A Sign-Extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
Although m os t i ns truc tio ns a r e ca p ab le of operating o n
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words .
3.2.5 NEAR DATA SPACE
An 8-Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly add res sab le via a 13-bit absolute address fiel d
within all memory direct instructions. The remaining X
address space and all of the Y address space is
address able indirec tly. Additional ly, the whole of X da ta
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
3.2.6 SOFTWARE STACK
The dsPIC DSC dev ices cont ain a s oftw are sta ck. W15
is used as the Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
and post-increments for stack pushes as shown in
Figure 3-10. Note that for a PC push during any CALL
instruc tio n, the M SB o f t he PC i s ze ro-ex te nde d b efo re
the push, ensuring that the MSB is always clear.
There is a Stack Point er Limit regi ster (SPLIM) associ-
ated with the Stack Pointer. SPLIM is uninitialized at
Reset. As is t he case f or t h e Stack Point er, SPL IM < 0>
is forced to ‘0’ because all stack operations must be
word-aligned. Whenever an Effective Address (EA) is
generated, using W15 as a source or destination
pointer, the address thus generated is compared with
the valu e i n SPL IM. If the cont ents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a stack error trap does not
occur. The stack error trap occurs on a subsequent
push operation. Thus, for example, if it is desirable to
cause a stack error trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.
Similarl y, a S t ack Po inter u nderf low ( stack error) tra p is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should no t be immediately
follow ed by an ind irec t read ope rati on usi ng W15.
FIGURE 3-10: CALL STACK FRAME
Note: A PC push during exception processing
concat enates the SRL regi ster to the MSB
of the PC prior to the push.
<Free Word>
PC<15:0>
000000000
015
W15 (before CALL)
W15 (after CALL)
Stack Grows Towards
Higher Address
0x0000
PC<22:16>
POP : [--W15]
PUSH : [W15++]
dsPIC30F3014/4013
DS70138G-page 34 2010 Microchip Technology Inc.
TABLE 3-3: CORE REGIS TER MAP (1)
SFR Name Address
(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
W0 0000 W0/WREG 0000 0000 0000 0000
W1 0002 W1 0000 0000 0000 0000
W2 0004 W2 0000 0000 0000 0000
W3 0006 W3 0000 0000 0000 0000
W4 0008 W4 0000 0000 0000 0000
W5 000A W5 0000 0000 0000 0000
W6 000C W6 0000 0000 0000 0000
W7 000E W7 0000 0000 0000 0000
W8 0010 W8 0000 0000 0000 0000
W9 0012 W9 0000 0000 0000 0000
W10 0014 W10 0000 0000 0000 0000
W11 0016 W11 0000 0000 0000 0000
W12 0018 W12 0000 0000 0000 0000
W13 001A W13 0000 0000 0000 0000
W14 001C W14 0000 0000 0000 0000
W15 001E W15 0000 1000 0000 0000
SPLIM 0020 SPLIM 0000 0000 0000 0000
ACCAL 0022 ACCAL 0000 0000 0000 0000
ACCAH 0024 ACCAH 0000 0000 0000 0000
ACCAU 0026 Sign Extension (ACCA<39>) ACCAU 0000 0000 0000 0000
ACCBL 0028 ACCBL 0000 0000 0000 0000
ACCBH 002A ACCBH 0000 0000 0000 0000
ACCBU 002C Sign Extension (ACCB<39>) ACCBU 0000 0000 0000 0000
PCL 002E PCL 0000 0000 0000 0000
PCH 0030 — — — — — — — — —PCH0000 0000 0000 0000
TBLPAG 0032 — — — — — — — —TBLPAG0000 0000 0000 0000
PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000
RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu
DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu
DOSTARTL 003A DOSTARTL 0uuuu uuuu uuuu uuu0
DOSTARTH 003C — — — — — — — — —DOSTARTH0000 0000 0uuu uuuu
DOENDL 003E DOENDL 0uuuu uuuu uuuu uuu0
DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2010 Microchip Technology Inc. DS70138G-page 35
dsPIC30F3014/4013
CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000
MODCON 0046 XMODEN YMODEN —— BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000
XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0
XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1
YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0
YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1
XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu
DISICNT 0052 —— DISICNT<13:0> 0000 0000 0000 0000
TABLE 3-3: CORE REGIS TER MAP (1) (CONTINUED)
SFR Name Address
(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 36 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 37
dsPIC30F3014/4013
4.0 ADDRESS GENERATOR UNITS
The dsPIC DSC core contains two independent
address generator un its: the X AGU and Y AGU. The Y
AGU supports word-sized data reads for the DSP MAC
class of instructions only. The dsPIC DSC AGUs
support three types of data addressing:
• Linear Addressing
• Modulo (Circular) Addressing
• Bit-Revers ed Addre ss in g
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressi ng is on ly appli cable to data s pace a ddres ses.
4.1 I nstruction Addressing Modes
The addressing modes in Table 4-1 form the basis of
the address ing modes o ptimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
4.1.1 FILE REGISTER INSTRUCTIONS
Most fil e re gis ter i ns truc tio ns use a 13-bit ad dres s f iel d
(f) to directly address data present in the first
8192 bytes of data memory (near dat a space). Most file
register instructions employ a working register, W0,
whic h is den oted as WREG in these i nstruc tions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which w rites the re sult t o a re gister or regi ster pair. The
MOV instruction allows additional flexibility and can
access the entire data space during file register
operation.
4.1.2 MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where O pe rand 1 is alw a ys a work in g reg ister (i.e., the
address ing mode can only be Reg ister Direct), whi ch is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory or a 5-bit literal. The result
location can be either a W register or an address
location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s Reference Manual”
(DS70157).
Note: Not all instructions support all the
address ing modes g iven abov e. Individu al
inst ruc tion s m ay su ppo rt di f f e rent subset s
of these addressing modes.
Addressing Mode Description
File Register Direct The address of the File register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn forms the EA.
Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Registe r Indire ct Pr e- M odi fie d W n is pr e-modified (increm en ted or de cre me nted ) by a si gne d con stant valu e
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
dsPIC30F3014/4013
DS70138G-page 38 2010 Microchip Technology Inc.
4.1.3 MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instruc-
tions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
In summary, the following addressing modes are
supported by move and accumulator instructions:
• Register Direc t
• Register Indi rec t
• Register Indi rec t Post-Mod ifi ed
• Register Indirect Pre-Modif ied
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
4.1.4 MAC INSTRUCTIONS
The dual s ource op erand DSP ins tructio ns (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), als o
referred to a s MAC instruction s, utilize a si mplified se t of
addressing modes to allow the user to effectively
manipulate the Data Pointers through register indirect
tables.
The two source operand prefetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 is always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The Effective Addresses generated (before and after
modification) must, therefore, be valid addresses within
X dat a sp ace f or W8 and W9 and Y data space for W10
and W11.
In summary, the following addressing modes are
supported by the MAC class of instructions:
• Register Indirect
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)
4.1.5 OTHER INSTRUCTIONS
Besides the various addressing modes outlined ab ove,
some i nstructio ns use li teral con sta nts of various sizes.
For example, BRA (branch) instructions use 16-bit
signed l iterals to spe cify the branch de stination dire ctly ,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opc ode
itse lf. Cert ain opera tions, such as NOP, do not have any
operands.
4.2 Modulo Addressing
Modulo Addressing is a method of providing an
automat ed means to support ci rcular dat a buf fers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or
program space (since the data pointer mechanism is
essentially the same for both). One circul ar buffer can
be support ed in e ach o f the X ( which also provide s th e
pointers into program space) and Y data spaces.
Modulo Addressing can operate on any W register
pointer . However , it is not advisable to use W14 or W15
for Modulo Addressing since these two registers are
used as the Stack Frame Pointer and Stack Pointer,
respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are
certain restrictions on the buffer s tart address (for incre-
menting buffers), or end address (for decrementing
buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirecti onal mode (i.e., addres s boundar y
checks are performed on both the lower and upper
address boundaries).
Note: For the MOV instructions, the addressing
mode spe cified in the ins truction can dif fer
for the source and destination EA.
However, the 4-bit Wb (register offset)
field is shared between both source and
destination (but typically only used by
one).
Note: Not all instructions support all the
addressing modes given above. Individual
inst ruc tio ns m ay su ppo rt diffe rent subsets
of these addressing modes.
Note: Register Indirect with Register Offset
addressing is only available for W9 (in X
spa ce) and W11 (in Y space).
2010 Microchip Technology Inc. DS70138G-page 39
dsPIC30F3014/4013
4.2.1 START AND END ADDRESS
The Modulo Addressing scheme requires that a start-
ing and an ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-3).
The leng th of a ci rcular buffer is not di rectly s pecified. It
is determined by the difference between the
corresp onding st art and end ad dress es. Th e ma ximu m
possible length of the circular buffer is 32K words
(64 Kbytes).
4.2.2 W ADDRESS REGISTER
SELECTION
The Mod ulo an d Bi t-Rev ers ed Add ress in g Control reg-
ister M O DCON <1 5:0 > c on t ai ns enable fla gs as w ell a s
a W register field to specify the W address registers.
The XWM and YWM fields se lect whic h registe rs oper-
ate with Modulo Addressing. If XWM = 15, X RAGU
and X WAGU Modulo Ad dressing is disab led. Simi larly,
if YWM = 15, Y AGU Modulo Addressing is disabled.
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 3-3). Modul o A ddress ing is
enabled for X data sp ace when XWM is set to any v alue
other than ‘15’ and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON<14>.
FIGURE 4 -1: MODULO ADDRESSING OPERATION EXAMPLE
Note: Y space Modulo Addressing EA calcula-
tions assume word-sized data (LSb of
ever y EA is always clear ).
0x0800
0x0863
Start Addr = 0x0800
End Addr = 0x0863
Length = 0x00 32 w ords
Byte
Address MOV #0x800,W0
MOV W0,XMODSRT ;set modulo start address
MOV #0x863,W0
MOV W0,MODEND ;set modulo end address
MOV #0x8001,W0
MOV W0,MODCON ;enable W1, X AGU for modulo
MOV #0x0000,W0 ;W0 holds buffer fill value
MOV #0x800,W1 ;point W1 to buffer
DO AGAIN,#0x31 ;fill the 50 buffer locations
MOV W0,[W1++] ;fill the next location
AGAIN: INC W0,W0 ;increment the fill value
dsPIC30F3014/4013
DS70138G-page 40 2010 Microchip Technology Inc.
4.2.3 MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. It is important to realize that the address
boundaries check for addresses less than or greater
than the uppe r (for incre menting buf fe rs) and lower (for
decrementing buffers) boundary addresses (not just
equal to). Address changes may, therefore, jump
beyond boundaries and still be adj us ted correctly.
4.3 Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by t he X AGU for data writes only.
The m odifier, which ma y be a c onstant value or reg ister
contents, is regarded as having it s bit order reversed. The
address source and destination are kept in normal order .
Thus, the only operand requiring reversal is the modifier .
4.3. 1 BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
1. BWM (W register selection) in the MODCON
register is any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing) and
2. the BREN bit is set in the XBREV register and
3. the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
If the length of a bit-reversed buffer is M = 2N bytes,
then the last ‘N’ bits of the data buffer start address
must be zero s.
XB<14:0> is th e b it-re versed addres s mo difi er or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
dat a buffer size.
When enabled, Bit-Reversed Addressing is only
executed for Register Indirect with Pre-Increment or
Post-Increment Addressing and word-sized data
writes. It does not function for any other addressing
mode or for byte sized data. Normal addresses are
generated instead. When Bit-Reversed Addressing is
active, the W Address Pointer is always added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the Bit-Reversed Pointer.
FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE
Note: The mo dulo correc ted effe ctive addre ss is
written back to the regis ter only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (e.g., [W7+W2])
is used, Modulo Addressing correction is
performed but the contents of the register
remain unc han ged.
Note: All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note: Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. In the event that the user
attempts to do this, Bit-Reversed Address-
ing assumes priority when active for the X
WAGU, and X WAGU Modulo Addressing
is disabled. However, Modulo Addressing
continues to function in the X RAGU.
b3 b2 b1 0
b2 b3 b4 0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
Bit-Reversed Address
XB = 0x0008 for a 16-word Bit-Reversed Buffer
b7 b6 b5 b1
b7 b6 b5 b4b11 b10 b9 b8
b11 b10 b9 b8
b15 b14 b13 b12
b15 b14 b13 b12
Sequential Address
Pivot Point
2010 Microchip Technology Inc. DS70138G-page 41
dsPIC30F3014/4013
TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER
Normal Address Bit-Reversed Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0000 00000 0
0001 11000 8
0010 20100 4
0011 31100 12
0100 40010 2
0101 51010 10
0110 60110 6
0111 71110 14
1000 80001 1
1001 91001 9
1010 10 0101 5
1011 11 1101 13
1100 12 0011 3
1101 13 1011 11
1110 14 0111 7
1111 15 1111 15
Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value
1024 0x0200
512 0x0100
256 0x0080
128 0x0040
64 0x0020
32 0x0010
16 0x0008
80x0004
40x0002
20x0001
dsPIC30F3014/4013
DS70138G-page 42 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 43
dsPIC30F3014/4013
5.0 FLASH PROGRAM MEMORY
The dsPIC30F family of devices contains internal
program Flash memory for executing user code. There
are two methods by which the user can program this
memory:
1. Run-Time Self-Programming (RTSP)
2. In-Circuit Serial Programming™ (ICSP™)
5.1 I n-Circuit Serial Programming
(ICSP)
dsPIC30F devices can be serially programme d while i n
the end ap plica tion circu it. This is s imply done wit h two
lines for Programming Clock and Programming Data
(which are named PGC and PGD, respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Cl ear (MCLR). This allows customers to manu-
facture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
5.2 Run-Time Self-Programming
(RTSP)
RTSP is accomplished using TBLRD (table read) and
TBLWT (table wr ite) ins tru cti ons .
With RTSP, the user may erase program memory,
32 instructions (96 bytes) at a time and can write
program memory data, 32 instructions (96 bytes) at a
time.
5.3 Table Instruction Operation
Summary
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
Word or Byte mode.
The TBLRDH and TBLWTH i nstructio ns are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can access program memory in Word or
Byte mode.
A 24-bit program memory address is formed using
bits<7:0> of the TBLPAG register and the Effective
Address (EA) from a W register specified in the table
instruction, as sh own i n Figure 5-1.
FIGURE 5-1: ADDRESSING FOR TABLE AND NVM REGISTERS
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s Reference Manual”
(DS70157).
0
Program Counter
24 bits
NVMADRU Reg
8 bits 16 bits
Program
Using
TBLPAG Reg
8 bits
Working Reg EA
16 bits
Using
Byte
24-bit EA
1/0
0
1/0
Select
Table
Instruction
NVMADR
Addressing
Counter
Using
NVMADR Reg EA
User/Configuration
Space Select
dsPIC30F3014/4013
DS70138G-page 44 2010 Microchip Technology Inc.
5.4 RTSP Operati on
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions or 96 bytes. Each panel consists of 128 rows or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program four
instructions at one time. RTSP may be used to program
multipl e program me mory p anels, but th e Table Pointer
must be changed at each panel boundary.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, in str u cti on 1,
etc. T he i ns truc tio n words loaded m us t a lway s b e fro m
a 32 address boundary.
The basi c sequence for R TSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load th e wri te latc hes. Prog ramming is perfo rmed b y
setting the special bits in the NVMCON register.
32 TBLWTL and four TBLWTH instructions are
required to load the 32 instructions. If multiple panel
programm ing is re quired, th e Table Poin ter needs to be
changed and the next set of multiple write latches
written.
All of the table write operations are single-word writes
(2 instruction cycles), because only the table latches
are written. A programming cycle is required for
programming each row.
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
5.5 Control Registers
The four SFRs used to read and write the program
Flash memory are:
•NVMCON
• NVMADR
• NVMADRU
• NVMKEY
5.5.1 NVMCON REGISTER
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed and
the start of the programming cycle.
5.5.2 NVMADR REGISTER
The NVMADR register is used to hold the lower two
bytes of the Effective Address. The NVMADR register
captures the EA<15 :0> of the last table instru ct ion that
has been executed and selects the row to write.
5.5.3 NVMADRU REGISTER
The NVMADRU register is used to hold the upper byte
of the Effective Address. The NVMADRU register cap-
tures the EA<23:16> of the last table instruction that
has been exec uted.
5.5. 4 NVMKEY REGISTER
NVMKEY is a wr ite- on ly r egist er th at is u sed for w r ite
protection. To start a programming or erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 5.6
“Programming Operations” for fu rthe r de tails .
Note: The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
2010 Microchip Technology Inc. DS70138G-page 45
dsPIC30F3014/4013
5.6 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A progra mming operati on is nominally 2 ms ec in
duration and the processor stalls (waits) until the oper-
ation is finished. Setting the WR bit (NVMCON<15>)
starts the operation and the WR bit is automatically
cleared when the operation is finished.
5.6.1 PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
The user can erase or program one row of program
Flash memory at a time. The general process is:
1. Read one row of program Flash (32 instruction
words) and store into data RAM as a data
“image”.
2. Update the data image with the desired new
data.
3. Erase program Flash row.
a) Set up NVMCON register for multi-word,
program Flash, erase, and set WREN bit.
b) Write address of row to be erased into
NVMADRU/NVMDR.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit. This begins erase cycle.
f) CPU stalls for the duration of the erase cycle.
g) The WR bit is cleared when erase cycle
ends.
4. Write 32 instruction words of data from data
RAM “image” into the program Flash write
latches.
5. Program 32 instruction words into program
Flash.
a) Set up NVMCON register for multi-word,
program Flash, program, and set WREN
bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. This begins program cycle.
e) CPU stalls for duration of the program cycle.
f) The WR bit is cleared by the hardware
when program cycle ends.
6. Repeat step s 1 through 5 as needed to program
desired amount of program Flash memory.
5.6.2 ERASING A ROW OF PROGRAM
MEMORY
Example 5-1 shows a code sequence that can be used
to erase a row (32 instructions) of program memory.
EXAMPLE 5-1: ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word write
; program memory selected, and writes enabled
MOV #0x4041,W0 ;
MOV W0,NVMCON ; Init NVMCON SFR
; Init pointer to row to be ERASED
MOV #tblpage(PROG_ADDR),W0 ;
MOV W0,NVMADRU ; Initialize PM Page Boundary SFR
MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer
MOV W0, NVMADR ; Initialize NVMADR SFR
DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted
dsPIC30F3014/4013
DS70138G-page 46 2010 Microchip Technology Inc.
5.6.3 LOADING WRITE LATCHES
Example 5-2 shows a sequence of instructions that
can be used to load the 96 bytes of write latches.
32 TBLWTL and 32 TBLWTH instructions are needed to
load the w rite latches selected by the Tabl e Pointer.
5.6.4 INITIATING THE PROGRAMMING
SEQUENCE
For pr otection, the w rite in itiate sequ ence f or NVMKEY
must be used to allow any erase or program operation
to proceed . Afte r the programmin g comman d has been
executed, the user must wait for the programming time
until programming is complete. The two instructions
following the start of the programming sequence
should be NOPs as shown in Example 5-3.
EXAMPL E 5- 2: LOA D ING WR ITE LATC HES
EXAMPLE 5-3: INITIATIN G A PROGRAM MING SEQUENCE
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV #0x0000,W0 ;
MOV W0,TBLPAG ; Initialize PM Page Boundary SFR
MOV #0x6000,W0 ; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV #LOW_WORD_0,W2 ;
MOV #HIGH_BYTE_0,W3 ;
TBLWTL W2,[W0] ; Write PM low word into program latch
TBLWTH W3,[W0++] ; Write PM high byte into program latch
; 1st_program_word
MOV #LOW_WORD_1,W2 ;
MOV #HIGH_BYTE_1,W3 ;
TBLWTL W2,[W0] ; Write PM low word into program latch
TBLWTH W3,[W0++] ; Write PM high byte into program latch
; 2nd_program_word
MOV #LOW_WORD_2,W2 ;
MOV #HIGH_BYTE_2,W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
•
•
•
; 31st_program_word
MOV #LOW_WORD_31,W2 ;
MOV #HIGH_BYTE_31,W3 ;
TBLWTL W2, [W0] ; Write PM low word into program latch
TBLWTH W3, [W0++] ; Write PM high byte into program latch
Note: In Example 5-2, the contents of the upper byte of W3 has no effect.
DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Start the erase sequence
NOP ; Insert two NOPs after the erase
NOP ; command is asserted
2010 Microchip Technology Inc. DS70138G-page 47
dsPIC30F3014/4013
TABLE 5-1: NVM REGISTER MAP(1)
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets
NVMCON 0760 WR WREN WRERR — — — —TWRI — PROGOP<6:0> 0000 0000 0000 0000
NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu
NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu
NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 48 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 49
dsPIC30F3014/4013
6.0 DATA EEPROM MEMORY
The data EEPROM memory is readable and writable
during no rmal operatio n over the enti re VDD range. The
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory as wel l. As descri bed in Section 5.5 “Control
Registers”, these registers are:
•NVMCON
• NVMADR
• NVMADRU
• NVMKEY
The EEPR OM data memory allows read and writ e of
single words and 16-word blocks. When interfacing to
data memory, NVMADR, in conjunction with the
NVMADRU register, are used to address the
EEPROM location being accessed. TBLRDL and
TBLWTL instructions are used to read and write data
EEPROM. The dsPIC30F devices have up to 8 Kbytes
(4K words) of data EEPROM with an address range
from 0x7FF000 to 0x7FFFFE .
A word wri te operatio n should be prec eded by an e rase
of the corresponding memory location(s). The write
typically requires 2 ms to complete, but the write time
varies with voltage and tempe r atur e.
A program or erase operation on the data EEPROM
does n ot sto p the ins truc tion fl ow. The us er is r espon -
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
Control bit, WR, initiates write operations similar to
prog ram Fl ash wri tes. This bi t canno t be clea red, only
set, in software. They are cleared in hardware at the
completion of the write operation. The inability to clear
the WR bit in software prevents the accidental or
premature termination of a write operation.
The W RE N bi t , w h en s et , al low s a wr ite op era t io n. On
power-u p, the WREN bit is cle ar . The WRERR bit is set
when a writ e opera tion i s inte rrupted by a MCLR Reset
or a WDT Time-out Reset during normal operation. In
these situations, following Reset, the user can check
the WRERR bit and rewrite the location. The address
register, NVMADR, remains unchanged.
6.1 Reading the Data EEPROM
A TBLRD instruction reads a word at the current
program word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4 as sho wn in Example 6-1.
EXAMPLE 6-1: DATA EEPROM READ
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s Reference Manual”
(DS70157).
Note: Interru pt flag bit, NVMIF in the IFS0 regis-
ter, is set when the write is complete. It
must be cleared in software.
MOV #LOW_ADDR_WORD,W0 ; Init Pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
TBLRDL [ W0 ], W4 ; read data EEPROM
dsPIC30F3014/4013
DS70138G-page 50 2010 Microchip Technology Inc.
6.2 Er asing Data EEPROM
6.2.1 ERASING A BLOCK OF DATA
EEPROM
In order to erase a block of data EEPROM, the
NVMADRU and NVMAD R registers must initially point
to the block of memory to be erased. Configure
NVMCON for erasing a block of data EEPROM and
set the WR and WR EN bits in the NVMCON re gister.
Setting the WR bit initiates the erase, as shown in
Example 6-2.
6.2.2 ERASING A WORD OF DATA
EEPROM
The NVMADRU and NVMADR registers must point to
the block. Select a block of data Flash and set the WR
and WREN bits in the NVMCON register. Setting the
WR bit initiates the erase, as shown in Example 6-3.
EXAMPLE 6-2: DATA EEPROM BLOCK ERASE
EXAMPLE 6-3: DATA EEPROM WORD ERASE
; Select data EEPROM block, WR, WREN bits
MOV #4045,W0
MOV W0,NVMCON ; Initialize NVMCON SFR
; Start erase cycle by setting WR after writing key sequence
DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
; Select data EEPROM word, WR, WREN bits
MOV #4044,W0
MOV W0,NVMCON
; Start erase cycle by setting WR after writing key sequence
DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0 ;
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1 ;
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
2010 Microchip Technology Inc. DS70138G-page 51
dsPIC30F3014/4013
6.3 Writing to the Data EEPROM
To write an EEPROM data location, the following
sequen ce must be followed :
1. Erase the data EEPROM word.
a) Select the word, data EEPROM erase and
set the WREN bit in the NVMCON register.
b) Write the address of word to be erased into
NVMADR.
c) Enable the NVM interrupt (optional).
d) Write 0x55 to NVMKEY.
e) Write 0xAA to NVMKEY.
f) Set the WR bit. This beg ins the erase cycl e.
g) Either poll the NVMIF bit or wait for the
NVMIF interrupt.
h) The W R bit is cleare d whe n the era se cy cle
ends.
2. Write the d ata word into dat a the EEPROM write
latches.
3. Program 1 data word into the data EEPROM.
a) Select the word, data EEPROM program and
set th e WREN bi t i n t he N VM CO N register.
b) Enable the NVM write done interrupt
(optional).
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit. This begins the program
cycle.
f) Either poll the NVMIF bit or wait for the
NVM interrupt.
g) The WR bit is cleared when the write cycle
ends.
The write doe s not initiate if the above sequen ce is n ot
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution. The WREN bit should be kept clear at all times
except when updating the EEPROM. The WREN bit is
not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit does not affect the current write cycle. The
WR bit is inhibited from bei ng s et un le ss the WREN b it
is set. The WREN bit must be set o n a previous instruc -
tion. Both WR a nd WREN c an not be se t w ith th e s ame
instruction.
At the completion of the write cycle, the WR bit is
cleared in ha rdware and the No nv ola til e M em ory Write
Complete Interrupt Flag bit (NVMIF) is set. The user
may either enable this interrupt or poll this bit. NVMIF
must be cleared by software.
6.3.1 WRITING A WORD OF DATA
EEPROM
Once the user has erased the word to be programme d,
then a table write instruction is used to write one write
latch, as shown in Example 6-4.
6.3. 2 WRITING A BLOCK OF DATA
EEPROM
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block, as shown in Example 6-5.
EXAMPLE 6-4: DATA EEPROM WORD WRITE
; Point to data memory
MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
MOV #LOW(WORD),W2 ; Get data
TBLWTL W2,[ W0] ; Write data
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV #0x4004,W0
MOV W0,NVMCON
; Operate key to allow write operation
DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Initiate program sequence
NOP
NOP
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
dsPIC30F3014/4013
DS70138G-page 52 2010 Microchip Technology Inc.
EXAMPLE 6-5: DATA EEPROM BLOCK WRITE
6.4 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.5 Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared;
also, the Power-up Timer prevents EEPROM write.
The write initiate sequence, and the WREN bit
together, help prevent an accidental write during
brown-out, power glitch or software malfunction.
MOV #LOW_ADDR_WORD,W0 ; Init pointer
MOV #HIGH_ADDR_WORD,W1
MOV W1,TBLPAG
MOV #data1,W2 ; Get 1st data
TBLWTL W2,[ W0]++ ; write data
MOV #data2,W2 ; Get 2nd data
TBLWTL W2,[ W0]++ ; write data
MOV #data3,W2 ; Get 3rd data
TBLWTL W2,[ W0]++ ; write data
MOV #data4,W2 ; Get 4th data
TBLWTL W2,[ W0]++ ; write data
MOV #data5,W2 ; Get 5th data
TBLWTL W2,[ W0]++ ; write data
MOV #data6,W2 ; Get 6th data
TBLWTL W2,[ W0]++ ; write data
MOV #data7,W2 ; Get 7th data
TBLWTL W2,[ W0]++ ; write data
MOV #data8,W2 ; Get 8th data
TBLWTL W2,[ W0]++ ; write data
MOV #data9,W2 ; Get 9th data
TBLWTL W2,[ W0]++ ; write data
MOV #data10,W2 ; Get 10th data
TBLWTL W2,[ W0]++ ; write data
MOV #data11,W2 ; Get 11th data
TBLWTL W2,[ W0]++ ; write data
MOV #data12,W2 ; Get 12th data
TBLWTL W2,[ W0]++ ; write data
MOV #data13,W2 ; Get 13th data
TBLWTL W2,[ W0]++ ; write data
MOV #data14,W2 ; Get 14th data
TBLWTL W2,[ W0]++ ; write data
MOV #data15,W2 ; Get 15th data
TBLWTL W2,[ W0]++ ; write data
MOV #data16,W2 ; Get 16th data
TBLWTL W2,[ W0]++ ; write data. The NVMADR captures last table access address.
MOV #0x400A,W0 ; Select data EEPROM for multi word op
MOV W0,NVMCON ; Operate Key to allow program operation
DISI #5 ; Block all interrupts with priority <7 for
; next 5 instructions
MOV #0x55,W0
MOV W0,NVMKEY ; Write the 0x55 key
MOV #0xAA,W1
MOV W1,NVMKEY ; Write the 0xAA key
BSET NVMCON,#WR ; Start write cycle
NOP
NOP
2010 Microchip Technology Inc. DS70138G-page 53
dsPIC30F3014/4013
7.0 I/O PORTS
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
7.1 Parallel I/O (PIO) Ports
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is dis abled . If a p eriphe ral is enabl ed but the p eriphera l
is not actively driving a pin, that pin can be driven by a
port.
All port pins have three registers directly associated
with the operation of the port pin. The Data Direction
register (TRISx ) determ ines whe ther the pin is an inp ut
or an output. If the data direction bit is a ‘1’, t hen the pin
is an input. All port pins are defined as inputs after a
Reset.
Reads from the latch (LATx), read the latch. Writes to
the latch, write the latch (LATx). Reads from the port
(PORTx ), read th e port pi ns and writes to the port p ins,
write the latch (LATx).
Any bit and its associated data and control registers
that are not valid for a particular device are disabled,
which means the corresponding LATx and TRISx
registers and the port pin read as zeros.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
A Parallel I/O (PIO) port that shares a pin with a periph-
eral is, in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has own ership of the outp ut dat a and co ntrol si gn als of
the I/O pad cell. Figure 7-2 shows how ports are shared
with oth er perip herals and the a ssociat ed I/O c ell (p ad)
to which they are connected. Table 7-1 shows the
formats of the registers for the shared ports, PORTB
through PORTF.
FIGURE 7-1: BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Note: The actual bits in use vary between
devices.
QD
CK
WR LAT +
TRIS Latch
I/O Pad
WR PORT
Data Bus
QD
CK
Data Latch
Read LAT
Read PORT
Read TRIS
WR TRIS
I/O Cell
Dedicated Port Module
dsPIC30F3014/4013
DS70138G-page 54 2010 Microchip Technology Inc.
FIGURE 7-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
7.2 Configuring Analog Port Pins
The use of the ADPC FG and TRIS registers control th e
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) is
converted.
When the PORT re gi ste r is rea d, all pi ns co nfi gure d a s
analog input channels are read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog i nput. Analog leve ls on any pin that is defined as
a dig ital inp ut (incl uding t he ANx p ins) ma y cause the
input buffer to consume current that exceeds the
device specifications.
7.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
EXAMPLE 7- 1: PO RT WRITE/R EAD
EXAMPLE
QD
CK
WR LAT +
TRIS Latch
I/O Pad
WR PORT
Data Bus
QD
CK
Data Latch
Read LAT
Read P ORT
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output Data
Peripheral Input Data
I/O Cell
Peripheral Module
Peripheral Output Enable
PIO Module
Output Multiplexers
Input Data
Peripheral Module Enable
Output Enable
Output Data
MOV 0xFF00, W0 ; C onfigu re PORT B<15:8>
; as inputs
MOV W0, TRISB ; and PORTB<7:0 > as ou tputs
NOP ; addition al inst ruction
cycle
BTSS PO RTB, #11 ; bit test RB11 and sk ip if set
2010 Microchip Technology Inc. DS70138G-page 55
dsPIC30F3014/4013
TABLE 7-1: dsPIC30F3014/4013 PORT REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
TRISA 02C0 ———— TRISA11 — — — — — — — — — — — 0000 1000 0000 0000
PORTA 02C2 ————RA11— — — — — — — — — — — 0000 0000 0000 0000
LATA 02C4 ————LATA11— — — — — — — — — — — 0000 0000 0000 0000
TRISB 02C6 ——— TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0001 1111 1111 1111
PORTB 02C8 ——— RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000
LATB 02CB ——— LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000
TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — — — — — 1110 0000 0000 0000
PORTC 02CE RC15 RC14 RC13 — — — — — — — — — — — — — 0000 0000 0000 0000
LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — — — — — 0000 0000 0000 0000
TRISD 02D2 —————— TRISD9 TRISD8 ———— TRISD3 TRISD2 TRISD1 TRISD0 0000 0011 0000 1111
PORTD 02D4 —————— RD9 RD8 ———— RD3 RD2 RD1 RD0 0000 0000 0000 0000
LATD 02D6 ——————LATD9LATD8———— LATD3 LATD2 LATD1 LATD0 0000 0000 0000 0000
TRISF 02DE — — — — — — — — — TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0000 0111 1111
PORTF 02E0 — — — — — — — — — RF6RF5RF4RF3RF2RF1RF00000 0000 0000 0000
LATF 02E2 — — — — — — — — — LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 56 2010 Microchip Technology Inc.
7.3 I nput Change Notification Module
The input change notification module provides the
dsPIC30F devices the ability to generate interrupt
request s to the processor, in response to a Ch ange-Of-
State (COS) on selected input pins. This module is
capable of detecting input Change-Of-States, even in
Sleep mode, when the clocks are disabled. There are
up to 10 exte rnal signals (CN 0 through CN9, CN17 an d
CN18) that may be selected (enabled) for generating
an interrupt request on a Change-Of-State.
2010 Microchip Technology Inc. DS70138G-page 57
dsPIC30F3014/4013
TABLE 7-2: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F3014/4013 DEVICES (BITS 15-0)(1)
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
CNEN1 00C0 — — — — — — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000
CNEN2 00C2 — — — — — — — — — — — — — CN18IE CN17IE —0000 0000 0000 0000
CNPU1 00C4 — — — — — — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000
CNPU2 00C6 — — — — — — — — — — — — — CN18PUE CN17PUE —0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 58 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 59
dsPIC30F3014/4013
8.0 INTERRUPTS
The dsPIC30F sensor and general purpose families
have up to 41 interrup t sources an d 4 processo r excep-
tions (traps) which must be arbitrated based on a
priority scheme.
The CPU i s respons ible for rea ding the I nterrupt Vector
Table (IVT) and transferring the address contained in
the interrupt vector to the program counter. The inter-
rupt vector is transferred from the program data bus
into the program counter v ia a 24-bit wide multiplexer
on the input of the program counter.
The Inte rrupt Vector Table (IVT) and A lter nate In terrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004). The IVT and AIVT are
shown in Figure 8-1.
The interrupt controller is responsible for pre-
processing the interrupts and processor exceptions
prior to them being presented to the processor core.
The peripheral interrupts and traps are enabled,
prioritized and controlled using centralized Special
Function Registers:
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their respec-
tive peripherals or external signals and they are
cleared via software.
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
• IPC0<15:0>... IPC10<7:0>
The user-as s ign abl e prio rity lev el assoc iate d with
each of these 41 interrupts is held centrally in
these eleven registers.
• IPL<3:0>
The current CPU priority level is explicitly stored
in the IPL bi ts. IPL<3> i s p res en t in the C ORCO N
register, whereas IPL<2:0> are present in the
STATUS register (SR) in the processor core.
• INTCON1< 15:0>, INTCON2<15 :0>
Global interrupt control functions are de rived from
these two registers. INTCON1 contains the con-
trol and status flags for the processor exceptions.
The INTCON2 register controls the external
interrupt request signal behavior and the use of
the alternate vector table.
All interrupt sources can be user-assigned to one of
7 priority levels, 1 through 7, via the IPCx registers.
Each interrupt source is associated with an interrupt
vector, as shown in Table 8-1. Levels 7 and 1 represent
the highest and lowest maskable priorities,
respectively.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prev en ted . Thus, if a n i nte rrupt is curre ntl y
being serviced, processing of a new interrupt is pre-
vented even if the new interrupt is of higher priorit y than
the one currently being serviced.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts, inter-
rupt-on-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program
memory that corresponds to the interrupt. There are
63 different vectors within the IVT (refer to Table 8-1)
These vectors are contained in locations 0x000004
through 0x0000FE of program memory (refer to
Table 8-1). These locations contain 24-bit addresses.
In order to preserve robustness, an address error trap
ta kes place shoul d the PC attempt to fet ch any of these
words during normal execution. This prevents execu-
tion of random data as a result of accidentally
decrementing a PC into vector space, accidentally
mappin g a da t a sp ac e add ress into vect or sp ac e or th e
PC rolling over to 0x000000 after reaching the end of
implemented program memory space. Execution of a
GOTO instruction to this vector space also generates an
address error trap.
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s Reference Manual”
(DS70157).
Note: Interru pt flag bits get set when an interrupt
condition occurs, regardless of th e state of
its corresponding enable bit. User soft-
ware should ensure the appropriate inter-
rupt flag bi t s are cle ar pri or to en ab lin g an
interrupt.
Note: Assigning a priority level of ‘0’ to an inter-
rupt source is equivalent to disabling that
interrupt.
Note: The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
dsPIC30F3014/4013
DS70138G-page 60 2010 Microchip Technology Inc.
8.1 Interrupt Priority
The user-assignable interrupt priority (IP<2:0>) bits for
each individual interrupt source are located in the
3 LSbs of each nibble within the IPCx register(s). Bit 3
of each nibble is not used and is read as a ‘0’. These
bits define the priority level assigned to a particular
interrupt by the user.
Since more than one interrupt request source may be
assigned to a specific user-assigned priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority” and is
final.
Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 8-1 and Table 8-2 list the interrupt numbers,
corresponding interrupt sources and associated vector
numbers for the dsPIC30F3014 and dsPIC30F4013
devices, respectively.
The ability for the user to assign every interrupt to one
of seven pri orit y lev el s means th at the user ca n as sign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (Pro-
gramma ble Lo w-V ol tage De tect) can be given a priorit y
of 7. The INT0 (External Interrupt 0) may be assigned
to priority Level 1, thus giving it a very low effective
priority.
TABLE 8-1: dsPIC30F3014 INTERRUPT
VECTOR TABLE
Note: The us er-ass ignab le priority levels st art at
0 as the lowest priority and Level 7 as the
highest priority.
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The natural order priority number is the
same as the INT number.
INT
Number Vector
Number Interrupt Source
Highest Natural Order Priority
0 8 INT0 – External Interrupt 0
1 9 IC1 – Input Capture 1
2 10 OC 1 – Output Compare 1
3 11 T1 – T imer1
4 12 IC2 – Input Capture 2
5 13 OC 2 – Output Compare 2
6 14 T2 – Ti me r2
7 15 T3 – Ti me r3
8 16 SPI1
9 17 U1RX – UART1 Receiver
10 18 U1TX – UART1 Transmitter
11 19 ADC – ADC Convert Done
12 20 NVM – NVM Write Complete
13 21 SI2C – I2C™ Slave Interrupt
14 22 MI2C – I2C Master Interrupt
15 23 Input Change Interrupt
16 24 INT1 – External Interrupt 1
17-22 25-30 Reserved
23 31 INT2 – External Interrupt 2
24 32 U2RX – UART2 Receiver
25 33 U2TX – UART2 Transmitter
26 34 Reserved
27 35 C1 – Combined IRQ for CAN1
28-41 36-49 Reserved
42 50 LVD – Low-Voltage Detect
43-53 51-61 Reserved
Lowest Natural Order Priority
2010 Microchip Technology Inc. DS70138G-page 61
dsPIC30F3014/4013
TABLE 8-2: dsPIC30F4013 INTERRUPT
VECTOR TABLE 8.2 Reset Sequence
A Reset is not a true exception because the interrupt
controll er is not involv ed in the Reset proce ss. The pro-
cessor initializes its registers in response to a Reset
which forces the PC to zero. The processor then beg ins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory loca-
tion immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the speci fie d address and then be gin s op erat ion at the
specified target (start) address.
8.2.1 RESET SOURCES
In addition to external Reset and Power-on Reset
(POR), these sources of error conditions ‘trap’ to the
Reset vector:
• Watchdog Time-out:
The watchdog has timed out, indicating that the
proce ssor is no lon ger executing the corre ct flow
of code.
• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer causes a Reset.
• Illegal Ins truc tion Tr a p:
Attempted execution of any unused opcodes
results in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
• Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
• Trap Lockout:
Occurrence of multiple trap conditions
simultaneously causes a Reset.
Interrupt
Number Vector
Number Interrupt Source
Highest Natural Order Priority
0 8 INT0 – External Interrupt 0
1 9 IC1 – Input Capture 1
2 10 OC1 – Output Compare 1
311T1 – Timer1
4 12 IC2 – Input Capture 2
5 13 OC2 – Output Compare 2
614T2 V Timer2
715T3 – Timer3
8 16 SPI1
9 17 U1RX – U ART1 Receiver
10 18 U1TX – UART1 Transmitter
11 19 ADC – ADC Convert Done
12 20 NVM – NVM Writ e Complete
13 21 SI2C – I2C™ Slave Interrupt
14 22 MI2C – I2C Master Interrupt
15 23 Input Change Interrupt
16 24 INT1 – External Interrupt 1
17 25 IC7 – Input Capture 7
18 26 IC8 – Input Capture 8
19 27 OC3 – Output Compare 3
20 28 OC4 – Output Compare 4
21 29 T4 – Timer4
22 30 T5 – Timer5
23 31 INT2 – External Interrupt 2
24 32 U2RX – UART2 Receiver
25 33 U2TX – UART2 Transmitter
26 34 Reserved
27 35 C1 – Combined IRQ for CAN1
28-40 36-48 Reserved
41 49 DCI – CODEC Transfer Done
42 50 LVD – Low-V o ltage Detect
43-53 51-61 Reserved
Lowest Natural Order Priority
dsPIC30F3014/4013
DS70138G-page 62 2010 Microchip Technology Inc.
8.3 Traps
Traps can be considered as non-maskable interrupts,
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 8-1. They
are intended to provide the user a means to correct
erroneous o pera t io n d uri ng deb ug and when operating
within the application.
Note that many of these trap conditions can only be
detecte d when th ey occur. Conseque ntly, the questio n-
able instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, w hi ch mea ns that the IPL3 i s alw ay s
set during processing of a trap.
If the us er is not cu rrently exec uting a trap, a nd he s et s
the I PL<3:0> bit s t o a va lue o f ‘0111’ (Lev el 7), then all
inter rupts ar e disabled , but trap s can stil l be proces sed.
8.3.1 TRAP SOURCES
The following traps are provided with increasing prior-
ity. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The math error trap executes under these
circumstances:
1. Should an attempt be made to divide by zero,
the divide operation aborts on a cycle boundary
and the trap is taken .
2. If enabled, a math error trap is taken when an
arithmetic operation on either accumulator A or
B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
3. If enabled, a math error trap is taken when an
arithmetic operation on either accumulator A or
B causes a catastrophic overflow from bit 39 and
all saturation is disabled.
4. If the shift am ou n t sp ec i fie d in a shi ft inst ru ct i on
is greater than the maximum allowed shift
amount, a trap occurs.
Address Error Trap:
This trap is initiated when any of the following
circumstances occ urs:
1. A misaligned data word access is attempted.
2. A data fetch from our unimplemented data
memory location is attempted.
3. A data access of an unimplemented program
memory location is attempted.
4. An instruction fetch from vector space is
attempted.
5. Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruc ti on, whe r e literal
is an un implem ented progra m memo ry addre ss.
6. Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
Stack Error Trap:
This trap is initiated under the following conditions:
1. The Stack Pointer is loaded with a value which
is greater than the (user-programmable) limit
value written into the SPLIM register (stack
overflow).
2. The Stack Pointer is loaded with a value which
is less than 0x0800 (simple stack underflow).
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
8.3.2 HARD AND SOFT TRAPS
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 8-2 is implemented,
whic h may requir e the user t o check if oth er traps are
pending, in order to completely correct the Fault.
‘Soft’ traps include exceptions of priority Level 8
through Level 11, inclusive. The arithmetic error trap
(Level 11) falls into this category of traps.
‘Hard’ traps include exceptions of priority Level 12
through Level 15, inclusive. The address error
(Level 12), stack error (Level 13) and oscillator error
(Level 14) traps fall into this category.
Note: If the user does not intend to take correc-
tive action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
cont aining an inv ali d ad dress is cal led , an
address error trap is generated.
Note: In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
2010 Microchip Technology Inc. DS70138G-page 63
dsPIC30F3014/4013
Each hard trap that occurs must be Acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, Acknowledged, or is being processed,
a hard trap conflict occurs.
The devic e is automatic ally Reset in a ha rd trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs so that the condition may be
detected in software.
FIGURE 8-1: TRAP VECTORS
8.4 Interrupt Sequence
All interr upt event flags are sampled in the beginni ng of
each instruction cycle by the IFSx registers. A pending
Interrupt Request (IRQ) is indicated by the flag bit
being equ al to a ‘1’ in an IFSx reg ister . The IRQ cau ses
an interrupt to occur if the corresponding bit in the Inter-
rupt Enable (IECx ) regis ter is set. For the remaind er of
the instruction cycle, the priorities of all pending
interrupt requests are eva lu ated .
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor is interrupted.
The proce ssor then stac ks the curren t program counter
and the low byte of the processor STATUS register
(SRL), as shown in Figure 8-2. The low byte of the
ST ATUS register contai ns the processor priority level at
the time prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this
interrupt i nto t he STATUS register. This action di sables
all lower priority interrupts until the completion of the
Interrupt Service Routine.
FI G U RE 8 -2 : INTERRUPT STACK FRAME
The RETFIE (return from interrupt ) instruction unstacks
the program counter and STATUS registers to return
the processor to its state prior to the interrupt
sequence.
Address Error Trap Vector
Oscillator Fail Trap Vector
Stack Error Trap Vector
Reserv ed Vector
Math Error Trap Vector
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Reser ved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
Math Error Trap Vector
Decreasing
Priority
0x000000
0x000014
Reserved
Stack Error Trap Vector
Reser ved Vector
Interrupt 1 Vector
—
—
Interrupt 52 Vector
Interrupt 53 Vector
IVT
AIVT
0x000080
0x00007E
0x0000FE
Reserved
0x000094
Reset – GOTO Inst ruction
Reset – GOTO Address 0x000002
Reserved 0x000082
0x000084
0x000004
Reserved Vector
Reserved Vector
Interrupt 0 Vector
—
Note 1: The user can always lower the priority
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
2: The IPL3 bit (CORCON<3>) is always
clear when interrupts are being pro-
cessed. It is set only during execution of
traps.
<Free Word>
015
W15 (before CALL)
W15 (after CALL)
Stack Grows Towards
Higher Address
0x0000
PC<15:0>
SRL IPL3 PC<22:16>
POP : [--W15]
PUSH: [W15++]
dsPIC30F3014/4013
DS70138G-page 64 2010 Microchip Technology Inc.
8.5 Alternate Vector Table
In program memory, the Interrupt Vector Table (IVT) is
follow ed b y the A ltern ate Interrupt Vector Table (AI VT),
as s h own in Figure 8-1. Access to the alternate vector
tabl e is provided by the AL TIV T bit in the INTCON2 reg-
ister. If the ALTIVT bit is set , al l i nterrupt and ex ce ptio n
processes use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vecto rs. The AIVT sup-
ports emulation and debugging efforts by providing a
means to s wi tc h betwe en an application and a supp ort
environment without requiring the interrupt vectors to
be reprogram m ed. This featu re als o en abl es switc hin g
between applications for evaluation of different
software algor ithms at r un time.
If the AIVT is not required, the program memory
allocated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
8.6 Fast Context Saving
A context saving option is available using shadow reg-
isters. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers, W0 through
W3. The s hadows are only o ne level deep. Th e shadow
registers are accessible using the PUSH.S and POP.S
instruc tions only.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority IS R shou ld no t inc lude the s ame instru c-
tions. Users must save the key registers in software
during a lo wer priori ty interru pt if the h igher pri ority ISR
uses fast context saving.
8.7 External Interrupt Requests
The interrupt controller supports up to five external
interrupt request signals, INT0-INT4. These inputs are
edge sensitive; they require a low-to-high or a high-to-
low transition to generate an interrupt request. The
INTCON2 re gister has thre e bits , INT0EP-INT2EP, that
select the polarity of the edge detection circuitry.
8.8 Wake-up from Sleep and Idle
The interrupt controller may be used to wake-up the
processor from either Sleep or Idle mode, if Sleep or
Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor wakes up from Sleep or Idle
and begins execution of the Interrupt Service Routine
(ISR) needed to process the int errup t reque st.
2010 Microchip Technology Inc. DS70138G-page 65
dsPIC30F3014/4013
TABLE 8-3: dsPIC30F3014 INTERRUPT CONTROLLER REGISTER MAP(1)
SFR
Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
INTCON1 0080 NSTDIS ———— OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —0000 0000 0000 0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000
IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000
IFS1 0086 ————C1IF— U2TXIF U2RXIF INT2IF — — — — — —INT1IF0000 0000 0000 0000
IFS2 0088 — — — — —LVDIF— — — — — — — — — — 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E ————C1IE— U2TXIE U2RXIE INT2IE — — — — — —INT1IE0000 0000 0000 0000
IEC2 0090 — — — — —LVDIE— — — — — — — — — — 0000 0000 0000 0000
IPC0 0094 — T1IP<2:0> —OC1IP<2:0>— IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 —ADIP<2:0>— U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100
IPC3 009A — CNIP<2:0> —MI2CIP<2:0>— SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C — — — — — — — — — — — — — INT1IP<2:0> 0100 0100 0100 0100
IPC5 009E — INT2IP<2:0> — — — — — — — — — — — — 0100 0100 0100 0100
IPC6 00A0 — C1IP<2:0> — — — — — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100
IPC7 00A2 — — — — — — — — — — — — — — — — 0100 0100 0100 0100
IPC8 00A4 — — — — — — — — — — — — — — — — 0100 0100 0100 0100
IPC9 00A6 — — — — — — — — — — — — — — — — 0000 0100 0100 0100
IPC10 00A8 — — — — — LVDIP<2:0> — DCIIP<2:0> — — — — 0000 0100 0100 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 66 2010 Microchip Technology Inc.
TABLE 8-4: dsPIC30F4013 INTERRUPT CONTROLLER REGISTER MAP(1)
SFR
Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
INTCON1 0080 NSTDIS ———— OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —0000 0000 0000 0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000
IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000
IFS1 0086 ————C1IF— U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000
IFS2 0088 — — — — — LVDIF DCIIF — — — — — — — — — 0000 0000 0000 0000
IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000
IEC1 008E ————C1IE— U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000
IEC2 0090 — — — — — LVDIE DCIIE — — — — — — — — — 0000 0000 0000 0000
IPC0 0094 — T1IP<2:0> —OC1IP<2:0>— IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100
IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100
IPC2 0098 —ADIP<2:0>— U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100
IPC3 009A — CNIP<2:0> —MI2CIP<2:0>— SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100
IPC4 009C —OC3IP<2:0>—IC8IP<2:0>— IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100
IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100
IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100
IPC7 00A2 — — — — — — — — — — — — — — — — 0100 0100 0100 0100
IPC8 00A4 — — — — — — — — — — — — — — — — 0100 0100 0100 0100
IPC9 00A6 — — — — — — — — — — — — — — — — 0000 0100 0100 0100
IPC10 00A8 — — — — — LVDIP<2:0> — DCIIP<2:0> — — — — 0000 0100 0100 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2010 Microchip Technology Inc. DS70138G-page 67
dsPIC30F3014/4013
9.0 TIMER1 MODULE
This section describes the 16-bit general purpose
Timer1 module and associated operational modes.
Figure 9-1 depicts the simplified block diagram of the
16-bit Timer1 module.
The following sections provide a detailed description
including setup and control registers, along with
associated block diagrams for the operatio nal modes of
the timers.
The T imer1 mo dule is a 16-bit timer which can serv e as
the time counter for the Real-Time Clock (RTC), or
operate as a free-running interval timer/counter. The
16-bit timer has the following modes:
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
• Timer gate operation
• Selectable p rescaler settings
• Timer operation during CPU Idle and Sleep
modes
• Interrupt on 16-bit Period register match or falling
edge of external gate signal
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
present s a block diagram o f the 16-b it timer modul e.
16-Bit Timer Mode: In the 16-Bit Timer mode, the
timer increments on every instruction cycle up to a
match value preloaded into the Period register, PR1,
then reset s to ‘0’ and continues to count.
When the CPU go es into t he Idle m ode, the ti mer stop s
incrementing unless the TSIDL (T1CON<13>) bit = 0.
If TSIDL = 1, the timer m odule logic resu mes th e inc re-
menting sequence upon termination of the CPU Idle
mode.
16-Bit Synchronous Counter Mode: In the 16-Bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the CPU go es into t he Idle m ode, the ti mer stop s
incrementing unless the respective TSIDL bit = 0. If
TSIDL = 1, the timer module logic resumes the incre-
menting sequence upon termination of the CPU Idle
mode.
16-Bit Asynchronous Counter Mode: In the 16-Bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then reset s to ‘0’ and conti nue s.
When the timer is configured for the Asynchronous
mode of operation and the CPU goes into the Idle
mode, the timer stops incrementing if TSIDL = 1.
FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
TON
Sync
SOSCI
SOSCO/
PR1
T1IF
Equal Comparator x 16
TMR1
Reset
LPOSCEN
Event Flag
1
0
TSYNC
Q
QD
CK
TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
T1CK
TCS
1 x
0 1
TGATE
0 0
Gate
Sync
dsPIC30F3014/4013
DS70138G-page 68 2010 Microchip Technology Inc.
9.1 Timer Gate Operation
The 16-bi t timer can be pl aced in the Ga ted Ti me Accu-
mulation mode. This mode allows the internal TCY to
increm ent the respec tive timer when the gate input si g-
nal (T1CK pin) is asserted high. Control bit, TGATE
(T1CON<6>), must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source se t to int erna l (TCS = 0).
When the CPU go es into t he Idle m ode, the ti mer stop s
increm enti ng unless TSID L = 0. If TSIDL = 1, the timer
resumes the incrementing sequence upon termination
of the CPU Idle mode.
9.2 Timer Prescaler
The input clock (FOSC/4 or external clock) to the 16-bit
T imer has a pre scale optio n of 1:1, 1:8, 1:64 a nd 1:256,
selected by control bits, TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs:
• a write to the TMR1 register
• a write to the T1CON register
• device Reset, su ch as POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writin g to the TMR1 regis ter.
9.3 Timer Operation During Sleep
Mode
During CPU Sleep mode, the timer operates if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
(TCS = 1) and
• The TSYNC bit (T1CON<2>) is asse rted to a logic
‘0’ which defines the external clock so urce as
asynchronous.
When all three conditions are true, the timer continues
to count up to the Period register and is reset to
0x0000.
When a match between the timer and the Period
register occurs, an interrupt can be generated if the
respective timer interrupt enable bit is asserted.
9.4 Timer Interrupt
The 16-bit timer has the ability to generate an interrupt-
on-period match. When the timer count matches the
Perio d regis ter, the T1I F bit is asse rted and an interr upt
is generated, if enabled. The T1IF bit must be cleared in
sof tware. The T i mer Interru pt Flag, T1 IF, is loc ated in the
IFS0 Control register in the interrupt controller.
When the Gated Time Accumulation mode is enabled,
an interrupt is also genera ted on the fa lli ng edge of the
gate signal (at the end of the accumulation cycle).
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.
9.5 Real-Time Clock
Timer1, when operating in Real-Time Clock (RTC)
mode, provides time of day and event time-stamping
capabilities. Key operation al features of the RTC are:
• Operation from 32 kHz LP oscillator
• 8-bit presc ale r
•Low power
• Real-Time Clock interrupts
These operating modes are determined by setting the
appropriate bit(s) in the T1CON Control register.
FIGURE 9-2: RECOMMENDED
COMPONENTS FOR
TI MER1 LP OSCILLATOR
RTC
9.5.1 RTC OSCILLATOR OPERATION
When the TON = 1, T CS = 1 an d TGATE = 0, the timer
increme nts on the ris in g e dge of the 32 kH z LP os c ill a-
tor output sig nal, up to the val ue specifi ed in the Period
register and is then reset to ‘0’.
The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) disables the nor-
mal Timer and Counter modes and enable a timer
carry-out wake-up event.
When the C PU e nte rs Slee p m od e, the RTC co ntin ues
to opera te, provid ed the 32 kHz external c rystal oscill a-
tor is active and the control bits have not been
changed. The TSIDL bit should be cleared to ‘0’ in
order for R TC to contin ue ope rati on in Idle mode .
9.5.2 RTC INTERRUPTS
When an interrupt event oc curs, the respectiv e interrupt
flag, T1IF, is asserted and an interrupt is generated, if
enabled. The T1IF bit must be cleared in software. The
respective Timer Interrupt Flag, T1IF, is located in the
IFS0 register in the interrupt controller.
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.
SOSCI
SOSCO
R
C1
C2
dsPIC30FXXXX
32.768 kHz
XTAL
C1 = C2 = 18 pF; R = 100K
2010 Microchip Technology Inc. DS70138G-page 69
dsPIC30F3014/4013
TABLE 9-1: dsPIC30F3014/4013 TIMER1 REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
TMR1 0100 Timer1 Register uuuu uuuu uuuu uuuu
PR1 0102 Period Regis ter 1 1111 1111 1111 1111
T1CON 0104 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 —TSYNCTCS —0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 70 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 71
dsPIC30F3014/4013
10.0 TIMER2/3 MODULE
This s ection d escribes t he 32-bit general purpose tim er
module (Timer2/3) and associated operational modes.
Figure 10-1 depicts the simplified block diagram of the
32-bit Timer2/3 module. Figure 10-2 and Figure 10-3
show Timer2/3 configured as two independent 16-bit
timers, Ti mer2 and Timer3, respectively.
The Timer2/3 module is a 32-bit timer (which can be
configured as two 16-bit timers) with selectable
operating modes. These timers are utilized by other
periphe ral modules, such as:
• Input Capture
• Output Compare/Sim pl e PWM
The following sections provide a detailed description,
including setup and control registers, along with
associated block diagrams for the operatio nal modes of
the timers.
The 32-bit timer has the following modes:
• Two independent 16-bit timers (Timer2 and
Tim er3) with all 16-bit oper ating modes (exc ept
Asynchronous Counter mode)
• Single 32-bit timer operation
• Single 32-bit synchronous counter
Further, the following operational characteristics are
supported:
• AD C event trigger
• Timer gate operation
• Selectable p rescaler settings
• Timer operation during Idle and Sleep modes
• Interrupt on a 32-bit Period register match
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit T2CON and T3CON
SFRs.
For 32-bit timer/counter operation, Timer2 is the lsw
and Timer3 is the msw of the 32-bit timer.
16-Bit Timer Mode: In the 16-bit mode, Timer2 and
Timer3 can be configured as two independent 16-bit
timers. Each timer can be set up in either 16-bit Timer
mode or 16-bit Synchronous Counter mode. See
Section 9.0 “Tim er1 Mo dule ” for details on these two
operating modes.
The only functional difference between Timer2 and
Timer3 is that Timer2 provides synchronization of the
clock prescaler output. This is useful for high-frequency
external clock inputs.
32-Bit Timer Mode: In the 32-Bit Timer mode, the
timer increments on every instruction cycle, up to a
match val ue preloaded into the combine d 32-bit Period
register, PR3/PR2, then resets to ‘0’ and continues to
count.
For synchronous 32-bit reads of the Timer2/Timer3
pair, reading the lsw (TMR2 register) causes the msw
to be read and latched into a 16-bit holding register,
termed TMR3HLD.
For synchronous 32-bit writes, the holding register
(TMR3HLD) must first be written to. When followed by
a write to the TMR2 re gister, the content s of TM R3HLD
is transferred and latched into the MSB of the 32-bit
timer (TMR3).
32-Bit Synchronous Counter Mode: In the 32-Bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in the
combin ed 32 -bit Period reg ister, PR3/PR2, then resets
to ‘0’ and continues.
When the timer is configured for the Synchronous
Counter mode of operation and the CPU goes into the
Idle mode, the timer stops incrementing unless the
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
module logic resumes the incrementing sequence
upon termination of the CPU Idle mode.
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Note: For 32 -bit tim er ope rati on, T3CON cont rol
bits are ignored. Only T2CON control bits
are used for setup and control. Timer2
clock and gate inputs are utilized for the
32-bit timer module, but an interrupt is
generated with the Timer3 Interrupt Flag
(T3IF) and the interrupt is enabled with the
Timer3 interrupt enable bit (T3IE).
dsPIC30F3014/4013
DS70138G-page 72 2010 Microchip Technology Inc.
FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM
TMR3 TMR2
T3IF
Equal Comparator x 32
PR3 PR2
Reset
LSB MSB
Event Flag
Note: T imer Configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.
Data Bus<15:0>
Read TMR2
Write TMR2 16
16
16
Q
QD
CK
TGAT E ( T2 CON<6>)
(T2CON<6>)
TGATE
0
1
TON TCKPS<1:0>
2
TCY
TCS
1 x
0 1
TGATE
0 0
Gate
T2CK
Sync
ADC Event Trigger
Sync
TMR3HLD
Prescaler
1, 8, 64, 256
2010 Microchip Technology Inc. DS70138G-page 73
dsPIC30F3014/4013
FIGURE 10-2: 16- BIT TI MER2 BLOCK DIAGRAM
FIGURE 10-3: 16- BIT TI MER3 BLOCK DIAGRAM
TON
Sync
PR2
T2IF
Equal Comparator x 16
TMR2
Reset
Event Flag TGATE
TCKPS<1:0>
2
TGATE
TCY
1
0
TCS
1 x
0 1
TGATE
0 0
Gate
T2CK
Sync Prescaler
1, 8, 64, 256
Q
QD
CK
TON
PR3
T3IF
Equal Comparator x 16
TMR3
Reset
Event Flag TGATE
TCKPS<1:0>
2
TGATE
TCY
1
0
TCS
1 x
0 1
TGATE
0 0
T3CK
ADC Event Trigger
Sync
Q
QD
CK
Prescaler
1, 8, 64, 256
Note: T3CK pin does not exist on dsPIC30F3014/4013 devices. The block diagram shown here illustrates the
schematic of Timer3 as implemented on the dsPIC30F6014 device.
dsPIC30F3014/4013
DS70138G-page 74 2010 Microchip Technology Inc.
10.1 Timer Gate Operation
The 32-bi t timer can be pl aced in the Ga ted Ti me Accu-
mulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input
signa l ( T 2C K pi n) i s as se rt ed hi g h. C o ntr o l bit , TG ATE
(T2CON<6>), must be set to enable this mode. When
in this mode, Timer2 is the originating clock source.
The TGATE setting is ignored for Timer3. The timer
must be e nab led (T O N = 1) and the time r cl oc k so urc e
set to internal (TCS = 0).
The falling edge of the external signal terminates the
count operation but does not reset the timer. The user
must reset the timer in order to sta rt counting from ze ro.
10.2 ADC Event Trigger
When a matc h occurs betwe en the 32-bit tim er (TMR3/
TMR2) and the 32-bit combined Period register (PR3/
PR2), a special ADC trigger event signal is generated
by Timer3.
10.3 Timer Prescaler
The in put cloc k (FOSC/4 or external clock) to the timer
has a prescale option of 1:1, 1:8, 1:64 and 1:256,
selected by control bits, TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
origina ting clock source is Time r2. The prescaler oper-
ation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
• a write to the TMR2/TMR3 register
• a write to the T2CON/T3CON register
• device Reset, su ch as POR and BOR
However, if the timer is disabled (TON = 0), then the
Timer2 prescaler cannot be reset since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.
10.4 Timer Operation During Sleep
Mode
During CPU Sleep mode, the timer does not operate
because the internal clocks are disabled.
10.5 Timer Interrupt
The 32-bit timer module can generate an interrupt-on-
period ma tch or on the fall ing edg e of the ext ernal ga te
signal. When the 32-bit timer count matches the
respective 32-bit Period register, or the falling edge of
the external “gate” signal is detected, the T3IF bit
(IFS0<7>) is asserted and an interrupt is generated, if
enabled . In th is mode, th e T3IF interrupt fl ag is u sed as
the source of the interrupt. The T3IF bit must be
cleared in software.
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T3IE (IEC0<7>).
2010 Microchip Technology Inc. DS70138G-page 75
dsPIC30F3014/4013
TABLE 10-1: dsPIC30F3014/4013 TIMER2/3 REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) uuuu uuuu uuuu uuuu
TMR3 010A Time r3 Register uuuu uuuu uuuu uuuu
PR2 010C Period Register 2 1111 1111 1111 1111
PR3 010E Period Register 3 1111 1111 1111 1111
T2CON 0110 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS —0000 0000 0000 0000
T3CON 0112 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 ——TCS —0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 76 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 77
dsPIC30F3014/4013
11.0 TIMER4/5 MODULE
This section describes the second 32-bit general
purpose timer module (Timer4/5) and associated
operational modes. Figure 11-1 depicts the simplified
block diagram of the 32-bit Timer4/5 module.
Figure 11-2 and Figure 11-3 show T imer4/5 confi gured
as two independent 16-bit timers, Timer4 and Timer5,
respectively.
The Timer4/5 module is similar in operation to the
Timer2/3 module. However, there are some
differences:
• The Timer4/5 module does not support the ADC
event trigger fea ture
• Timer4/5 can not be utilized by other peripheral
modules, such as input capture and output compare
The oper ating modes of the T imer4/5 module are deter-
mined by setting the appropriate bit(s) in the 16-bit
T4CON and T5CON SFRs.
For 32-bit timer/counter operation, Timer4 is the lsw
and Timer5 is the msw of the 32-bit timer.
FIGURE 11 -1: 32-BIT TIMER 4/5 BLOCK DIAGRAM
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046).
Note: For 32 -bit tim er ope rati on, T5CON cont rol
bits are ignored. Only T4CON control bits
are used for setup and control. Timer4
clock and gate inputs are utilized for the
32-bit timer module but an interrupt is
generated with the Timer5 Interrupt Flag
(T5IF) and the interrupt is enabled with the
Timer5 interrupt enable bit (T5IE).
TMR5 TMR4
T5IF
Equal Comparator x 32
PR5 PR4
Reset
LSB
MSB
Event Flag
Note: Timer Configuration bit, T32 (T4CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All
control bits are respective to the T4CON register.
Data Bu s< 15 :0 >
TMR5HLD
Read TMR4
Write TMR4 16
16
16
Q
QD
CK
TGATE (T4CON<6>)
(T4CON<6>)
TGATE
0
1
TON TCKPS<1:0>
Prescaler
1, 8, 64 , 25 6
2
TCY
TCS
1 x
0 1
TGATE
0 0
Gate
T4CK
Sync
Sync
dsPIC30F3014/4013
DS70138G-page 78 2010 Microchip Technology Inc.
FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM
FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM
TON
Sync
PR4
T4IF
Equal Comparator x 16
TMR4
Reset
Event Flag TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
TCS
1 x
0 1
TGATE
0 0
Gate
T4CK
Sync
Q
QD
CK
TON
PR5
T5IF
Equal Comparator x 16
TMR5
Reset
Event Flag TGATE
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
TGATE
TCY
1
0
TCS
1 x
0 1
TGATE
0 0
T5CK
ADC Event Trigger
Sync
Q
QD
CK
Note: In the dsPIC30F3014 device, there is no T5CK pin. Therefore, in this device the following modes should
not be used for Timer5:
2: TCS = 1 (16-bit coun ter)
3: TCS = 0, TGATE = 1 (gated time accumulation)
2010 Microchip Technology Inc. DS70138G-page 79
dsPIC30F3014/4013
TABLE 1 1 -1: dsPIC30F4013 TIMER4/5 REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
TMR4 0114 Timer4 Register uuuu uuuu uuuu uuuu
TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) uuuu uuuu uuuu uuuu
TMR5 0118 Timer5 Register uuuu uuuu uuuu uuuu
PR4 011A Period Register 4 1111 1111 1111 1111
PR5 011C Period Register 5 1111 1111 1111 1111
T4CON 011E TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS—0000 0000 0000 0000
T5CON 0120 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 ——TCS—0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 80 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 81
dsPIC30F3014/4013
12.0 INPUT CAPTURE MODULE
This section describes the input capture module and
associated operational modes. The features provided
by this module are useful in applications requiring fre-
quency (period) and pulse measurement. Figure 12-1
depicts a block diagram of the input capture module.
Input capture is useful for such modes as:
• Frequency/Period/Pulse Measurements
• Additional Sources of External Interrupts
The key operational features of the input capture
module are:
• Simple Capture Event mode
• Timer2 and Timer3 mode selection
• Interrupt on input capture event
These operating modes are determined by setting the
appropriate bits in the ICxCON register (where
x = 1,2,...,N). The dsPIC DSC devices contain up to 8
capture channels (i.e., the maximum value of N is 8).
The dsPIC30F3014 device contains 2 capture
channels while the dsPIC30F4013 device contains
4 capture channels.
12.1 Simple Capture Event Mode
The simple capture events in the dsPIC30F product
family are:
• Capture every falling edge
• Capture every rising edge
• Capture every 4th rising edge
• Capture every 16th rising edge
• Capture every rising and falling edge
These simple Input Capture modes are configured by
setting t he appropri ate bits, IC M<2:0> (ICx CON<2:0>).
12.1.1 CAPTURE PRESCALER
There are four input capture prescaler settings speci-
fied by bits, ICM<2:0> (ICxCON<2:0>). Whenever the
capture channel is turned off, the prescaler counter is
cleared. In addition, any Reset clears the prescaler
counter.
FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
ICxBUF
Prescaler
ICx pin
ICM<2:0>
Mode Select
3
Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture
channels, 1 through N.
10
Set Flag
ICxIF
ICTMR
T2_CNT T3_CNT
Edge
Detection
Logic
Clock
Synchronizer
1, 4, 16
From GP Timer Module
16 16
FIFO
R/W
Logic
ICI<1:0>
ICBN E, IC O V
ICxCON Interrupt
Logic
Set Flag
ICxIF
Data Bus
dsPIC30F3014/4013
DS70138G-page 82 2010 Microchip Technology Inc.
12.1.2 CAPTURE BUFFER OPERATION
Each capture channel has an associated FIFO buffer
which is four 16-bit words deep. There are two status
flags which provide status on the FIFO buffer:
• ICBNE – Input Capture Buffer Not Empty
• IC OV – Input Capture Ov erfl ow
The ICBFNE is set on the first input capture event and
remain s et unt il all ca pture even ts have b een read from
the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.
In the event that the FIFO is full with four capture
events and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition occurs an d the ICOV
bit is s et to a log ic ‘1’. The fif th c apture eve nt is lost an d
is not stored in the FIFO. No additional events are
captured until all four events have been read from the
buffer.
If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results .
12.1.3 TIMER2 AND TIMER3 SELECTION
MODE
The inp ut capture mod ule c onsist s of up to 8 input cap-
ture chann els. Each channel can select between one of
two timers for the time base, Timer2 or Timer3.
Selection of the timer resource is accomplished
through SFR bit, ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
12.1.4 HALL SENSOR MODE
When the input capture module is set for capture on
every edge, rising and falling, ICM<2:0> = 001, the
following operations are performed by the input capture
logic:
• The input capture interrupt flag is set on every
edge, rising and falling.
• The interrupt on Capture mode setting bits,
ICI<1:0>, is ignored since every capture
generates an interrupt.
• A capture overflow condition is not generated in
this mode.
12.2 Input Capture Operation During
Sleep and Idle Modes
An input capture event generates a device wake-up or
interrupt, if enabl ed, if the devi ce is in CPU Id le or Sleep
mode.
Independent of the timer being enabled, the input cap-
ture module wakes up from the CPU Sleep or Idle mode
when a c apture event occurs if ICM<2:0> = 111 and the
interrupt enable bit is asserted. The same wake-up can
generate an interrupt if the conditions for processing the
interrupt have been satisfied. The wake-up feature is
useful as a method of adding extra external pin
interrupts.
12.2.1 INPUT CAPTURE IN CPU SLEEP
MODE
CPU Sleep mode allows input capture module opera-
tion w ith reduced function ality. In the CPU Sleep mode,
the ICI<1:0> bits are not applicable and the input cap-
ture module can only function as an external interrupt
source.
The capture module must be configured for interrupt
only on rising edge (ICM<2:0> = 111) in order for the
input capture module to be used while the device is in
Sleep mode. The prescale settings of 4:1 or 16:1 are
not applicable in this mode.
12.2.2 INPUT CAPTURE IN CPU IDLE
MODE
CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the Inter-
rupt mode selected by the ICI<1:0> bits is applicable,
as well as the 4:1 and 16:1 capture prescale settings
which are d efined by co ntrol bits, ICM< 2:0>. This mod e
requires the selected timer to be enabled. Moreover,
the ICSIDL bit must be asserted to a logic ‘0’.
If the input capture module is defined as
ICM<2:0> = 111 in CPU Idle mode, the input capture
pin serves only as an external interrupt pin.
12.3 Input Capture Interrupts
The inpu t captur e channe ls have the a bility to generate
an interrupt based upon the selected number of
capture events. The selection number is set by control
bits, ICI<1:0> (ICxCON<6:5>).
Each chan nel provide s an interrupt flag (IC xIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx register.
Enabling an interrupt is accomplished via the respec-
tive Input C apture Chann el Interrupt En able (ICx IE) bit.
The capture interrupt enable bit is located in the
corresponding IEC Control register.
2010 Microchip Technology Inc. DS70138G-page 83
dsPIC30F3014/4013
TABLE 12-1: dsPIC30F3014 INPUT CAPTURE REGISTER MAP(1)
TABLE 12-2: dsPIC30F4013 INPUT CAPTURE REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu
IC1CON 0142 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu
IC2CON 0146 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu
IC1CON 0142 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu
IC2CON 0146 ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC7BUF 0158 Input 7 Capture Register uuuu uuuu uuuu uuuu
IC7CON 015A ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
IC8BUF 015C Input 8 Capture Register uuuu uuuu uuuu uuuu
IC8CON 015E ——ICSIDL— — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 84 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 85
dsPIC30F3014/4013
13.0 OUTPUT COMP ARE MODULE
This sec tion desc ribes the ou tput comp are modu le and
associated operational modes. The features provided
by this module are useful in applications requiring
operational modes, such as:
• Generation of Variable Width Output Pulses
• Pow er Fact or Correction
Figure 13-1 depicts a block diagram of the output
compare module.
The key operational features of the output compare
module includ e:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simp le P WM mo de
• Output Compare During Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where
x = 1,2,3,...,N). The dsPIC DSC devices contain up to
8 comp are channels (i.e., the maximum value of N i s 8).
The dsPIC30F3014 device contains 2 compare
channels while the dsPIC30F4013 device contains
4 compare channels.
OCxRS and OCxR in Figure 13-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the f irst comp are and O CxRS
is used for the second compare.
13.1 T imer2 and Ti mer3 Selection Mode
Each output compare channel can select between one
of two 16-bit timers: Timer2 or Timer3.
The selection of the timers is controlled by the OCT SEL
bit (OCxCON<3> ). Timer2 is th e defau lt timer resource
for the output compare module.
FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
OCxR
Comparator
Output
Logic QS
R
OCM<2:0>
Output OCx
Set Flag bit
OCxIF
OCxRS
Mode Select
3
Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels, 1 through N.
OCFA
OCTSEL 01
T2P2_MATCHTMR2<15:0 TMR3<15:0> T3P3_MATCH
From GP
(for x = 1, 2, 3 or 4)
or OCFB
(for x = 5, 6, 7 or 8)
01
Timer Module
Enable
dsPIC30F3014/4013
DS70138G-page 86 2010 Microchip Technology Inc.
13.2 Simple Output Compare Match
Mode
When control bit s, OC M< 2: 0> (O CxCO N <2 :0>) = 001,
010 or 011, the selected output compare channel is
configured for one of three simple Output Compare
Match modes:
• Compare forces I/O pin low
• Compare forces I/O pin high
• Compare toggles I/O pin
The OCxR reg is ter i s us ed in th es e m ode s. Th e O C xR
register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, o ne of these Compare Match mode s occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.
13.3 Dual Output Compare Match Mode
When control bits, OCM<2:0> (OCxCON<2:0>) = 100
or 101, the selec ted outp ut compare chan nel is co nfig-
ured for one of two Dual Output Compare modes,
which ar e:
• Single Output Pulse mode
• Continuous Output Pulse mode
13.3.1 SINGLE PULSE MODE
For the use r to confi gure the modul e for the ge ner ation
of a single output pulse, the following steps are
required (assuming timer is off):
• Determine instruction cycle time, TCY.
• Calcu la te d es ired pulse w id t h v al ue bas ed on TCY.
• Calcu late time to S t art pulse from time r star t value
of 0x0000.
• Write pulse-width start and stop times into OCxR
and OCxRS Compare registers (x denotes
channel 1, 2, ...,N).
• Set Timer Period register to value equal to or
greater than value in OCxRS Compare register.
• Set OCM<2:0> = 100.
• Enable timer, TON (TxCON<15>) = 1.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100.
13.3.2 CONTINUOUS PULSE MODE
For the use r to confi gure the modul e for the ge neratio n
of a continuous stream of output pulses, the following
steps are required:
• Determine instruction cycle time, TCY.
• Calculate desired pulse value based on TCY.
• Calculate timer to Start pulse width from timer
start value of 0x0000.
• Write pulse-width Start and Stop times into OCxR
and OCxRS (x denotes channel 1, 2, ...,N)
Compare registers, respectively.
• Set Timer Period register to value equal to or
greater than value in OCxRS Compare register.
• Set OCM<2:0> = 101.
• Enable timer, TON (TxCON<15>) = 1.
13.4 Simple PWM Mode
When control bits, OCM<2:0> (OCxCON<2:0>) = 110
or 111, the selec ted outp ut comp are c hannel is confi g-
ured for th e PWM mode of opera tion. When co nfigured
for the PWM mode of operation, OCxR is the main l atch
(read-only) and OCxRS is the secondary latch. This
enables glitchless PWM transitions.
The user must perform the following steps in order to
configure the output compare module for PWM
operation:
1. Set the PWM pe riod by writing to the appropriate
Period register.
2. Set the PWM duty cy cle by writ ing to the OCxRS
register.
3. Configure the output compare module for PWM
operation.
4. Set the TMRx prescale value and enable the
timer, TON (TxCON<15>) = 1.
13.4.1 INPUT PIN FAULT PROTECTION
FOR PWM
When con trol bits, OCM <2: 0> (O CxCO N<2 :0>) = 111,
the selected output compare channel is again config-
ured fo r the PWM mode of op eration with the add itional
feature of input Fault protection. While in this mode, if
a logic ‘0’ is detected on the OCF A/B pin, the respective
PWM output pin is placed in the high-impedance input
state . The O CFLT bit (OCxCON <4>) in dicate s wheth er
a Fault co ndition ha s occurred. Thi s state is mai ntaine d
until both of the following events have occurred:
• The external Fault condition has been removed.
• The PWM mode has been re-enabled by writing
to the appropriate control bits.
2010 Microchip Technology Inc. DS70138G-page 87
dsPIC30F3014/4013
13.4.2 PWM PERIOD
The PWM period is specified by writing to the PRx
register. The PWM period can be calculated using
Equation 13-1.
EQUATION 13-1:
PWM frequency is defined as 1/[PWM period].
When the selected TMRx is equal to its respective
Period regi ster, PRx, the followi ng four eve nts occur o n
the next increment cycle:
• TMRx is cleared.
• The OCx pin is set.
- Exception 1: If PWM duty cycle is 0x0000,
the OCx pin remains low.
- Exception 2: If duty cy cle is greater tha n PRx,
the pin remains high.
• The PWM duty cycle is latched from OCxRS into
OCxR.
• The corresponding timer interrupt flag is set.
See Figure 13-2 for key PWM period comparisons.
Timer3 is referred to in Figure 13-2 for clarity.
FIGURE 13-2: PWM OUTPUT TIMING
PWM period = [(PRx) + 1] • 4 • TOSC •
(TMRx prescale value)
Period
Duty Cycle
TMR3 = Duty Cycle T MR3 = Duty Cycle
TMR3 = PR3
T3IF = 1
(Interrupt Flag)
OCxR = OCxRS
TMR3 = PR3
(Interrupt Flag)
OCxR = OCxRS
T3IF = 1
(OCxR) (OCxR)
dsPIC30F3014/4013
DS70138G-page 88 2010 Microchip Technology Inc.
13.5 Output Comp are Operation During
CPU Sleep Mode
When the CPU enters Sleep mode, all internal clocks
are stopped. Therefore, when the CPU enters the
Sleep s t ate, the outp ut c om p a r e channel driv es the pi n
to the active state that was observed prior to entering
the CPU Sleep state.
For exam ple, if the pin was hi gh when the CPU en tered
the Sleep state, the pin remains high. Likewise, if the
pin wa s low wh en the CPU entered th e Sleep st ate, th e
pin remains low. In either case, the output compare
module res um es operation w hen the dev ic e w a ke s u p.
13.6 Output Comp are Operation During
CPU Idle Mode
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel operates during the CPU
Idle mode if the OCSIDL bit (OCxCON<13>) is at logic
‘0’ and the selected time base (Timer2 or Timer3) is
enabled and the TSIDL bit of the selected timer is set
to logic ‘0’.
13.7 Outp ut Compare Interrupts
The outpu t comp are channels have the abil ity to gener-
ate an interrupt on a compare match for whichever
Match mode has been selected.
For all modes, except the PWM mode, when a com-
pare e vent occurs, the respective in terrupt flag (OCx IF)
is asserted and an interrupt is generated, if enabled.
The OCx IF bit is located in the corresp onding IFSx reg-
ister and must be cleared in software. The interrupt is
enabled via the respective compare interrupt enable
(OCxIE ) bit located in the correspondin g IEC registe r.
For the PWM mode, when a n event occurs, the respec-
tive Timer Interru pt Fl a g (T2IF or T3 IF) i s ass erte d and
an interrupt is generated, if enabled. The TxIF bit is
located in the IFS0 re gister and mu st be cleared in sof t-
ware. The interrupt is enabled via the respective timer
interrupt enable bit (T2IE or T3IE) located in the IEC0
register. The outpu t compare interrupt flag is never set
during the PWM mode of operation.
2010 Microchip Technology Inc. DS70138G-page 89
dsPIC30F3014/4013
TABLE 13-1: dsPIC30F3014 OUTPUT COMPARE REGISTER MAP(1)
TABLE 13-2: dsPIC30F4013 OUTPUT COMPARE REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000
OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000
OC1CON 0184 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000
OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000
OC2CON 018A ——OCSIDL— — — — — — — — OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000
OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000
OC1CON 0184 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000
OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000
OC2CON 018A ——OCSIDL— — — — — — — — OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000
OC3RS 018C Output Compare 3 Secondary Register 0000 0000 0000 0000
OC3R 018E Output Compare 3 Main Register 0000 0000 0000 0000
OC3CON 0190 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
OC4RS 0192 Output Compare 4 Secondary Register 0000 0000 0000 0000
OC4R 0194 Output Compare 4 Main Register 0000 0000 0000 0000
OC4CON 0196 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 90 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 91
dsPIC30F3014/4013
14.0 I2C™ MODULE
The Inter-Integrated Circuit (I2CTM) module provides
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication
standard with a 16-bit interface.
This module offers the following key features:
•I
2C interface supporting both master and slave
operation.
•I
2C Slav e mode supp orts 7-bit a nd 10-b it add ress-
ing.
•I
2C Master mode supports 7-bit and 10-bit
addressing.
•I
2C port allows bidirectional transfers between
master and slav es.
• Serial clock synchronization for I2C port can be
used as a ha ndshake mechanis m to suspen d and
resume serial transfer (SCLREL control).
•I
2C supports multi-master operation; detects bus
collision and arbitrates accordingly.
14.1 Operating Function Description
The hardw are fully imple ments al l the master an d slave
functions of the I2C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
Thus, the I2C module can operate either as a slave or
a master on an I2C bus.
14.1.1 VARIOUS I2C MODES
The following types of I2C operation are supported:
•I
2C slave operation with 7-bit addressing
•I
2C slave operation with 10-bit addressing
•I
2C master operation with 7-bit or 10-bit addressing
See the I2C programmer’s model in Figure 14-1.
14.1.2 PIN CONFIGURATION IN I2C MODE
I2C has a 2-pin interface: the SCL pin is clock and the
SDA pin is data.
14.1.3 I2C REGISTERS
I2CCON and I2C STAT are control and s ta tus reg isters,
respect ively. The I2CCON reg ister is readable and writ-
able. The lower 6 bits of I2CSTAT are read-only. The
remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer as shown in Figure 14-1.
I2CTRN is the transmit register to which bytes are
written during a transmit operation, as shown in
Figure 14-2.
The I2CADD regis ter hol ds the s lave a ddress. A status
bit, ADD10, indicates 10-Bit Addressing mode. The
I2CBRG acts as the Baud Rate Generator reload
value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and an interrupt pulse is generated. During
transmission, the I2CTRN is not double-buffered.
FIGURE 14- 1 : PROGRAMMER’S MODEL
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
'dsPIC30F Family Reference Manual'
(DS70046).
Note: Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit addre ss .
Bit 7 Bit 0 I2CRCV (8 bits)
Bit 7 Bit 0 I2CTRN (8 bits)
Bit 8 Bit 0 I2CBRG (9 bits)
Bit 15 Bit 0 I2CCON (16 bits)
Bit 15 Bit 0 I2CSTAT (16 bits)
Bit 9 Bit 0 I2CADD (10 bits)
dsPIC30F3014/4013
DS70138G-page 92 2010 Microchip Technology Inc.
FIGURE 14-2: I2C™ BLOCK DIAGRAM
I2CRSR
I2CRCV
Internal
Data Bus
SCL
SDA
Shift
Mat ch Detect
I2CADD
Start and
Stop bit Detect
Clock
Addr_Match
Clock
Stretching
I2CTRN LSB
Shift
Clock
Write
Read
BRG Down I2CBRG
Reload
Control
FCY
Start, Restart,
Stop bit Generate
Write
Read
Acknowledge
Generation
Collision
Detect
Write
Read
Write
Read
I2CCON
Write
Read
I2CSTAT
Control Logic
Read
LSB
Counter
2010 Microchip Technology Inc. DS70138G-page 93
dsPIC30F3014/4013
14.2 I2C Module Addresses
The I2CADD register contains the Slave mode
addresses. The register is a 10-bit register.
If the A10M bit (I2CCON<10>) is ‘0’, the address is
inter prete d by the mo dul e as a 7 - bit add ress . When an
address is re ceived, i t is c ompa red to the 7 LSbs of the
I2CADD register.
If the A10M bit is ‘1’, the address is assumed to be a
10-bit add ress. When an address is rec eived, it is com-
pared with the binary value, ‘11110 A9 A8’ (w here A9
and A8 are two Most S ignifi cant b its of I2CA DD). I f that
value matches, the next address is compared with the
Least Significant 8 bits of I2CADD, as specified in the
10-bit addressing protocol.
14.3 I2C 7-Bit Slave Mode Operati o n
Once enabled (I2CEN = 1), the slave module waits for
a S t art bit to occ ur (i.e., the I2C module i s ‘Idle’). F ollow-
ing the detection of a Start bit, 8 bits are shifted into
I2CRSR, and the address is compared against
I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0>
are compared against I2CRSR<7:1> and I2CRSR<0>
is the R_W bit. All incoming bits are sampled on the
rising edge of SCL.
If an address match occurs, an Acknowledgement is
sent and the Slave Event Interrupt Flag (SI2CIF) is set
on the falling edge of the ninth (ACK) bit. The address
match does not affect the contents of the I2CRCV buf-
fer or the RBF bit.
14.3 .1 SLAVE TR ANSMISSION
If the R _W bi t re ceived is a ‘1’, the s eri al port goes into
Transmit mode. It sends an ACK on the ninth bit and
then ho lds SCL to ‘0’ u nt il th e CP U r es po nd s b y wr iti n g
to I2CTRN . SCL is releas ed by setting th e SCLREL bit,
and 8 bits of data are shifted out. Data bits are shifted
out on the falling edge of SCL, such that SDA is valid
during SCL high. The interrupt pulse is sent on the
falling edge of the ninth clock pulse, regardless of the
status of the ACK received from the master.
14.3.2 SLAV E RECEP TION
If the R_W bit received is a ‘0’ during an address
match, then Receive mode is initiated. Incoming bits
are sampl ed on the ris in g edg e of SC L. Af te r 8 bit s are
received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK is sent on the
ninth clock.
If the RBF flag is set, indicating that I2CRCV is still
holding data from a pre vious operati on (RBF = 1), the n
ACK is not sent; however, the interrupt pulse is gener-
ated. In the case of an overflow, the contents of the
I2CRSR are not loaded into the I2CRCV.
14.4 I2C 10-Bit Slave Mode Operati on
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match is more complex.
The I2C specification dictates that a slave must be
address ed for a write operatio n with two ad dress byte s
following a Start bit.
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a 7-bit
address. The address detection protocol for the first byte
of a message address is identical for 7-bit and 10-bit
mess ag es , b ut the bit s be ing com p a r ed ar e different.
I2CADD holds the entire 10-bit address. Upon receiv-
ing an address following a Start bit, I2CRSR <7:3> is
compared against a literal ‘11110’ (the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs and if R_W = 0, the
interr upt pulse is sent. Th e ADD10 b it is clea red to ind i-
cate a partial address match. If a match fails or
R_W = 1, the ADD10 bit is cleared and the module
returns to the Idle state.
The low byte of the address is then received and com-
pared with I2CADD<7:0>. If an address match occurs,
the interrupt pulse is generated and the ADD10 bit is
set, indicating a complete 10-bit address match. If an
address match did not occur, the ADD10 bit is cleared
and the module returns to the Idle state.
14.4.1 10-BIT MOD E SLAVE TRAN SMISS ION
Once a slave is addressed in this fashion with the full
10-bit address (we refer to this state as
“PRIOR_ADDR_MATCH”), the master can begin
sending data bytes for a slave reception operation.
TABLE 14-1: 7-BIT I2C™ SLAVE
ADDRESSES SUPPORTED BY
dsPIC30F
0x00 General Call Address or Start Byte
0x01-0x03 Reserved
0x04-0x0 7 HS mode Master Codes
0x08-0x77 Valid 7-Bit Addresses
0x78-0x7b Valid 10-Bit Addresses (lower 7 bits)
0x7c-0x7f Reserved
Note: The I2CRCV is loaded if the I2COV bit = 1
and the RBF flag = 0. In this case, a read
of the I2CRCV was performed but the
user did not clear the state of the I2COV
bit before the next receive occurred. The
acknowledgement is not sent (ACK = 1)
and the I2CRCV is updated.
dsPIC30F3014/4013
DS70138G-page 94 2010 Microchip Technology Inc.
14.4.2 10-BIT MODE SLAVE RECEPTION
Once ad dress ed, the ma ster ca n genera te a Rep eated
Start, reset the high byte of the address and set the
R_W bit without generating a Stop bit, thus initiating a
slave tran sm it ope ratio n.
14.5 Automatic Clock Stretch
In the Slave modes, the module can synchronize buffer
reads and write to the master device by clock stretching.
14.5.1 TRANSMI T CLOCK STRETCHING
Both 10-Bit an d 7-Bi t Trans mi t mo des imp lement cloc k
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock, if the TBF bit is cleared,
indicating the buffer is empty.
In Slave Transmit modes, clock stretching is always
performed irrespective of the STREN bit.
Clock synchronization takes place following the ninth
clock of the transmit sequence. If the device samples
an AC K on the falling edge of the ninth clock and if the
TBF bit is still clear, then the SCLREL bit is automati-
cally cleared. The SCLREL being cleared to ‘0’ asserts
the SCL li ne low. The user’s ISR must se t the SCLR EL
bit before transmissi on i s a llo wed to continu e. By hol d-
ing the SCL line low, the user has time to service the
ISR and load the contents of the I2CTRN before the
master device can initiate another transmit sequence.
14.5.2 RECEIV E CLOCK STRETCHING
The STREN bit in the I2CCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCL pi n is held low at the en d
of each data receive sequence.
14.5.3 CLOCK STRETCHING DURING
7-BIT ADDRESSING (STREN = 1)
When the S TREN bit is set in Sla ve Receive mode , the
SCL lin e is hel d low when th e buf fe r regist er is full . The
method for stretching the SCL output is the same for
both 7 and 10-Bit Addressing modes.
Clock stretch ing ta kes pla ce follo wing th e ninth clock of
the receive sequence. On the falling edge of the ninth
clock at the end of the AC K sequence, if the RBF bit is
set, the SCLREL bit is automatically cleared, forcing
the SCL o utput to be hel d low. The user’s ISR must s et
the SCLREL bit before reception is allowed to continue.
By hol ding th e SCL line lo w, the us er has time to ser-
vice the ISR and read the contents of the I2CRCV
before the master device can initiate another receive
sequence. This prevents buffer overruns from
occurring.
14.5.4 CLOCK STRETCHING DURING
10-BIT ADDRESSING (STREN = 1)
Clock stretching takes place automatically during the
addressing sequence. Because this module has a
register for the entire address, it is not necessary for
the protocol to wait for the address to be updated.
After the address phase is complete, clock stretching
occurs on each data receive or transmit sequence, as
describ ed earl ie r.
14.6 Software Controlled Clock
Stretching (STREN = 1)
When the STREN bit is ‘1’, the SCLREL bit can be
cleared by software to allow software to control the
clock stretching. Program logic synchronizes writes to
the SCLREL bit with the SCL clock. Clearing the
SCLREL bit does not assert the SCL output until the
module detects a falling edge on the SCL output and
SCL is sampled low . If the SCLREL bit is cleared by the
user w hile the SCL li ne has been sam pled low , the SCL
output is asserted (held low). The SCL output remains
low until the SC LREL bit is s et and all oth er devic es on
the I2C bus have deasserted SCL. This ensures that a
write to the SCLREL bit does not violate the minimum
high time requirement for SCL.
If the STREN bit is ‘0’, a software write to the SCLREL
bit is d isregarded and has no effect on the SCL REL bit.
Note 1: If the user load s the content s of I2C TR N,
setting the TBF bit before the falling edge
of the ninth clock, the SCLREL bit is not
be cleared and clock stretching does not
occur.
2: The SCLREL bit can be set in software,
regardless of the state of the TBF bit.
Note 1: If the user reads the contents of the
I2CRCV, clearing the RBF bit before the
falling edge of the ninth clock, the
SCLREL bit is not cleared and clock
stretching does not occur.
2: The SCLREL bit can be set in software
regardless of the state of the RBF bit. The
user should be careful to clear the RBF
bit in the ISR before the next receive
sequenc e i n o r der to p reve nt a n overflow
condition.
2010 Microchip Technology Inc. DS70138G-page 95
dsPIC30F3014/4013
14.7 Interrupts
The I2C module generates two interrupt flags, MI2CIF
(I2C Master I nterrupt Fla g) and SI2CIF (I2C Slav e Inter-
rupt Flag). The MI2CIF interrupt flag is activated on
completion of a master message event. The SI2CIF
interrupt flag is activated on detection of a message
directed to the slave.
14.8 Slope Control
The I2C standard requires slope control on the SDA
and SCL signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate
control if desired. It is necessary to disable the slew
rate control for 1 MHz mode.
14.9 IPMI Support
The con trol bit, IPM IEN, enabl es the modul e to supp ort
Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module ac ce pts and ac t s upo n
all addres ses .
14.10 General Call Address Support
The general call address can address all devices.
When this address is used, all devices should, in
theor y, respond with an Acknowl edgement.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R_W = 0.
The general call address is recognized when the Gen-
eral Call Enable (GCEN) bit is set (I2CCON<7> = 1).
Following a Start bit detection, 8 bits are shifted into
I2CRSR and the address is compared with I2CADD,
and is also compared with the general call address
which is fixed in hardware.
If a gen eral cal l addres s matc h occurs, the I2CRS R is
transferred to the I2CRCV after the eighth clock, the
RBF flag is set and on the falling edge of the ninth bit
(ACK bit), the Master Event Interrupt Flag (MI2CIF) is
set.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
I2CRCV to determine if the address w as device-specific
or a general call address.
14.11 I2C Master Support
As a master device, six operations are supported:
• Assert a Start condition on SDA and SCL.
• Assert a Restart condition on SDA and SCL.
• Write to the I2CTRN register initiating
transmission of data/address.
• Generate a Stop condition on SDA and SCL.
• Config ure the I2C port to receive data.
• Generate an ACK condition at the end of a
received byte of data.
14.12 I2C Master Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus is
not released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the data direction bit. In
this ca se, the da ta direc tion bit (R_ W) is logi c ‘0’. Serial
data is transmitted 8 bits at a time. After each byte is
transmitted, an ACK bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the data direction bit. In this case, the data
direction bit (R_W) is logic ‘1’. Thus, the first byte
transmitted is a 7-bit slave address, followed by a ‘1’ to
indica te the rece ive bit . Seria l dat a is rece ived v ia SDA
while SCL outputs the serial clock. Serial data is
receive d 8 bits at a time. After e ach byte is rece ived, an
ACK bit is transmitted. Start and Stop conditions indi-
cate the beginning and end of transmission.
14.12.1 I2C MASTER TRANSMISSION
Transmission of a data byte, a 7-bit address or the
second half of a 10-bit address, is accomplished by
simply writing a value to I2CTRN register. The user
should only write to I2CTRN when the module is in a
Wait state. This action sets the Buffer Full Flag (TBF)
and allow the Baud Rate Generator to begin counting
and start the next transmission. Each bit of address/
data is shifted out onto the SDA pin after the falling
edge of SCL is asserted. The Transmit Status Flag,
TRSTAT (I2CSTAT<14>), indicates that a master
transmit is in progress.
dsPIC30F3014/4013
DS70138G-page 96 2010 Microchip Technology Inc.
14.12.2 I2C MASTER RECEPTION
Master mode recepti on is enab led by progra mmin g the
Receive Enable bit, RCEN (I2CCON<3>). The I2C
module must be Idle before the RCEN bit is set; other-
wise, the RCEN bit is disregarded. The Baud Rate
Generator begins counting and on each rollover, the
state of the SCL pin ACK and data are shifted into the
I2CRSR on the rising edge of each clock.
14.12.3 BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the I2CBRG register. When the BRG is
loaded w ith th is v alu e, the BRG c ou nt s d ow n to ‘0’ and
stops until another reload has taken place. If clock
arbitration is taking place, for instance, the BRG is
reloaded when the SCL pin is sampled high.
As per the I2C standard, FSCK may be 100 kHz or
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.
EQUATION 14-1: SERIAL CLOCK RATE
14.12.4 CLOCK ARBITRATION
Clock arbitration oc curs when the m aster deasse rts the
SCL pi n (SCL al lowe d to fl oat hi gh) duri ng an y rece ive,
tran smit, or Res tart/Stop co nditio n. Wh en the S CL pin
is allowed to float high, the Baud Rate Generator
(BRG) is suspended from counting until the SCL pin is
actually sampled high. When the SCL pin is sampled
high, the Baud Rate Generator is reloaded with the
content s of I2CB RG and begin s counting. Th is ensures
that the SCL high time is always at least one BRG roll-
over count in the event that the clock is held low by an
external device.
14.12.5 MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-m aster operation support is achiev ed by bus arbi-
tration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA by letting SDA float high
whil e another mas ter asser ts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master sets the MI2CIF pulse and resetS the master
portion of the I2C port to its Idle state.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are deasserted and a
value can now be written to I2CTRN. When the user
services the I2C master event Interrupt Service
Rout i ne, if t h e I2C bus is free (i.e., the P bit is set), the
user can resume communication by asserting a Start
condition.
If a Start, Restart, Stop or Acknowledge condition was
in progres s wh en the b us co lli si on o cc urre d, th e c ond i-
tion is aborted, the SDA and SCL lines are deasserted
and the respective control bits in the I2CCON register
are cleared to ‘0’. When the user services the bus
collis ion Inte rrup t Serv ic e R ou tin e, an d if the I 2C bus is
free, the user can resume co mm uni ca tio n by as se rtin g
a St art conditi on .
The master continues to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit is
set.
A write to the I2CTRN s tarts the transm ission of d ata at
the firs t data bit, rega rdless of wh ere the tra nsmitter left
off when bus collision occurred.
In a multi-maste r en vi ronm en t, th e i nte rrupt generatio n
on the d etecti on of St art a nd Stop conditio ns al lows the
determination of when the bus is free. Control of t he I2C
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
14.13 I2C Module Operation During CPU
Sleep and Idle Modes
14.13.1 I2C OPERATION DURING CPU
SLEEP MO DE
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’. If
Sleep occurs in the middle of a transmission and the
state machine is partially into a transmission as the
clocks s top, the n the tra nsmiss ion is ab orted. Si milarl y,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
14.13.2 I2C OPERATION DURING CPU IDLE
MODE
For the I2C, the I2CSIDL bit determines if the module
stops or continues on Idle. If I2CSIDL = 0, the module
continues operation on assertion of the Idle mode. If
I2CSIDL = 1, the module stops on Idle.
I2CBRG = FCY FCY
FSCK 1,111,111 – 1
–
()
2010 Microchip Technology Inc. DS70138G-page 97
dsPIC30F3014/4013
TABLE 14-2: dsPIC30F3014/4013 I2C REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
I2CRCV 0200 — — — — — — — — Receive Register 0000 0000 0000 0000
I2CTRN 0202 — — — — — — — — Transmit Register 0000 0000 1111 1111
I2CBRG 0204 — — — — — — — Baud Rate Generator 0000 0000 0000 0000
I2CCON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000
I2CSTAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000
I2CADD 020A — — — — — — Address Regist er 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 98 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 99
dsPIC30F3014/4013
15.0 SPI MODULE
The Serial Peripheral Interface (SPI) module is a syn-
chronou s serial inte rface. It is usefu l for commun icating
with other periph eral devic es, suc h as EEPROMs, shi ft
registers, display drivers and A/D converters, or other
microcontrollers. It is compatible with Motorola’s SPI
and SIOP interfaces. The dsPIC30F3014 and
dsPIC30F4013 devi ce s feature one SPI modul e, SPI 1.
15.1 Operating Function Description
Each SPI module consists of a 16-bit shift register,
SPIxSR (whe re x = 1 or 2), used for shift ing data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON , configures th e module. Ad ditionally, a st atus
register , SPIxST A T, indicates various status conditions.
The serial interface consists of 4 pins: SDIx (Serial
Data Input), SDOx (Serial Data Output), SCKx (Shift
Clock Input or Output), and SSx (Active-Low Slave
Select).
In Master mode operation, SCKx is a clock output but
in Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shift
out bits from the SPIxSR to SDOx pin and
simultaneously shift in data from SDIx pin. An interrupt
is genera ted when the transfe r is complete and the cor-
responding interrupt flag bit (SPI1IF or SPI2IF) is set.
This interrupt can be disabled through an interrupt
enable bit (SPI1IE or SPI2IE).
The receive operation is double-buffered. When a com-
plet e by te i s r ecei ved , i t is tra nsf erre d f rom SPI xSR t o
SPIxBUF.
If the re ceive buf fer is full when new data is b eing trans-
ferred from SPIxSR to SPIxBUF, the module sets the
SPIROV bit, indicating an overflow condition. The
transfer of the data from SPIxSR to SPIxBUF is not
completed and new data is lost. The module does not
respond to SCL transitions while SPIROV is ‘1’,
effectively disabling the module until SPIxBUF is read
by user s oftware.
Transmit writes are also double-buffered. The user
writes to SPIxBUF. When the master or slave transfer
is completed, the con tents of the shi ft register (SPIxSR)
are mov ed to the receive buffer . If any transmit dat a has
been written to the buffer register, the contents of the
transmit buffer are moved to SPIxSR. The received
data is thus placed in SPIxBUF and the trans mit dat a in
SPIxSR is ready for the next transfer.
In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as a
value is written to SPIxBUF. The interrupt is generated
at the middle of the transfer of the last bit.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCKx. Again, the int er-
rupt is generated when the last bit is latched. If SSx
control i s enabled , then tran smission and recepti on are
enabled only when SSx = low. The SDOx output is
disabled in SSx mode with SSx high.
The clock provided to the module is (FOSC/4). This
clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transi-
tion from active clock state to Idle clock state, or vice
versa. The CKP bit selects the Idle state (high or low)
for the clock.
15.1.1 WORD AND BYTE
COMMUNICATION
A control bit, MODE16 (SPIxCON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation except
that the number of bits transmitted is 16 instead of 8.
The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.
A basic dif ference betwee n 8-bit and 16-bit operat ion is
that the data is transmitted out of bit 7 of the SPIxSR for
8-bit operation, and data is transmitted out of bit 15 of
the SPIxSR for 16-bit opera tion . In both mode s, dat a is
shifted into bit 0 of the SPIxSR.
15.1.2 SDOx DISABLE
A control bit , DISSDO, is provided to the SPIxCON reg-
ister to allow the SDOx output to be disabled. This
allows the SPI module to be connected in an input-only
configuration. SDOx can also be used for general
purpose I/O.
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). Note: Both the transmit buffer (SPIxTXB) and
the recei ve buffer (SPIxRXB) a re m app ed
to the same register address, SPIxBUF.
dsPIC30F3014/4013
DS70138G-page 100 2010 Microchip Technology Inc.
15.2 Framed SPI Support
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables frame d SPI s upport and c auses th e SSx pin to
perform the Frame Synchronization pulse (FSYNC)
function. The control bit, SPIFSD, determines whether
the SSx pin is an input or an output (i.e., whether the
module rec ei ves o r ge nera tes th e Frame Sync hron iz a-
tion pulse). The frame pulse is an active-high pulse for
a single SPI clock cycle. When Frame Synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
FIGURE 15-1: SP I BLOCK DIAGRAM
FIGURE 15-2: SP I MA STER/SLAVE CONNECTION
Note: x = 1 or 2.
Read Write
Internal
Data Bus
SDIx
SDOx
SSx
SCKx
SPIxSR
SPIxBUF
bit 0
Shift
Clock Edge
Select
Enable Master Clock
SSx and
Control
Clock
Control
Transmit
SPIxBUF
Receive
FSYNC
FCY
Primary
1:1, 1:4,
Prescaler
Secondary
Prescaler
1:1-1:8 1:16, 1:64
Serial Input Buffer
(SPIxBUF)
Shift Register
(SPIxSR)
MSb LSb
SDOx
SDIx
PROCESSOR 1
SCKx
SPI Master
Serial Input Buffer
(SPIyBUF)
Shift Register
(SPIySR)
LSb
MSb
SDIy
SDOy
PROCESSOR 2
SCKy
SPI Slav e
Serial Clock
Note: x = 1 or 2, y = 1 or 2.
2010 Microchip Technology Inc. DS70138G-page 101
dsPIC30F3014/4013
15.3 Slave Select Synchronization
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SSx pin
control enabled (SSEN = 1). When the SSx pin is low,
transmi ssio n and rec ep tio n are enabled and the SD Ox
pin is driven. W hen SSx pi n goes high , the SDO x pi n is
no longer driven. Also, the SPI module is resynchro-
nized, and all counters/control circuitry are reset.
Therefore, when the SSx pin is asserted low again,
transmission/reception begins at the MSb even if SSx
had been deasserted in the middle of a transmit/
receive.
15.4 SPI Operation During CPU Sleep
Mode
During Sleep mode, the SPI module is shut down. If th e
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver stop in Sleep mode.
Howeve r , regi ster conten ts are not af fected by entering
or exiting Sleep mode.
15.5 SPI Operation During CPU Idle
Mode
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPIxSTAT<13>)
determines if the SPI module stops or continues on
Idle. If SPISIDL = 0, the module continues to operate
when the CPU enters Idle mode. If SPISIDL = 1, the
module stops when the CPU enters Idle mode.
dsPIC30F3014/4013
DS70138G-page 102 2010 Microchip Technology Inc.
TABLE 15-1: dsPIC30F3014/4013 SPI1 REGISTER MAP
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
SPI1STAT 0220 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000
SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000
SPI1BUF 0224 Transmit and Receive Buffer 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2010 Microchip Technology Inc. DS70138G-page 103
dsPIC30F3014/4013
16.0 UNIV ERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART) MODULE
This section describes the Universal Asynchronous
Receiver/Transmitter Communications module.
16.1 UART Module Overview
The key features of the UART module are:
• Full-duplex, 8 or 9-bit data communication
• Even, odd or no parity options (for 8-bit data)
• One or two Stop bits
• Fully integ rate d Baud R ate Ge nera tor w ith 16-b it
prescaler
• Baud rates range from 38 bps to 1.875 Mbps at a
30 MHz instruction rate
• 4-word deep transmit data buffer
• 4-word deep receive data buffer
• Parity, framing and buffer overrun error detection
• Support for interrupt only on address detect
(9th bit = 1)
• Separate transmit and receive interrupts
• Loopback mode for diagnostic support
• Two choices of TX/RX pins on UART1 module
FIGURE 16-1: UART TRANSMITTER BLOCK DIAGRAM
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Write Write
UTX8 UxTXREG Low Byte
Load TSR
Transmit Control
– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt
Control and Status bits
UxTXIF
Data
‘0’ (Start)
‘1’ (Stop)
Parity Parity
Generator
Transmit Shift Regist er (UxTSR)
16 Divider
Control
Signals
16x Baud Clock
from Baud Rate
Generator
Internal Data Bus
UTXBRK
UxTX
Note: x = 1 or 2.
or UxATX
if ALTIO = 1
dsPIC30F3014/4013
DS70138G-page 104 2010 Microchip Technology Inc.
FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM
Read
URX8 UxRXREG Low Byte
Load RSR
UxMODE
Receive Buffer Control
– Generate Flags
– Generate Interrupt
UxRXIF
UxRX · Start bit Detect
Receive Shift Register
16 Divider
Control
Signals
UxSTA
– Shift Data Characters
Read Read
Write Write
to Buffer
8-9
(UxRSR)
PERR
FERR
· Parity Check
· Stop bit Detect
· Shift Clock Generation
· Wake Logic
16
Interna l Data Bus
1
0
LPBACK
From UxTX
16x Baud Clock from
Baud Rate Generator
or UxARX
if ALTIO = 1
2010 Microchip Technology Inc. DS70138G-page 105
dsPIC30F3014/4013
16.2 Enabling and Setting Up UART
16.2.1 ENABLING THE UART
The UART module is enabled by setting the UARTEN
bit in the UxMODE register (where x = 1 or 2). Once
enabled , the UxTX and UxRX pins are configured as an
output and an input, respectively, overriding the TRIS
and LAT registe r bit setting s for the corres pondin g I/O
port pins. The UxTX pin is at logic ‘1’ when no
transmission is taking place.
16.2.2 DISABLING THE UART
The UAR T module is di sabled by cle aring the UAR TEN
bit in the UxMODE register. This is the default state
after any Reset. If the UART is disabled, all I/O pins
operate as port pins under the control of the LAT and
TRIS bits of the corresponding port pins.
Disab ling the UAR T module reset s the buf fers to empty
states. Any data characters in the buffers are lost and
the baud rate counter is reset.
All error and status flags associated with the UART
module are reset when the module is disabled. The
URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and
UTXBF bits are cleared, whereas RIDLE and TRMT
are set. Other control bits, including ADDEN,
URXISEL<1:0>, UTXISEL, as well as the UxMODE
and UxBRG registers, are not affected.
Clearing the UARTEN bit while the UART is active
aborts all pending transmissions and receptions and
resets the module, as defined above. Re-enabling the
UART restarts the UART in the same configuration.
16.2.3 ALTERNA TE I/O
The alternate I/O function is enabled by setting the
ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX
and UxARX pins (alternate transmit and alternate
receive pins, respectively) are used by the UART mod-
ule instead of the UxTX and UxRX pins. If ALTIO = 0,
the UxTX and UxRX pins are used by the UART
module.
16.2.4 SETTING UP DATA, PARITY AND
STOP BIT SELECTIONS
Control bit s, PDSEL<1 :0> in the U xMODE regi ster, are
used to select the data length and parity used in the
transmission. The data length may either be 8 bits with
even, odd or no parity, or 9 bits with no parity.
The STSEL bit determin es whether one or two S top bits
are used during data transmission.
The defa ult (powe r-on) settin g of the U ART is 8 bits, n o
parity and 1 Stop bit (typically represented as 8, N, 1).
16.3 Transmitting Data
16.3.1 TRANSMITTING IN 8-BIT DATA
MODE
The following steps must be performed in order to
transmit 8-bit da ta:
1. Set up the UART:
First, the data length, parity and number of Stop
bits must be selected. Then, the transmit and
receive interrupt enable and priority bits are set
up in the UxMODE and UxSTA registers. Also,
the appropriate baud rate value must be written
to the UxBRG register.
2. Enable the UART by setting the UARTEN bit
(UxMODE<15>).
3. Set the UTXEN bit (UxSTA<10>), thereby
enabling a transmission.
4. Write the byte to be t ransmitted to the lower byte
of UxTXREG. The value is transferred to the
Transmit Shift register (UxTSR) immediately,
and the se rial bit stream starts shifting out d uring
the next rising edge of the baud clock. Alterna-
tively, the dat a byte can be written wh ile UTXEN
= 0, following which, the user can set UTXEN.
This ca uses t he seri al bit s tream to begi n imm e-
diately because the baud clock starts from a
cleared state.
5. A transmit interrupt is generated, depending on
the value of the interrupt control bit, UTXISEL
(UxSTA<15>).
16.3.2 TRANSMITTING IN 9-BIT DATA
MODE
The sequence of steps involved in the transmission of
9-bit data is similar to 8-bit transmission, except that a
16-bit data word (of which the upper 7 bits are always
clear) must be written to the UxTXREG register.
16.3.3 TRANSMIT BUFFER (UXTXB)
The transmit buffer is 9 bits wide and 4 characters
deep. Including the Transmit Shift register (UxTSR),
the user effectively has a 5-deep FIFO (First-In, First-
Out) buffer. The UTXBF status bit (UxSTA<9>)
indicates whether the transmit buffer is full.
If a user attempts to write to a full buffer, the new data
is not accepted into the FIFO, and no data shift occurs
within the buffer. This enables recovery from a buffer
overrun condition.
The FIFO is reset during any device Reset but is not
affected when the device enters or wakes up from a
power-saving mode.
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DS70138G-page 106 2010 Microchip Technology Inc.
16.3.4 TRANSMIT INTERRUPT
The transmit interrupt flag (U1TXIF or U2TXIF) is
located in the corresponding interrupt flag register.
The transmitter generates an edge to set the UxTXIF
bit. The cond itio n for gene rati ng the in terr upt depe nds
on the UTXISEL control bit:
a) If UTXISEL = 0, an interrupt is generated when
a word is transferred from the transmit buffer to
the Transmit Shift register (UxTSR). Th is means
that the transmit buffer has at least one empty
word.
b) If UTXISEL = 1, an interrupt is generated when
a word is transferred from the transmit buffer to
the Transmit Shift register (UxTSR) and the
transmit buffer is empty.
Switching between the two Interrupt modes during
operation is possible and sometimes offers more
flexibility.
16.3.5 TRANSMIT BREAK
Setting the UTXBRK bit (UxSTA<11>) causes the
UxTX line to be driven to logic ‘0’. The UTXBRK bit
overrides all transmission activity. Therefore, the user
should generally wait for the transmitter to be Idle
before setting UTXBRK.
To send a Break character , the UTXBRK bit must be set
by software and must remain set for a minimum of
13 baud clock cycles. The UTXBRK bit is then cleared
by software to generate Stop bits. The user must wait
for a duration of at least one or two baud clock cycles
in order to ensure a valid Stop bit(s) before reloading
the UxTXB, or sta rtin g othe r transm it ter activity. T ran s-
mission of a Break character does not generate a
transmit interrupt.
16.4 Receiving Data
16.4.1 RECEIVING IN 8-BIT OR 9-BIT
DATA MODE
The following steps must be performed while receiving
8-bit or 9-bit data:
1. Set up the UART (see Section 16.3.1
“Transmitting in 8-Bit Data Mode”).
2. Enable the UART (see Section 16.3.1
“Transmitting in 8-Bit Data Mode”).
3. A receive interrupt is generated when one or
more data words have been received, depend-
ing on the receiv e i nterrupt set tin gs specified b y
the URXISEL bits (UxSTA<7:6>).
4. Read the OERR bit to determine if an overrun
error has occ urred. The OERR bit must be reset
in software.
5. Read the received data from UxRXREG. The act
of reading UxRXREG moves the next word to
the top of the receive FIFO, and the PERR and
FER R values are updated.
16.4.2 RECEIVE BUFFER (UXRXB)
The receive buffer is 4 words deep. Including the
Receive Shift register (UxRSR), the user effectively
has a 5-word deep FIFO buffer.
URXDA (UxSTA<0>) = 1 indicates that the receive
buffer has data available. URXDA = 0 means that the
buff er is empty . If a user attemp ts to read an empty buf-
fer, the old values in the buffer are read and no data
shift occurs within the FIFO.
The FIFO is reset during any device Reset. It is not
affected when the device enters or wakes up from a
power-saving mode.
16.4.3 RECEIVE INTERRUPT
The receive interrupt flag (U1RXIF or U2RXIF) can be
read from the c orresp onding interru pt fla g regis ter. The
interrupt flag is set by an edge generated by the
rece iver. The co nditi on f or se tti ng t he re ceiv e int err upt
flag depends on the settings specified by the
URXISEL<1:0> (UxSTA<7:6>) control bits.
a) If URXISEL<1:0> = 00 or 01, an interrup t is gen-
erated every time a data word is transferred
from the Receive Shift register (UxRSR) to the
receive buffer. There may be one or more
charact ers in the receive buffer.
b) If URXISEL<1:0> = 10, an interrupt is generated
when a word is transferred from the Receive Shif t
register (UxRSR) to the receive buffer , which as a
result of the transfer, contains 3 characters.
c) If URXISEL<1:0> = 11, an interrupt is set when
a word is transferred from the Receive Shift
register (Ux R SR) to th e rec ei ve buffer, which as
a result of the transfer, contains 4 characters
(i.e., becom es full).
Switching between the Interrupt modes during opera-
tion is possible, though generally not advisable during
normal operation.
16.5 Reception Error Handling
16.5.1 RECEIVE BUFFER OVERRUN
ERROR (OERR BIT)
The OERR bit (UxSTA<1>) is set if all of the following
conditions occur:
a) The receive buffer is full.
b) The Receive Shift register is full, but unable to
transfer the character to the receive buffer.
c) The Stop bit of the character in the UxRSR is
detected, indicating that the UxRSR needs to
transfer the character to the buffer.
Once OERR is set, no further data is shifted in UxRSR
(until the OERR bit is cleared in software or a Reset
occurs). The data held in UxRSR and UxRXREG
remains valid.
2010 Microchip Technology Inc. DS70138G-page 107
dsPIC30F3014/4013
16.5.2 FRAMING ERROR (FERR)
The FERR bit (UxSTA<2>) is set if a ‘0’ is detected
instead of a Stop bit. If two Stop bits are selected, both
S top bits must be ‘1’; otherwise, FERR is set. The read-
only FERR bit is buffered along w it h the rec ei ve d data;
it is cleared on any Reset.
16.5 .3 PARITY ERROR (PERR)
The PERR bit (UxSTA<3>) is set if the parity of the
received word is incorrect. This error bit is applicable
only if a Parity mode (odd or even) is selected. The
read-only PERR bit is buffered along with the received
data bytes; it is cleared on any Reset.
16.5.4 IDLE STATUS
When the receiver is active (i.e., between the initial
detecti on of the Start bit and the comp letion of the Stop
bit), the RIDLE bit (UxST A<4>) is ‘0’. Between the com-
pletion of the Stop bit and dete ction of the next S t art bit,
the RIDLE bit is ‘1’, indicating that the UART is Idle.
16.5.5 REC EIV E BRE AK
The rece iver counts and expect s a certain number of bit
times based on the values programmed in the PDSEL
(UxMODE<2:1>) and STSEL (UxMODE<0>) bits.
If the break is longer than 13 bit times, the reception is
considered complete after the number of bit times
specif ied by PDSEL and STSEL. The URXDA bit is se t,
FERR is set, zeros are loaded into the receive FIFO,
interrupts are generated if appropriate, and the RIDLE
bit is set.
When t he module rece ives a lon g Break s ignal a nd the
receive r has detected the S t art bit, the dat a bits and the
invalid Stop bit (which sets the FERR), the receiver
must wai t for a val id Sto p bit before looki ng for the next
Start bit. It cannot assume that the Break condition on
the line is the next Start bit.
Break is reg arded as a characte r containin g all ‘0’s with
the FERR bit set. The Break character is loaded into
the buf fer . No further reception can occur until a S top bit
is received. Note that RIDLE goes high when the Stop
bit has not yet been received.
16.6 Address Detect Mode
Setting the ADDEN bit (UxSTA<5>) enables this
special mode in which a 9th bit (URX8) value of ‘1’
identifies the received word as an address, rather than
data. This mode is only applicable for 9-bit data
communication. The URXISEL control bit does not
have any impact on interrupt generation in this mode
since an interrupt (if enabled) is generated every time
the received word has the 9th bit set.
16.7 Loopback Mode
Setting the LPBACK bit enables this special mode in
which the UxT X pin is int ernally conne cted to the UxRX
pin. When configured for the Loopback mode, the
UxRX pin is disconnected from the internal UART
rece ive lo gic. H owever, the Ux TX pin still functi ons as
in a normal operation.
To select this mode:
a) Configure UART for desired mode of operation.
b) Set LPBACK = 1 to enable Loopback mode.
c) Enable tran sm is si on as def ine d in Section 16.3
“Transmitting Data”.
16.8 Baud Rate Generator
The UART has a 16-bit Baud Rate Generator to allow
maximu m fl exib ilit y in b aud r ate ge nera tio n. Th e Baud
Rate Generator register (UxBRG) is readable and
writable. The baud rate is computed as follows:
BRG = 16-bit value held in UxBRG register
(0 through 65535)
FCY = Instruction Clock Rate (1/TCY)
The Baud Rate is given by Equation 16-1.
EQUATION 16-1: BAUD RATE
Therefore, the maximum baud rate possible is:
FCY/16 (if BRG = 0),
and the minimum baud rate possible is:
FCY/(16 * 65536).
With a full 16-bit Baud Rate Generator at 30 MIPS
operation, the minimum baud rate achievable is
28.5 bps.
Baud Rate = FCY/(16*(BRG+1))
dsPIC30F3014/4013
DS70138G-page 108 2010 Microchip Technology Inc.
16.9 Auto-Baud Support
To allow the system to determine baud rates of
received characters, the input can be optionally linked
to a capture input (IC1 for UART1, IC2 for UART2). To
enable this mode, the user must program the input
capture modul e t o dete ct the falli ng and risin g edge s of
the Start bit.
16.10 UART Operation During CPU
Sleep and Idle Modes
16.10.1 UART OPERATION DURING CPU
SLEEP MODE
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’. If
entry in to Slee p mod e occ urs whi le a tr ansmi ssio n is i n
progress, then the transmission is aborted. The UxTX
pin is driven to logic ‘1’. Similarly, if entry into Sleep
mode occurs while a reception is in progress, then the
reception is aborted. The UxSTA, UxMODE, transmit
and receive registers and buffers, and the UxBRG
register are not affected by Sleep mode.
If the W AKE bit (UxMODE <7>) is set before the device
enters Sleep mode, a falling edge on the UxRX pin
generates a receive interrupt. The Receive Interrupt
Select mode bit (URXISEL) has no effect for this func-
tion. If the receive interrupt is enabled, this wakes the
device up from Sleep. The UARTEN bit must be set in
order to generate a wake-up interrupt.
16.10.2 UART OPERATION DURING CPU
IDLE MODE
For the UART, the USIDL bit determines if the module
stops or continues operation when the device enters
Idle mode. If USIDL = 0, the module continues
operation during Idle mode. If USIDL = 1, the module
stops on Idle.
2010 Microchip Technology Inc. DS70138G-page 109
dsPIC30F3014/4013
TABLE 16-1: dsPIC30F3014/4013 UART1 REGISTER MAP(1)
TABLE 16-2: dsPIC30F3014/4013 UART2 REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
U1MODE 020C UARTEN —USIDL——ALTIO—— WAKE LPBACK ABAUD —— PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
U1STA 020E UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
U1TXREG 0210 — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu
U1RXREG 0212 — — — — — — — URX8 Receive Register 0000 0000 0000 0000
U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
U2MODE 0216 UARTEN —USIDL— — — — — WAKE LPBACK ABAUD —— PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
U2STA 0218 UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000
U2TXREG 021A — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu
U2RXREG 021C — — — — — — — URX8 Receive Register 0000 0000 0000 0000
U2BRG 021E Baud Rate Generator Prescaler 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 110 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 111
dsPIC30F3014/4013
17.0 CAN MODULE
17.1 Overview
The Controller Area Network (CAN) module is a serial
interface, useful for communicating with other CAN
modules or microcontroller devices. This interface/
protocol was designed to allow communications within
noisy env iro nm ents.
The C AN mo du le is a co mm un i ca tio n co ntr o lle r i mple -
menting the CAN 2.0 A/B protocol, as defined in the
BOSCH specification. The module supports CAN 1.2,
CAN 2.0A, CAN 2.0B Passive, and CAN 2.0B Active
version s of th e proto col. Th e mod ule im plement a tion i s
a full CAN system. The CAN specification is not cov-
ered within thi s data she et. The reader may refer to the
BOSCH CAN specification for further details.
The module features are as follows:
• Implementation of the CAN protocol CAN 1.2,
CAN 2.0A and CAN 2.0B
• Standard and extended data frames
• 0-8 bytes data length
• Programmable bit rate up to 1 Mbit/sec
• Support for remote frames
• Doubl e-bu f fe red receiver with two prioritiz ed
received message storage buffers (each buffer
may contain up to 8 bytes of data)
• 6 full (standard/extended identifier), acceptance
filters, 2 associated with the high-priority receive
buffer and 4 associated with the low-priority
rec eive buffer
• 2 full, acceptance filter masks, one each
associated with the high and low-priority receive
buffers
• Three transmit buffers with application specified
priori tization and abort c apabilit y (each buf fer may
contain up to 8 bytes of data)
• Programmable wake-up functionality with
integrated low-pass fil ter
• Programm abl e Loopback m ode su pp orts self -tes t
operation
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
• Programmable clock source
• Programmable link to input capture module (IC2,
for both CAN1 and CAN2) for time-stamping and
netw ork synchronizati on
• Low-power Sleep and Idle mode
The CAN bus modu le consist s of a protocol engi ne and
message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
17.2 Frame Types
The CAN module transmits various types of frames
which include data messages or remote transmission
requests, ini tiat ed by the us er, as other frames tha t a re
automatically generated for control purposes. The
following frame types are supported:
• Standard Data Frame:
A standard data frame is generated by a node
when the node wishes to transmit data. It includes
an 11-bit S t andard I dentifier (SID) b ut not an 18-bit
Extended Identifier (EID).
• Extended Data Frame:
An extended data frame is similar to a standard
data frame but includes an extended identifier as
well.
• Remote Frame:
It is possible for a destination node to request the
data from the source. For this purpose, the
destination node sends a remote frame with an
identifi er that matches the identifier of the required
data frame. The appropriate data source node
then sends a data frame as a response to this
remote request.
• Error Frame:
An error frame is generated by any node that
detects a bus error. An error frame consists of
2 fields: an error flag field and an error delimiter
field.
• Overload Frame:
An overl oad fram e can b e generat ed by a node a s
a re sult of 2 condi tions. First, the node detec ts a
dominant bit during interframe space which is an
illegal condition. Second, due to internal condi-
tions, the node is not yet able to start reception of
the next message. A node may generate a
maximum of 2 sequential overload frames to
delay the start of the next message.
• Inter frame Space:
Interframe space separates a proceeding frame
(of wha tever t ype) from a follo wing da ta or remo te
frame.
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
dsPIC30F3014/4013
DS70138G-page 112 2010 Microchip Technology Inc.
FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
Acceptance Filter
RXF2(2)
R(2)
X
B
1
A
c
c
e
p
t
A
c
c
e
p
t
Identifier
Data Field Data Field
Identifier
Acceptance Mas k
RXM1(2)
Acceptance Filter
RXF3(2)
Acceptance Filter
RXF4(2)
Acceptance Filter
RXF5(2)
M
A
B
Acceptance Mask
RXM0(2)
Acceptance Filter
RXF0(2)
Acceptance Filter
RXF1(2)
R(2)
X
B
0
TXREQ
TXB2(2)
TXABT
TXLARB
TXERR
MESSAGE
Message
Queue
Control Transmit Byte Sequencer
TXREQ
TXB1(2)
TXABT
TXLARB
TXERR
MESSAGE
TXREQ
TXB0(2)
TXABT
TXLARB
TXERR
MESSAGE
Receive ShiftTransmit Shift
Receive
Error
Transmit
Error
Protocol
RERRCNT
TERRCNT
Err Pas
Bus Off
Finite
State
Machine
Counter
Counter
Transmit
Logic
Bit
Timing
Logic
CiTX(1) CiRX(1)
Bit Timing
Generator
PROTOCOL
ENGINE
BUFFERS
CRC Check
CRC Generator
Note 1: i = 1 or 2 refers to a particular CAN module (CAN1 or CAN2).
2: These are conceptual groups of registers, not SFR names by themselves.
2010 Microchip Technology Inc. DS70138G-page 113
dsPIC30F3014/4013
17.3 Modes of Operation
The CAN module can operate in one of several operation
modes selected by the user . These modes include:
• Initialization mode
• Disable mode
• Normal Operation mode
• List en On ly mode
• Loopback mode
• Error Recognition mode
Modes are requested by setting the REQOP<2:0> bits
(CiCTRL<10:8>). Entry into a mode is Acknowledged
by mon itoring the OPM ODE< 2:0> bi t s (C iCTRL<7:5>).
The module does not change the mode and the
OPMODE bits until a change in mode is acceptable,
generally during bus Idle time which is defined as at
least 11 consecutive recessive bits.
17.3.1 INITIALIZATION MODE
In the Ini tia lizati on mo de, the m odule does not tr ansmit
or receive. The error counters are cleared and the int er-
rupt flags remain unchanged. The programmer has
access to Configuration registers that are access
restrict ed in other modes. The module protects the user
from accidentally violating the CAN protocol through
programming errors. All registers that control the con-
figuration of the module can not be modified while the
module is on-line. The CAN module is not allowed to
enter the Configuration mode while a transmission is
ta ki ng pl ace . The C onfi gu r atio n mo de serves as a lock
to protect the following registers.
• All Module Control registers
• Baud Rate and Interrupt Configuration registers
• Bus Timing registers
• Identifier Acceptance Filter registers
• Identifier Acceptance Mask registers
17.3.2 DISABLE MODE
In Disable mode, the module does not transmit or
receive . The mo dule has the ability to set the W AKIF b it
due to bus activity, however, any pending interrupts
remain and the error counters retain their value.
If the REQOP<2:0> bits (CiCTRL<10:8>) = 001, the
module enters the Module Disable mode. If the module is
active, the module waits for 1 1 recessive bits on the CAN
bus, detects that condition as an Idle bus, and then
accepts the module disable command. When the
OPMODE<2:0> bits (CiCTRL<7:5>) = 001, that
indicates whether the module successfully went into
Module Disable mode. The I/O pins revert to normal I/O
function when the mod ule is in the Module Disable mo de.
The module can be programmed to apply a low-pass
filter fun ction to the CiRX i nput l ine whil e the m odule or
the CPU is in Sleep mode. The WAKFIL bit
(CiCFG2<14>) enables or disables the filter.
17.3.3 NORMAL OPERATION MODE
Normal Operating mode is selected when
REQOP<2:0> = 000. In this mode, the module is acti-
vated and the I/O pins assu me th e CAN bu s fun cti ons .
The module transmits and receives CAN bus
messages via the CxTX and CxRX pins.
17.3.4 LIST EN ON LY MODE
If the Li st en O nl y mode is activa ted , the m odule on the
CAN bus is passive. The transmitter buffers revert to
the port I/O function. The receive pins remain inputs.
For the rec eiv er, no error flags or Ac kn owledge sign al s
are sent. The error counters are deactivated in this
state. The Listen Only mode can be used for detecting
the baud rate on the CAN bus. To use this, it is neces-
sary that there are at least two further nodes that
communicate with each other.
17.3.5 LISTEN AL L MESS A GES MODE
The module can be set to ignore all errors and receive
any message. The Listen All Messages mode is acti-
vated by se ttin g the R EQO P<2:0> bits t o ‘111’. In this
mode, the data which is in the message assembly buf-
fer until the time an error occurred, is copied in the
receive buffer and can be read via the CPU interface.
17.3.6 LOOPBACK MODE
If the Loopback mode is activated, the module
connects the internal transmit signal to the internal
receive signal at the module boundary. The transmit
and receive pins revert to their port I/O function.
Note: Typically, if the CAN module is allowed to
transmit in a particular mode of operation
and a transmission is requested immedi-
ately after the CAN module has been
placed in th at mod e of o per ation, the m od-
ule waits for 11 consecutive recessive bits
on the bus before starting transmission. If
the user switches to Disable mode within
this 11-bit period, then this transmission is
aborted and the corresponding TXABT bit
is set and TXREQ bit is cleared.
dsPIC30F3014/4013
DS70138G-page 114 2010 Microchip Technology Inc.
17.4 Message Reception
17.4.1 REC EIV E BUFF ERS
The CAN bus module has 3 receive buffers. However,
one of the receiv e b uffers is al w ays com mi tted to mon-
itoring the bus for incoming messages. This buffer is
called the Message Assembly Buffer (MAB). So there
are 2 receive buffers visible, denoted as RXB0 and
RXB1, that can essentially instantaneously receive a
complete message from the protocol engine.
All messages are assembl ed by the MAB and are trans-
ferred to the RXBn buffers only if the acceptance filter
criterion are met. When a message is received, the
RXnIF flag (CiINRF<0> or CiINRF<1>) is set. This bit
can only be set by the module when a message is
received. The bit is cleared by the CPU when it has com-
pleted processing the message in the buffer. If the
RXnIE bit (CiINTE<0> or CiINTE<1>) is set, an interrupt
is generated when a message is received.
RXF0 and RXF1 filters with RXM0 mask are associated
with RXB0. The filters RXF2, RXF3, RXF4 and RXF5,
and the mask RXM1 are associated with RXB1.
17.4.2 MESSAGE ACCEPTANCE FILTERS
The me ssage acc eptance filters and masks ar e used to
determine if a message in the message assembly buf-
fer shoul d be l oaded i nto eithe r of t he rec eive b uffer s.
Once a valid m essage has been received into the Mes-
sage Ass embly Buf fer (M AB), the id entifi er fields of th e
messa ge ar e co mpared to the filte r val ue s. If th ere i s a
match, that message is loaded into the appropriate
rec eive buffer.
The acceptance filter looks at incoming messages for
the RXIDE bit (CiRXnSID<0>) to determine how to
compare the identifiers. If the RXIDE bit is clear, the
message is a standard frame and only filters with the
EXIDE bit (CiRXFnSID<0>) clear are compared. If the
RXIDE bit is set, the message is an extended frame
and only filters with the EXIDE bit set are compared.
17.4.3 MESSAGE ACCEPTANCE FILTER
MASKS
The mask bits e ssential ly determi ne which bit s to appl y
the filter to. If any mask bit is set to a zero, that bit is
automatically accepted regardless of the filter bit.
There are two programmable acceptance filter masks
assoc iated with the receive bu ffers, one for each bu ffer .
17.4.4 RECEIVE OVERRUN
An overrun condition occurs when the Message
Assembly Buffer (MAB) has assembled a valid
received message, the message is accepted through
the acceptance filters, and when the receive buffer
associated with the filter has not been designated as
clear of the previous message.
The overrun error flag, RXnOVR (CiINTF<15> or
CiINTF<14>), and the ERRIF bit (CiINTF<5>) are set
and the message in the MAB is discarded.
If the DBEN bit is clear , RXB1 and RXB0 operate inde-
pendently. When this is the case, a message intended
for RXB0 is not dive rted into RXB1 if RXB0 con tains an
unread message, and the RX0OVR bit is set.
If the DBEN bit is set, the overrun for RXB0 is handled
differently. If a valid mes sa ge is r ece iv ed for RXB0 an d
RXFUL = 1 it indicates that RXB0 is full and
RXFUL = 0 indicates that RXB1 is empty, the messag e
for RXB0 is loaded into RXB1. An overrun error is not
generated for RXB0. If a valid message is received for
RXB0 and RXFUL = 1, indicates that both RXB0 and
RXB1 are full, the message is lost and an overrun is
indicated for RXB1 .
17.4.5 RECEIVE ERRORS
The CAN module detects the following receive errors:
• Cyclic Redundancy Check (CRC) error
• Bit Stuffing error
• Invalid Message Rece ive Er ror
The receive error counter is incremented by one in
case one of these errors occur. The RXWAR bit
(CiINTF<9>) indicates that the receive error counter
has reached the CPU warning limit of 96 and an
interrupt is genera ted.
17.4.6 RECEIVE INTERRUPTS
Receive interrupts can be divided into 3 major groups,
each including various conditions that generate
interrupts:
• Receive Interrupt:
A message has been successfully received and
loaded into one of the receive buffers. This inter-
rupt is activated immediately after receiving the
End-of-Frame (EOF) field. Reading the RXnIF flag
indicates which receive buffer caused the
interrupt.
• Wake-up Interrupt:
The CAN module has woken up from Disable
mode or the device has woken up from Sleep
mode.
2010 Microchip Technology Inc. DS70138G-page 115
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• Receive Error Interrupts:
A receive error in terrupt is indicated by the ERRIF
bit. This bit shows that an error condition
occurred. The source of the error can be deter-
mined by checking the bits in the CAN Interrupt
register, CiINTF.
- Invalid Message Received:
If any type of error occurred during reception of
the last message, an error is indicated by the
IVRIF bit.
- Receiver Overrun:
The RXnOVR bit indicates that an overrun
conditi on oc curred.
- Receiver Warning:
The R XW A R bit indic ates that th e Re ceiv e Error
Counter (RERRCNT<7:0>) has reached the
warning limit of 96.
- Receiver Error Passive:
The RXEP bit indicates that the Receive Error
Counter has exceeded the error passive limit of
127 and the modul e h as go ne into erro r p assive
state.
17.5 Message Transmission
17.5.1 TRAN SMI T BUFFERS
The CAN module has three transmit buffers. Each of
the thre e buf fers occ upies 14 bytes o f data . Eight o f the
bytes a re the maximum 8 bytes of the tran smitted mes-
sage. Five bytes hold the standard and extended
identifiers and other message arbitration information.
17.5.2 TRANSMIT MESS AGE PRIORI T Y
Transmit priority is a prioritization within each node of
the pending transmittable messages. There are
4 levels of transmit priority. If TXPRI<1:0>
(CiTXnCON<1:0>, where n = 0, 1 or 2, represents a
parti cu lar tran sm it buf f er) for a p a r ticula r mes s age buf-
fer is set to ‘11’, that buffer has the highest priority. If
TXPRI<1:0> for a particular message buffer is set to
‘10’ or ‘01’, that buffer has an intermediate priority. If
TXPRI<1:0 > for a parti cular message buffe r is ‘00’, that
buffe r has the lowest prior ity.
17.5.3 TRANSMISSION SEQUENCE
To initiate transmission of the message, the TXREQ bit
(CiTXnCON<3>) must be set. The CAN bus module
resolves any timing conflicts between setting of the
TXREQ bit and the S tart-of-Frame (SOF), ensuring that if
the priority was changed, it is resolved correctly before the
SOF occurs. When TXREQ is set, the TXABT
(CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR
(CiTXnCON<4>) flag bits are automatically cleared.
Setting TXREQ bit simply flags a message buffer as
enqueued for transmission. When the module detects
an available bus, it begins transmitting the message
which has been determi ned to have the highest priori ty .
If the transmission completes successfully on the first
attempt, the TXREQ bit is cl eared autom aticall y and an
interrupt is generated if TX1IE was set.
If the message transmission fails, one of the error
condition flags is set, and the TXREQ bit remains set,
indica ting that the message is sti ll pending for tra nsmis-
sion. If the message encountered an error condition
during the transmission attempt, the TXERR bit is set,
and the error condition may cause an interrupt. If the
message loses arbitration during the transmission
attempt, the TXLARB bit is set. No interrupt is
generated to signal the loss of arbitration.
17.5.4 ABORTING MESSAGE
TRANSMISSION
The system can also abort a message by clearing the
TXREQ bit associated with each message buffer.
Setting the ABAT bit (CiCTRL<12>) requests an abort
of all pending messages. If the message has not yet
started transmission, or if the message started but is
interrupte d by loss of arbitratio n or an error, the abort is
processed. The abort is indicated when the module
sets the TXABT bit and the TXnIF flag is not
automatically set.
17.5.5 TRANSMISSION ERRORS
The CAN module detects the following transmission
errors:
• Acknowledge error
• Form error
• Bit error
These tra ns mi ssio n e rrors do not necess ari ly gen era te
an interrupt but are indicated by the transmission error
counter. However, each of these errors causes the
transmission error counter to be incremented by one.
Once the value of the error counter exceeds the value
of 96, the ERRIF (CiINTF<5>) and the TXWAR bit
(CiINTF<10>) are set. Once the value of the error
counter exceeds the value of 96, an interrupt is
generate d and the TXW A R bit in the Erro r Flag regist er
is set.
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DS70138G-page 116 2010 Microchip Technology Inc.
17.5.6 TRANSMIT INTERRUPTS
T ransmit interrupts can be divided into 2 major groups,
each including various conditions that generate
interrupts:
• Transmit Interrupt:
At least one of the three transmit buffers is empty
(not scheduled) and can be loaded to schedule a
message for transmission. The TXnIF flags are
read to determine which transmit buffer is
available and caused the interrupt.
• Transmit Error Interrupts:
A transmission error interrupt is indicated by the
ERRIF flag. This flag shows that an error condition
occurred. The source of the error can be
determi ned by check ing the error fl ags in the CAN
Interrupt reg ister , CiINTF. The flags in this reg ister
are related to receive and transmit errors.
- Transmitter Warning Interrupt:
The TXW AR bit in dicates that the T ransmi t Error
Counter has reached the CPU warning limit of
96.
- Transmitter Error Passive:
The TXEP bit (CiINTF<12>) indicates that the
Transmit Error Counter has exceeded the error
pas siv e lim it of 127 an d the modul e has gone to
error passive state.
- Bus Off:
The TXBO bit (CiINTF<13>) indicates that the
Transmit Error Counter (TERRCNT<7:0>) has
exceeded 255 and the module has gone to the
bus off state .
17.6 Baud Rate Setting
All nodes on any particular CAN bus must have the
same nomin al bit rate. In ord er to set the baud rate, the
following parameters have to be initialized:
• Syn chronization Ju mp Width
• Baud Rate Prescaler
• Phase Segments
• Length determination of Phase Segment 2
• Sample Point
• Prop ag ati on Segmen t bits
17.6.1 BIT TIMING
All controllers on the CAN bus must have the same
baud rate and bit length. However, different controllers
are not required to have the same master oscillator
clock. At different clock frequencies of the individual
controllers, the baud rate has to be adjusted by
adjusti ng the num be r of time quan t a in eac h segm en t.
The nomi nal bit time can be though t of as being div ided
into separate non-overlapping time segments. These
segments are shown in Figure 17-2.
• Synchronization Segment (Sync Seg)
• Propagation Time Segment (Prop Seg)
• Phase Segment 1 (Phase1 Seg)
• Phase Segment 2 (Phase2 Seg)
The time segments and also the nominal bit time are
made up of integer units of time called time quanta or
TQ. By definition, the nominal bit time has a minimum
of 8 TQ and a maximum of 25 TQ. Also, by definition,
the minimum nominal bit time is 1 sec corresponding
to a maximum bit rate of 1 MHz.
FIGURE 17-2: CAN BIT TIMING
Input Signal
Sync Prop
Segment Phase
Segment 1 Phase
Segment 2 Sync
Sample Point
TQ
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17.6.2 PRESCALER SETTING
There is a programmable prescaler with integral values
ranging f rom 1 to 64 in additi on to a fixed divi de-by-2 for
clock generation. The Time Quantum (TQ) is a fixed
unit of time deri ve d f rom th e o sc ill ato r pe rio d, sho wn in
Equation 17-1, where FCAN is FCY (if the CANCKS bit
is set) or 4FCY (if CA NC K S i s cle a r).
EQUATION 17-1: TIME QUANTUM FOR
CLOCK GENERATION
17.6.3 PROPAGATION SEGMENT
This p art of t he bit time is u sed to com pensa te phy sica l
delay ti me s withi n the ne twork . These delay times con-
sist of the signal propagation time on the bus line and
the internal delay time of the nodes. The propagation
segment can be programmed from 1 TQ to 8 TQ by
setting the PRSEG<2:0> bits (CiCFG2<2:0>).
17.6.4 PHASE SEGMENTS
The phase segments are used to optimally locate the
sampling of the received bit within the transmitted bit
time. The sampling point is between Phase1 Seg and
Phase2 Seg. These segmen ts are lengthen ed or sho rt-
ened by res ynchronizatio n. The end of the Phase1 Seg
determines the sampling point within a bit period. The
segment is programmable from 1 TQ to 8 TQ. Phase2
Seg provides delay to the next transmitted data transi-
tion. The s egm en t is pro gra mm abl e from 1 TQ to 8 TQ,
or it may be defined to be equal to the greater of
Phase1 Seg or the in form ati on pro ce ssin g tim e (2 TQ).
The Phase1 Seg is initialized by setting bits
SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is
initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).
The following requirement must be fulfilled while setting
the lengths of the phase segments:
Prop Seg + Phase1 Seg > = Phase2 Seg
17.6 .5 SAMPLE POINT
The sample point is the point of time at which the bus
level is read and interpreted as the value of that respec-
tive bi t. The loca tio n i s at the end of Phas e1 Seg. If the
bit timin g is slow and cont ains many TQ, it is possible to
specify multiple sampling of the bus line at the sample
point. The level determin ed by the CAN bus the n corre-
sponds to the result from the majority decision of three
values. The majority samples are taken at the sample
point and twice before with a distance of TQ/2. The
CAN module allows the user to choose between
sampling three times at the same point, or once at the
same point by setting or clearing the SAM bit
(CiCFG2<6>).
Typically, the sampling of the bit should take place at
about 60-70% through the bit time depending on the
system parameters.
17.6.6 SYNCHRONIZATION
To compensate for phase shifts between the oscillator
frequencies of the different bus stations, each CAN
controller must be able to sync hronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logi c compares the
locatio n of the edge to t he ex pecte d tim e (sy nchron ous
segment). The circuit then adjusts the values of
Phase1 Seg and Phase2 Seg. There are two
mechanisms used to synchronize.
17.6.6. 1 Hard Synchr oni za tio n
Hard synchronization is only done when there is a
recessive to dominant edge during bus Idle, indicating
the start of a message. After hard synchronization, the
bit-time counters are restarted with the synchronous
segment. Hard synchronization forces the edge which
has caused the hard synchronization to lie within the
synchronization segment of the restarted bit time. If a
hard synchronization is done, there will not be a
resynchronization within that bit time.
17.6.6.2 Resynchronization
As a result of resynchronization, Phase1 Seg may be
lengthened or Phase2 Seg may be shortened. The
amount of lengthening or shortening of the phase buf-
fer segment has an upper bound known as the syn-
chronization jump width, and is specified by the
SJW<1:0> bits (CiCFG1<7:6>). The value of the
synchronization jump width is added to Phase1 Seg or
subtracted from Phase2 Seg. The resynchronization
jump width is programmable between 1 TQ and 4 TQ.
The following requirement must be fulfilled whi le setting
the SJW<1:0> bits:
Phase2 Seg > Synchronizat ion Jump Width
Note: FCAN must not exceed 30 MHz. If
CANCKS = 0, then FCY must not exceed
7.5 MHz.
TQ = 2 (BRP<5:0> + 1)/FCAN
dsPIC30F3014/4013
DS70138G-page 118 2010 Microchip Technology Inc.
TABLE 17-1: dsPIC30F4013 CAN1 REGISTER MAP(1)
SFR Name Addr . Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Stat e
C1RXF0SID 0300 — — — Recei ve Accept anc e Filter 0 Stand ard Iden tifier< 10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF0EIDH 0302 — — — — Receive Accept ance Filter 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXF0EIDL 0304 Receive Acceptance Fil ter 0 Extended Ident ifier<5: 0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF1SID 0308 — — — Recei ve Accept anc e Filter 1 Stand ard Iden tifier< 10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF1EIDH 030A — — — — Receive Acceptance Filter 1 Extended Identifi er<17:6> 0000 uuuu uuuu uuuu
C1RXF1EIDL 030C Receive Ac ceptanc e Filter 1 Extended Ident ifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF2SID 0310 — — — Recei ve Accept anc e Filter 2 Stand ard Iden tifier< 10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF2EIDH 0312 — — — — Receive Accept ance Filter 2 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXF2EIDL 0314 Receive Acceptance Fil ter 2 Extended Ident ifier<5: 0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF3SID 0318 — — — Recei ve Accept anc e Filter 3 Stand ard Iden tifier< 10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF3EIDH 031A — — — — Receive Acceptance Filter 3 Extended Identifi er<17:6> 0000 uuuu uuuu uuuu
C1RXF3EIDL 031C Receive Ac ceptanc e Filter 3 Extended Ident ifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF4SID 0320 — — — Recei ve Accept anc e Filter 4 Stand ard Iden tifier< 10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF4EIDH 0322 — — — — Receive Accept ance Filter 4 Extended Identifier<17:6> 0000 uuuu uuuu uuuu
C1RXF4EIDL 0324 Receive Acceptance Fil ter 4 Extended Ident ifier<5: 0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXF5SID 0328 — — — Recei ve Accept anc e Filter 5 Stand ard Iden tifier< 10:0> — EXIDE 000u uuuu uuuu uu0u
C1RXF5EIDH 032A — — — — Receive Acceptance Filter 5 Extended Identifi er<17:6> 0000 uuuu uuuu uuuu
C1RXF5EIDL 032C Receive Ac ceptanc e Filter 5 Extended Ident ifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXM0SID 0330 — — — Receive Accept ance Mas k 0 Standard Identifier<10:0> —MIDE000u uuuu uuuu uu0u
C1RXM0EIDH 0332 — — — — Receive Accept anc e Mask 0 E xtended Id entif ier<17:6> 0000 uuuu uuuu uuuu
C1RXM0EIDL 0334 Receive Acceptan ce Mas k 0 Ex tended I dentifi er<5:0> — — — — — — — — — — uuuu uu00 0000 0000
C1RXM1SID 0338 — — — Receive Accept ance Mas k 1 Standard Identifier<10:0> —MIDE000u uuuu uuuu uu0u
C1RXM1EIDH 033A — — — — Receive Acceptanc e Mask 1 Ext ended Id entifier< 17:6> 0000 uuuu uuuu uuuu
C1RXM1EIDL 033C Receive Accept an ce Mask 1 Extended I denti fier<5:0 > — — — — — — — — — — uuuu uu00 0000 0000
C1TX2SID 0340 Transmit Buf fer 2 St andard Id entifier<10:6> — — — T ra nsmit Buf fer 2 Sta ndard Id entifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX2EID 0342 Tr ansmit B uffe r 2 E xtended Iden tif ier< 17:14> — — — — T ra nsmit Buf fer 2 Extended Ident ifier< 13:6> uuuu 0000 uuuu uuuu
C1TX2DLC 0344 Tra nsmit B uf fer 2 E xtended Ident ifier< 5:0> TXRTR TXRB1 TXRB0 DLC<3: 0> — — — uuuu uuuu uuuu u000
C1TX2B1 0346 Transmit Buf fer 2 Byte 1 T ransmit Buf fer 2 Byte 0 uuuu uuuu uuuu uuuu
C1TX2B2 0348 Transmit Buf fer 2 Byte 3 T ransmit Buf fer 2 Byte 2 uuuu uuuu uuuu uuuu
C1TX2B3 034A T ransmit Buf fer 2 Byte 5 T ransmit Buf fer 2 Byte 4 uuuu uuuu uuuu uuuu
C1TX2B4 034C T ran smit Bu ffer 2 B yte 7 Tran smit Bu f fer 2 B yte 6 uuuu uuuu uuuu uuuu
C1TX2CON 034E — — — — — — — — — TXABT TXLARB TXERR TXREQ —TXPRI<1:0>0000 0000 0000 0000
C1TX1SID 0350 Transmit Buf fer 1 St andard Id entifier<10:6> — — — T ra nsmit Buf fer 1 Sta ndard Id entifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX1EID 0352 Tr ansmit B uffe r 1 E xtended Iden tif ier< 17:14> — — — — T ra nsmit Buf fer 1 Extended Ident ifier< 13:6> uuuu 0000 uuuu uuuu
C1TX1DLC 0354 Tra nsmit B uf fer 1 E xtended Ident ifier< 5:0> TXRTR TXRB1 TXRB0 DLC<3: 0> — — — uuuu uuuu uuuu u000
Legend: u = uninitial ized bi t; — = unimplemented bit , read as ‘ 0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS7 0046) fo r descript ions of regis ter bit f ields.
2010 Microchip Technology Inc. DS70138G-page 119
dsPIC30F3014/4013
C1TX1B1 0356 Transmit Buf fer 1 Byte 1 T ransmit Buf fer 1 Byte 0 uuuu uuuu uuuu uuuu
C1TX1B2 0358 Transmit Buf fer 1 Byte 3 T ransmit Buf fer 1 Byte 2 uuuu uuuu uuuu uuuu
C1TX1B3 035A T ransmit Buf fer 1 Byte 5 T ransmit Buf fer 1 Byte 4 uuuu uuuu uuuu uuuu
C1TX1B4 035C T ran smit Bu ffer 1 B yte 7 Tran smit Bu f fer 1 B yte 6 uuuu uuuu uuuu uuuu
C1TX1CON 035E — — — — — — — — — TXABT TXLARB TXERR TXREQ —TXPRI<1:0>0000 0000 0000 0000
C1TX0SID 0360 Transmit Buf fer 0 St andard Id entifier<10:6> — — — Transmit Buf f er 0 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu
C1TX0EID 0362 Trans mit Buf fer 0 Extended I denti fier <17 :14> — — — — Transmit B uf fer 0 E xtended Identifie r<13:6> uuuu 0000 uuuu uuuu
C1TX0DLC 0364 Tra nsmit B uf fer 0 E xtended Ident ifier< 5:0> TXRTR TXRB1 TXRB0 DLC<3: 0> — — — uuuu uuuu uuuu u000
C1TX0B1 0366 Transmit Buf fer 0 Byte 1 T ransmit Buf fer 0 Byte 0 uuuu uuuu uuuu uuuu
C1TX0B2 0368 Transmit Buf fer 0 Byte 3 T ransmit Buf fer 0 Byte 2 uuuu uuuu uuuu uuuu
C1TX0B3 036A T ransmit Buf fer 0 Byte 5 T ransmit Buf fer 0 Byte 4 uuuu uuuu uuuu uuuu
C1TX0B4 036C T ran smit Bu ffer 0 B yte 7 Tran smit Bu f fer 0 B yte 6 uuuu uuuu uuuu uuuu
C1TX0CON 036E — — — — — — — — — TXABT TXLARB TXERR TXREQ —TXPRI<1:0>0000 0000 0000 0000
C1RX1SID 0370 — — — Receive Buf fer 1 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu
C1RX1EID 0372 — — — — Receive Buf f er 1 Ext ended Id entifier <17:6> 0000 uuuu uuuu uuuu
C1RX1DLC 0374 Recei ve Buf fe r 1 Exte nded Ide ntifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C1RX1B1 0376 Receive Buf fer 1 Byte 1 Receive Buf fer 1 Byte 0 uuuu uuuu uuuu uuuu
C1RX1B2 0378 Receive Buf fer 1 Byte 3 Receive Buf fer 1 Byte 2 uuuu uuuu uuuu uuuu
C1RX1B3 037A Receive Buf fer 1 Byte 5 Receive Buf fer 1 Byte 4 uuuu uuuu uuuu uuuu
C1RX1B4 037C Receive Buffer 1 Byte 7 Receive Buf fer 1 Byte 6 uuuu uuuu uuuu uuuu
C1RX1CON 037E — — — — — — — —RXFUL— — — RXRTRRO FILHIT<2:0> 0000 0000 0000 0000
C1RX0SID 0380 — — — Receive Buf fer 0 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu
C1RX0EID 0382 — — — — Receive Buf fer 0 E xtended Ident ifier< 17:6> 0000 uuuu uuuu uuuu
C1RX0DLC 0384 Recei ve Buf fe r 0 Exte nded Ide ntifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu
C1RX0B1 0386 Receive Buf fer 0 Byte 1 Receive Buf fer 0 Byte 0 uuuu uuuu uuuu uuuu
C1RX0B2 0388 Receive Buf fer 0 Byte 3 Receive Buf fer 0 Byte 2 uuuu uuuu uuuu uuuu
C1RX0B3 038A Receive Buf fer 0 Byte 5 Receive Buf fer 0 Byte 4 uuuu uuuu uuuu uuuu
C1RX0B4 038C Receive Buffer 0 Byte 7 Receive Buf fer 0 Byte 6 uuuu uuuu uuuu uuuu
C1RX0CON 038E — — — — — — — —RXFUL— — — RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
C1CTRL 0390 CANCAP — CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — ICODE<2:0> —0000 0100 1000 0000
C1CFG1 0392 — — — — — — — —SJW<1:0> BRP<5:0> 0000 0000 0000 0000
C1CFG2 0394 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0u00 0uuu uuuu uuuu
C1INTF 0396 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000
C1INTE 0398 — — — — — — — — IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1IE RX0IE 0000 0000 0000 0000
C1EC 039A TERRCNT<7:0> RERRCNT<7:0> 0000 0000 0000 0000
TABLE 17-1: dsPIC30F4013 CAN1 REGISTER MAP(1) (CONTINUED)
SFR Name Addr . Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Stat e
Legend: u = uninitial ized bi t; — = unimplemented bit , read as ‘ 0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS7 0046) fo r descript ions of regis ter bit f ields.
dsPIC30F3014/4013
DS70138G-page 120 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 121
dsPIC30F3014/4013
18.0 DATA CONVERTER
INTERFACE (DCI) MODULE
18.1 Module Introduction
The dsPIC30F Data Converter Interface (DCI) module
allows simple interfacing of devices, such as audio
coder/decoders (Codecs), A/D converters and D/A
converters. The following interfaces are supported:
• Framed Synchronous Serial Transfer (single or
multichannel)
• Inter-IC Sound (I2S) Interface
• AC-Link Compliant mode
The DCI module provides the following general
features:
• Programmable word size up to 16 bits
• Support for up to 16 time slots, for a maximum
frame size of 256 bits
• Data buffering for up to 4 samples without CPU
overhead
18.2 Module I/O Pins
There are four I/O pins associated with the module.
When enabled, the module controls the data direction
of each of the four pins.
18.2.1 CSCK PIN
The CSCK pin provides the serial clock for the DCI
module. The CSCK pin may be configured as an input
or output using the CSCKD control bit in the DCICON1
SFR. When configured as an output, the serial clock is
provided by the dsPIC30F. When configured as an
input, the serial clock must be provided by an external
device.
18.2.2 CSD O PIN
The serial data output (CSDO) pin is configured as an
output only pin when the module is enabled. The
CSDO pin drives the serial bus whenever data is to be
tran smit ted. Th e CSDO pi n is tri- state d or driv en t o ‘0’
during CSCK periods when data is not transmitted,
depending on the state of the CS DOM control bit. T his
allows other devices to place data on the serial bus
during transmission periods not used by the DCI
module.
18.2.3 CSDI PIN
The serial data input (CSDI) pin is configured as an
input only pin when the module is enabled.
18.2.3.1 COFS PIN
The Co dec Fra me Sync hroniz ation (COFS ) pin i s used
to synchronize data transfers that occur on the CSDO
and CSDI pins. The COFS pin ma y be configured as an
input or an ou tpu t. The data directi on for the COFS pi n
is determined by the COFSD control bit in the
DCICON1 register.
The DCI module accesses the shadow registers while
the CPU is in the process of accessing the memory
mapped buffer registers.
18.2.4 BUFFER DATA ALIGNMENT
Data values are always stored left justified in the buf-
fers sinc e m os t Co de c da t a is represente d as a si gne d
2’s comp lemen t fracti onal n umber. If the rece ived w ord
length is less than 16 bits, the unused LSbs in the
receive buffer registers are set to ‘0’ by the module. If
the transmitted word length is less than 16 bits, the
unused LSb s in the transm it buf fer regis ter are ignore d
by the module. The word length setup is described in
subsequent sections of this document.
18.2.5 TRANSMIT/RECEIVE SHIFT
REGISTER
The DCI module has a 16-bit shift register for shifting
serial data in and out of the module. Data is shifted in/
out of the shif t regist er MSb first , since a udio PCM data
is transmitted in signed 2’s complement format.
18.2.6 DCI BUFFER CONTROL
The DCI m odule con tains a buffe r control uni t for trans -
ferring data between the shadow buffer memory and
the serial shift register. The buffer control unit is a sim-
ple 2-bit address counter that points to word locations
in the shadow buffer memory. For the receive memory
spac e (high addres s portion of DCI bu ffer me mory), the
address counter is concatenated with a ‘0’ in the MSb
locatio n to form a 3-bit ad dres s. For th e tran sm it mem -
ory space (high portion of DCI buffer memory), the
address counter is concatenated with a ‘1’ in the MSb
location.
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Note: The DCI buffer control unit always
access es the same relati ve loc ation in the
transmit and receive buffers, so only one
address counter is provided.
dsPIC30F3014/4013
DS70138G-page 122 2010 Microchip Technology Inc.
FIGURE 18-1: DCI MODULE BLOCK DIAGRAM
BCG Control bits
16-Bit Data Bus
Sample Rate
Generator
SCKD
FSD
DCI Buffer
Frame
Synchronization
Generator
Control Unit
DCI Shift Register
Receive Buffer
Registers w/Shadow
FOSC/4
Word-Size Selection bits
Frame Length Selection bits
DCI Mode Selection bits
CSCK
COFS
CSDI
CSDO
15 0
Transmit Buffer
Registers w/Shadow
2010 Microchip Technology Inc. DS70138G-page 123
dsPIC30F3014/4013
18.3 DCI Module Operation
18.3.1 MODULE ENABLE
The DCI module is enabled or disabled by setting/
clearing the DCIEN control bit in the DCICON1 SFR.
Clearing the DCIEN control bit has the effect of reset-
ting the module. In particular, all counters associated
with CSCK generation, Frame Sync, and the DCI buf fer
control unit are reset.
The DCI clocks are shut down when the DCIEN bit is
cleared.
When enabled, the DCI controls the data direction for
the four I/O pins associated with the module. The port,
LAT and TRIS register values for these I/O pins are
overridden by the DCI module when the DCIEN bit is set.
It is also possible to override the CSCK pin separately
when the bit clock generator is enabled. This permits
the bit clock generator to operate without enabling the
rest of the DCI module.
18.3.2 WORD-SIZE SELECTION BITS
The WS<3:0> word-siz e selectio n bits in the DCICON2
SFR determine the number of bits in each DCI data
word. Essentially, the WS<3:0> bits determine the
counting period for a 4-bit counter clocked from the
CSCK signal.
Any data length, up to 16 bits, may be selected. The
value loaded into the WS<3:0> bits is one less the
desired word length. For example, a 16-bit data word
size is sele cted when WS<3:0> = 1111.
18.3.3 FRAME SYNC GENERATOR
The Frame Syn c gene rato r (C OF SG) i s a 4-bi t co un ter
that sets the frame length in data words. The Frame
Sync ge nerator is increm ented each ti me the word-size
counter is reset (refer to Section 18.3.2 “Word-Size
Selection Bits”). The pe riod for the Frame Sy nchron i-
zation generator is set by writing the COFSG<3:0>
control bits in the DCICON2 SFR. The COFSG period
in clock cycles is determined by the following formula:
EQUATION 18-1: COFSG PE RIOD
Frame lengths, up to 16 data words, may be selected.
The frame length in CSCK periods can vary up to a
maximum of 256 depending on the word size that is
selected.
18.3.4 FRAME SY NC MODE
CONTROL BITS
The type of Frame Sync signal is selected using the
Frame Synchronization mode control bits
(COFSM<1:0>) in the DCICON1 SFR. The following
operating modes can be selected:
• Multichannel mode
•I
2S mode
• AC-Link mode (16-bit)
• AC-Link mode (20-bit)
The operation of the COFSM control bits depends on
whether the DCI module generates the Frame Sync
signal as a master device, or receives the Frame Sync
signal as a slave device.
The master device in a DSP/Codec pair is the device
that gene rates the Frame Sync signal. The Frame Sync
signal initiates data transfers on the CSDI and CSDO
pins and usually has the same frequency as the data
sample rate (COFS).
The DCI modu le is a Fra me Sync mast er if the CO FSD
control bit is cleared and is a Frame Sync slave if the
COFSD cont rol bit is set.
18.3.5 MASTER FRAME SYNC
OPERATION
When the DCI module is operating as a Frame Sync
master device (COFSD = 0), the COFSM mode bits
determine the type of Frame Sync pulse that is
generated by the Frame Sync generator logic.
A new CO FS signal is gen erated when the Frame Sync
generator resets to ‘0’.
In the Multichannel mode, the Frame Sync pulse is
drive n high for the CSC K period to init iate a d at a trans -
fer. The number of CSCK cycles between successive
Frame Sync pulses depends on the word size and
Frame Sync generator control bits. A timing diagram for
the Frame Sync signal in Multichannel mode is shown
in Figure 18-2.
In the AC-Link mode of operation, the Frame Sync
signal has a fixed period and duty cycle. The AC-Link
Frame Sync signal is high for 16 CSCK cycles and is
low for 240 CSCK cycles. A timing diagram with the
timing details at the start of an AC-Link frame is shown
in Figure 18-3.
In the I2S mode, a Frame Sync signal having a 50%
duty cycle is generated. The period of the I2S Frame
Sync signal in CSCK cycles is determined by the word
Note: These WS<3:0> control bits are used only
in the Multichannel and I2S modes. These
bits have no effect in AC-Link mode since
the dat a slot sizes are fixed by the protocol.
Frame Leng th = Word Length • (FSG Value + 1)
Note: The COFSG control bits have no effect in
AC-Link mode since the frame length is
set to 256 CSCK periods by the protocol.
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DS70138G-page 124 2010 Microchip Technology Inc.
size and Frame Sync generator control bits. A new I2S
data transfer boundary is marked by a high-to-low or a
low-to-high transition edge on the COFS pin.
18.3.6 SLAVE FRAME SYNC OPERATION
When the DCI module is operating as a Frame Sync
slave (COFSD = 1), data transf ers are contro lled by the
Codec device attached to the DCI module. The
COFSM control bits control how the DCI module
responds to incoming COFS signals.
In the Multichannel mode, a new data frame transfer
begins on e C SCK c ycle after the COFS pin is s am ple d
high (see Figure 18-2). The pulse on the COFS pin
resets the Frame Sync generator logic.
In the I2S mode, a new data word is transferred one
CSCK cycl e after a l ow-t o- high o r a hi gh-t o-lo w tr ansi -
tion is sampled on the COFS pin. A rising or falling
edge on the COFS pin resets the Frame Sync
generator logic.
In the AC -Li nk mo de, the tag s lot and subsequent data
slots for the next frame is transferred one CSCK cycle
after the COFS pin is sampled high.
The COFSG and WS bits must be configured to
provide the proper frame length when the module is
operatin g in th e Slave mo de. Onc e a val id Frame Sync
pulse has been sampled by the module on the COFS
pin, an entire data frame transfer takes place. The
module will not respond to further Frame Sync pulses
until the data frame transfer has completed.
FIGURE 18-2: FRAME SYNC TIMING, MULTICHANNEL MODE
FIGURE 18-3: FRAME SYNC TIMING, AC-LINK START-OF-FRAME
FIGURE 18-4: I2S INTERFACE FRAME SYNC TIMING
CSCK
CSDI/CSDO
COFS
MSB LSB
Tag
MSb
BIT_CLK
CSDO or CSDI
SYNC
Tag
bit 14
S12
LSb
S12
bit 1
S12
bit 2 Tag
bit 13
MSB LSB MSB LSB
CSCK
CSDI or CSDO
WS
Note: A 5-bit transfer is sho wn here for illustration purposes. The I2S protocol does not specify word length – this
will be system dependent.
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18.3.7 BIT CLOCK GENERATOR
The DCI module has a dedicated 12-bit time base that
produ ces the bit cl ock. The bit clock r ate (period ) is set
by writing a non-zero 12-bit value to the BCG<11:0>
control bits in the DCICON3 SFR.
When the BCG<11:0> bits are set to zero, the bit clock
is dis abled . If the BCG< 11:0> bit s are se t to a non -zero
value, the bit clock generator is enabled. These bits
should be set to ‘0’ and the CSCKD bit set to ‘1’ if the
serial clock for the DCI is received from an external
device.
The formula for the bit clock frequency is given in
Equation 18-2.
EQUATION 18-2: BIT CLOCK FREQUENCY
The required bit clock frequency is determined by the
system sampling rate and frame size. Typical bit clock
frequencies range from 16x to 512x the converter
sample rate depending on the data converter and the
communication protocol that is used.
To achieve bit clock frequencies associated with
common audio sampling rates, the user needs to selec t
a crystal frequency that has an ‘even’ binary value.
Examples of such crystal frequencies are listed in
Table 18-1.
TABLE 18-1: DEVICE FREQUENCIES FOR COMMON CODEC CSCK FREQUE NCIE S
FBCK = FCY
2 (BCG + 1)
•
FS (kHz) F CSCK/FSFCSCK (MHz)(1) FOSC (MHZ)PLLFCY (MIPS) BCG(2)
8 256 2.048 8.192 4 8.192 1
12 256 3.072 6.144 8 12.288 1
32 32 1.024 8.192 8 16.384 7
44.1 32 1.4112 5.6448 8 11.2896 3
48 64 3.072 6.144 16 24.576 3
Note 1: When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the
operation of the DCI module.
2: When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must
meet the device timing requirements.
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18.3.8 SAMPLE CLOCK EDGE
CONTROL BIT
The sample clock edge (CSCKE) control bit determines
the sam pling edge for the CSCK si gnal. If the C SCK bit
is clea red (defau lt), d ata i s samp led on th e fallin g edge
of the CSCK signal. The AC-Link protocols and most
multichannel formats require that data be sampled on
the falling edge of the CSCK signal. If the CSCK bit is
set, data is sampled on the rising edge of CSCK. The
I2S protocol requires that data be sampled on the rising
edge of the CSC K signa l.
18.3.9 DATA JUSTIFICATION
CONTROL BIT
In most applications, the data transfer begins one
CSCK cycle after the COFS signal is sampled active.
This is the de fault conf igura tion of t he DCI module. An
alternate data alignment can be selected by setting the
DJST control bit in the DCICON1 SFR. When DJST = 1,
data transfers begin during the same CSCK cycl e when
the COFS signal is sampled active.
18.3.10 TRANSMIT SLOT ENABLE BITS
The TSCON SFR has control bits that are used to
enable up t o 16 ti me sl ots for tran smis sion. The se co n-
trol bits are t he TSE <15 :0> bi ts. Th e siz e of each time
slot is det erm ine d by the WS<3:0 > word-s ize s election
bits and can vary up to 16 bits.
If a transmit tim e slot is enabl ed via one of the TSE bit s
(TSEx = 1), the contents of the current transmit shadow
buffer location is loaded into the CSDO Shift register
and the DCI buffer control unit is incremented to point
to the next location.
During an unused transmit time slot, the CSDO pin
drives ‘0’s or is tri-stated during all disabled time slots
depending on the state of the CSDOM bit in the
DCICON1 SFR.
The dat a frame size in bit s is determine d by the chosen
data word size and the number of data word elements
in the frame. If the chosen frame size has less than
16 elements, the additional slot enable bits have no
effect.
Each tran smit dat a word is written to the 16-bit trans mit
buffer as left justified data. If the selected word size is
less than 16 bits, then the LSbs of the transmit buffer
memory have no effect on the transmitted data. The
user should write ‘0’s to the unused LSbs of each
transmit buffer location.
18.3 .11 RECEIVE SLOT ENABLE BITS
The RSCON SFR cont ains control bits that are used to
enable up to 16 time slots for reception. These control
bits are the RSE<15:0> bits. The size of each receive
time slot is determined by the WS<3:0> word-size
selection bits and can vary fr om 1 to 16 bits.
If a recei ve t im e sl ot i s e nab led via one of the RS E bits
(RSEx = 1), the shi ft regis ter content s are wr itten to the
current DCI receive shadow buf fer location and the buf-
fer contro l unit is increme nted to po int to the next buf fer
location.
Data is not packed in the receive memory buffer loca-
tions if the selected w ord size is less than 16 bits . Each
received slot data word is stored in a separate 16-bit
buffer location. Data is always stored in a left justified
format in the receive memory buffer.
18.3.12 SL O T ENA BL E BITS OPERATIO N
WITH FRAME SYNC
The TSE and RSE control bits operate in concert with
the DCI Frame Sync generator. In the Master mode, a
COFS signal is generated whenever the Frame Sync
generator is reset. In the Slave mode, the Frame Sync
generato r is reset whenev er a COFS pulse is recei ved.
The TSE and R SE control bits allow up to 16 co ns ec u-
tive time slots to be enabled for transmit or receive.
After the last enabled time slot has been transmitted/
received, the DCI stops buffering data until the next
occurring COFS pulse.
18.3.13 SYNCHRONOUS DATA
TRANSFERS
The DCI buf fer c ontrol un it is inc rement ed by one word
location whenever a given time slot has been enabled
for trans mission or receptio n. In most case s, data inp ut
and output transfers are synchronized, which means
that a da ta sample is received for a given channel at the
same time a data sample is transmitted. Therefore, the
transmit and receive buffers are filled with equal
amounts of data when a DCI interrupt is generated.
In some cases, the amount of data transmitted and
rece ived dur ing a data fr ame may no t be eq ual . As an
example, assume a two-word data frame is used.
Furt her m or e, as su me th at d a ta is onl y r e ce iv ed du r i ng
slot #0 but is transmitted during slot #0 and slot #1. In
this case, the buffer control unit counter would be
incremented twice during a data frame but only one
receive register location would be filled with data.
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18.3.14 BUFFER LENGTH CONTROL
The amount of data that is buffered between interrupts
is dete rmined by the buf fer le ngth (BLEN <1:0> ) contro l
bit s in the DCI CON2 SFR. T he size of the transm it and
receive buffers may be varied from 1 to 4 data words
using the BLEN control bits. The BLEN control bits are
compared to the current value of the DCI buffer control
unit address counter. When the two LSbs of the DCI
addr es s c o un t er m at c h th e BL E N<1 : 0> v al u e, t h e bu f -
fer con trol unit i s reset to ‘0’. In addit ion, the content s of
the receive shadow registers are transferred to the
receive buffer re gisters and the contents of the tr ansmit
buffer registers are transferred to the transmit shadow
registers.
18.3.15 BUFFER ALI GN ME NT WITH DATA
FRAMES
There is no direct coupling between the position of the
AGU Address Pointer and the data frame boundaries.
This mea ns that there is an impl ied assignm ent of each
transmit and receive buffer that is a function of the
BLEN control bits and the number o f enabled data s lots
via the TSE and RSE control bits.
As an example, assume that a 4-word data frame is
chosen and that we want to transmit on all four time
slots in the frame. This configuration would be estab-
lished by setting the TSE0, TSE1, TSE2, and TSE3
control bits in the TSCON SFR. With t his module s etup,
the TXBUF0 register would be naturally assigned to
slot #0, the TXBUF1 register would be naturally
assigned to slot #1, and so on.
18.3.16 TRANSMIT STATUS BITS
There are two transmit st atus bits in the DCIST A T SFR.
The TMPT Y bit i s se t when the conte nts of th e trans mit
buffer registers are transferred to the transmit shadow
registers. The TMPTY bit may be polled in software to
determine when the transmit buffer registers may be
wri tte n. Th e TM P TY b i t is cle ar e d au t om at i call y by t he
hardware when a write to one of the four transmit
buffers occurs.
The TUNF bi t is read-onl y and in dicat es t hat a trans mit
underflow has occurred for at least one of the transmit
buff er registers that is in use. The TUNF bit is set at the
time t h e t ran sm it b uffer reg i st e rs ar e tr an sfe r red to t he
transmit shadow registers. The TUNF status bit is
cleared automatically when the buffer register that
underflowed is written by the CPU.
18.3.17 RECEIVE STATUS BITS
There are two receive status bits in the DCISTAT SFR.
The RFUL status bit is read-only and indicates that new
data is availa ble in the rec eive buf fers . The RFUL bi t is
cleared automatically when all receive buffers in use
have been read by the CPU.
The ROV status bit is read-only and indicates that a
receive overflow has occurred for at least one of the
receive buffer locations. A receive overflow occurs
when the buffer location is not read by the CPU before
new dat a is transfe rred from the sha dow regis ters. Th e
ROV st atus bit is clea red auto matic ally when th e b uff er
register that caused the overflow is read by the CPU.
When a receive overflow occurs for a specific buffer
location, the old contents of the buffer are overwritten.
Note: When m ore tha n four time slo ts are ac ti ve
within a data frame, the user code must
keep track of which time slots are to be
read/written at each interrupt. In some
cases, the alignment between transmit/
receive buffers and their respective slot
assignments could be lost. Examples of
such cases include an emulation
breakpoint or a hardware trap. In these
situations, the user should poll the SLOT
status bits to determine what data should
be loaded into the buffer registers to
resynchronize the software with the DCI
module.
Note: The transmit status bits only indicate
status for buffer locations that are used by
the module. If the buffer length is set to
less than four words, for example, the
unused buffer locations do not affect the
transmit status bits.
Note: The receive statu s bits only indicate status
for buffer locations that are used by the
module. If the buffer length is set to less
than four words, for example, the unused
buffer locations do not affect the transmit
statu s bit s .
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18.3.18 SLOT STATUS BITS
The SLOT<3:0> status bits in the DCISTAT SFR indi-
cate the curre nt active time slo t. These bit s correspond
to the value of the Frame Sync generator counter. The
user may poll these status bits in software when a DCI
interrupt occurs to determine what time slot data was
last rec eived and w hich time slot data sh ould be loade d
into the TXBUF registers.
18.3.19 CSD O MO DE BIT
The CSDOM control bit controls the behavior of the
CSDO pin during unused transmit slots. A given trans-
mit time slot is unused if it’s corresponding TSEx bit in
the TSCON SFR is cleared.
If the CSDOM bit is cleared (default), the CSDO pin is
low during u nused time slot period s. This mod e is use d
when there are only two devices attached to the serial
bus.
If the CSDOM bit is se t, the CSDO pin is tri -st a ted dur-
ing unus ed time slo t periods. Thi s mode allo ws multiple
device s to share the s ame CSDO line in a multichanne l
application. Each device on the CSDO line is config-
ured so that it only transmits data during specific time
slots. No two devices transmit data during the same
time slot.
18.3.20 DIGITAL LOOPBACK MODE
Digital Loopback mode is enabled by setting the
DLOOP control bit in the DCICON1 SFR. When the
DLOOP bit is set, the module internally connects the
CSDO signal to CSDI. The actual data input on the
CSDI I/O pin is ignored in Digital Loopback mode.
18.3.21 UNDERFLOW MODE CONTROL BIT
When an underflow occurs, one of two actions may
occur depending on the state of the Underflow mode
(UNFM) control bit in the DCICON1 SFR. If the UNFM
bit is cl eared (d efault) , the module tran smit s ‘0’s on th e
CSDO pin during the active time slot for the buffer loca-
tion. In th is operating m ode, the Co dec device att ached
to the DCI module is simply fed digital ‘silence’. If the
UNFM control bit is set, the module transmits the last
data w ritte n to the buffer locati on. This ope rati ng m od e
permits the user to send continuous data to the Codec
device without consuming CPU overhead.
18.4 DCI Module Interrupts
The frequency of DCI module interrupts is dependent
on the BLEN<1:0> control bits in the DCICON2 SFR.
An interrupt to the CPU is generated each time the set
buffer length has been reached and a shadow register
transfer takes place. A shadow register transfer is
defined as the time when th e previou sly written TXBUF
values a re transferred to the transmit sh adow regist er s
and new received values in the receive shadow
registers are transferred into the RXBUF registers.
18.5 DCI Module Operation During CPU
Sleep and Idle Modes
18.5.1 DCI MODULE OPERATION DURING
CPU SLEEP MODE
The DCI module has the ability to operate while in
Sleep mode and wake the CPU when the CSCK signal
is supplied by an external device (CSCKD = 1). The
DCI module generates an asynchronous interrupt
when a DC I buffer t ransfer has co mpleted and th e CPU
is in Sleep mode.
18.5.2 DCI MODULE OPERATION DURING
CPU IDLE MODE
If the DCISIDL control bit is cleared (default), the mod-
ule continues to operate normally even in Idle mode. If
the DCISIDL bit is set, the module halts when Idle
mode is asserted.
18.6 AC-Link Mode Operati on
The AC-L in k p roto co l i s a 2 56 -bit fram e w ith on e 1 6-b it
data slot, followed by twelve 20-bit data slots. The DCI
module has two operating modes for the AC-Link pro-
tocol. These operating modes are selected by the
COFSM<1:0> control bits in the DCICON1 SFR. The
first AC-Link mode is called ‘16-bit AC-Link mode’ and
is selected by setting COFSM<1:0> = 10. The seco nd
AC-Link mode is called ‘20-bit AC-Link mode’ and is
selected by setting COFSM<1:0> = 11.
18.6.1 16-BIT AC-LINK MODE
In the 16-bit AC-Link mode, data word lengths are
restricted to 16 bits. Note that this restriction only
affects the 20-bit data time slots of the AC-Link proto-
col. For received time slots, the incoming data is simply
truncate d to 16 bit s. For outgoing tim e slots, the 4 LSb s
of the data w ord are s et to ‘ 0’ by the modul e. This trun-
cation of the time slots limits the A/D and DAC data to
16 bit s but p ermits proper da ta ali gnment in t he TXBUF
and RXBUF registers. Each RXBUF and TXBUF
register contains one data time slot value.
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18.6.2 20-BIT AC-LINK MODE
The 20-bit AC-Link mo de allows all bits in th e data tim e
slot s to be trans mitted and rece ived but doe s not main-
tain data alignment in the TXBUF and RXBUF
registers.
The 20-bit AC -Li nk mo de functions simi lar to the Mul ti-
channel mode of the DCI module, except for the duty
cycle of the Frame Synchronization signal. The AC-
Link Frame Synchronization signal should remain high
for 16 C SCK cy cles and sh ould b e low for the followin g
240 cycles.
The 20-bit mode treats each 256-bit AC-Link frame as
sixteen, 16-bit time slots. In the 20-bit AC-Link mode,
the module operates as if COFSG<3:0> = 1111 and
WS<3:0> = 1111. The data alignment for 20-bit data
slots is ignored. For example, an entire AC-Link data
frame can be transmitted and received in a packed
fashion by setting all bits in the TSCON and RSCON
SFRs. Since the total available buffer length is 64 bits,
it would take 4 consecutive interrupts to transfer the
AC-Link frame. The application software must keep
track of the current AC-Link frame segment .
18.7 I2S Mode Operatio n
The DCI module is configured for I2S mode by writing
a value of ‘01’ to the COFSM<1:0> control bits in the
DCICON1 SFR. When operating in th e I2S mode, the
DCI module generates Frame Synchronization signals
with a 50% duty cycle. Each edge of the Frame
Synchronization signal marks the boundary of a new
data word transfer.
The user must also select the frame length and data
word size using the COFSG and WS control bits in the
DCICON2 SFR.
18.7.1 I2S FRAME AND DATA WORD
LENGTH SELECTION
The WS and COFSG control bit s are set to produce the
period for one half of an I2S data frame. That is, the
frame length is the total number of CSCK cycles
required for a left or a right data word transfer.
The BLEN bits must be set fo r the desired buffer le ngth.
Setting BLEN<1:0> = 01 produces a CPU interrupt,
once per I2S fr ame.
18.7.2 I2S DATA JUSTIFICATION
As per the I2S specification, a data word transfer, by
default, begins one C SCK cycl e af ter a tra nsiti on of th e
WS signal. A ‘MSb left justified’ option can be selected
using the DJST control bit in the DCICON1 SFR.
If DJST = 1, the I2S dat a transfers are MSb lef t justifie d.
The MSb of the data word is presented on the CSDO
pin durin g the same CSCK cy c le as the ris ing or fal lin g
edge of the COFS signal. The CSDO pin is tri-stated
after the data word has been sent.
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TABLE 18-2: dsPIC30F3014/4013 DCI REGISTER MAP(1)
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
DCICON1 0240 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD UNFM CSDOM DJST — — — COFSM1 COFSM0 0000 0000 0000 00 00
DCICON2 0242 — — — — BLEN1 BLEN0 — COFSG<3:0> —WS<3:0>0000 0000 0000 0000
DCICON3 0244 — — — —BCG<11:0>0000 0000 0000 0000
DCISTAT 0246 — — — — SLOT3 SLOT2 SLOT1 SLOT0 — — — — ROV RFUL TUNF TMPTY 0000 0000 0000 0000
TSCON 0248 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 0000 0000 0000 0000
RSCON 024C RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 00 00 0000 0000 0000
RXBUF0 0250 Receive Buffer 0 Data Register 0000 0000 0000 0000
RXBUF1 0252 Receive Buffer 1 Data Register 0000 0000 0000 0000
RXBUF2 0254 Receive Buffer 2 Data Register 0000 0000 0000 0000
RXBUF3 0256 Receive Buffer 3 Data Register 0000 0000 0000 0000
TXBUF0 0258 Transmit Buffer 0 Data Register 0000 0000 0000 0000
TXBUF1 025A T ransmit Buffer 1 Data Register 00 00 0000 0000 00 00
TXBUF2 025C Transmit Buffer 2 Data Register 0000 0000 0000 0000
TXBUF3 025E T ransmit Buffer 3 Data Register 00 00 0000 0000 00 00
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2010 Microchip Technology Inc. DS70138G-page 131
dsPIC30F3014/4013
19.0 12-BIT ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The 12-bit Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 12-bit digital
number. This module is based on a Successive
Approximation Register (SAR) architecture and pro-
vides a maxi mum samplin g rate of 200 ksps . The A/D
module has up to 16 analog inputs which are multi-
plexed into a sample and hold amplifier. The output of
the sample and hold is the input into the converter
which generates the result. The analog reference volt-
age is software selectable to either the device supply
voltage (AVDD/AVSS) or the voltage level on the
(VREF+/VREF-) pin. The A/D converter has a unique
feature of being able to operate while the device is in
Sleep mode with RC oscillator selection.
The A/D module has six 16-bit registers:
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
• A/D Control Register 3 (ADCON3)
• A/D Input Select Register (ADCHS)
• A/D Port Configuration Register (ADPCFG)
• A/D Input Scan Selection Register (ADCSSL)
The ADCON1, ADCON2 and ADCON3 registers
control the operation of the A/D module. The ADCHS
register selects the input c hannels to be co nverted. The
ADPCFG register configures the port pins as analog
inputs or as digital I/O. The ADCSSL register selects
input s for sca nni ng .
The block diagram of the 12 -bit A/D module is shown in
Figure 19-1.
FIGURE 19-1: 12-BIT A/D FUNCTIONAL BLOCK DIAGRAM
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Note: The SSRC<2:0>, ASAM, SMPI<3:0>,
BUFM and ALTS bits, as well as the
ADCON3 and ADCSSL registers, must
not be written to while ADON = 1. This
would lead to indeterminate results.
Comparator
12-Bit SAR Conversion Logic
VREF+
DAC
Data
16-Word, 12- Bi t
Dual Port
RAM
Bus Interface
AN12
0000
0101
0111
1001
1100
0001
0010
0011
0100
0110
1000
1010
1011
AN8
AN9
AN10
AN11
AN4
AN5
AN6
AN7
AN0
AN1
AN2
AN3
CH0
AN1
VREF-
VREF-
Sample/Sequence
Control
Sample
Input MUX
Control
Input
Switches
S/H
AVSS
AVDD
Format
Note: The ADCHS, ADPCFG and ADC SSL registers allow the application to configure AN13-AN15 as analog input
pins. Since these pins are not physically present on the device, conversion results from these pins will read ‘0’.
dsPIC30F3014/4013
DS70138G-page 132 2010 Microchip Technology Inc.
19.1 A/D Result Buffer
The module contains a 16-word, dual port read-only
buffer, called ADCBUF0...ADCBUFF, to buffer the A/D
results. The RAM is 12 bits wide but the data obtained
is represented in one of four different 16-bit data for-
mats. The contents of the sixteen A/D Conversion
Result Buffer registers, ADCBUF0 through ADCBUFF,
cannot be written by user software.
19.2 Conversion Operation
After the A/D module has been configured, the sample
acquisition is started by setting the SAMP bit. Various
sources, such as a programmable bit, timer time-outs
and external events, terminate acquisition and start a
conversion. When the A/D conversion is complete, the
result is loaded into ADCBUF0...ADCBUFF, and the
DONE bit and the A/D Interrupt Fla g, ADIF, are set after
the number of samples specified by the SMPI bit. The
ADC module can be configured for different interrupt
rates as described in Section 19.3 “Selecting the
Conversion Sequence”.
The following steps should be followed for doing an
A/D conversion:
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O
• Select A/D input channels
• Select A/D conve rsi on cl ock
• Select A/D conversi on trigger
• Turn on A/D module
2. Configure A/D interrupt (if required):
• Clear ADIF bit
• Select A/D interrupt priority
• Set ADIE bit (for ISR processing)
3. Start sampling
4. Wait the required acquisition time
5. Trigger acquisition end, start conversion:
6. Wait for A/D conversion to complete, by either:
• Waiting for the A/D interrupt, or
• Waiting for the DONE bit to get set.
7. Read A/D result buffer, clear ADIF if required
19.3
Selecting the Conversion Sequence
Several groups of control bits select the sequence in
which the A/D connects inputs to the sample/hold
channel, converts a channel, writes the buffer memory
and generates interrupts.
The sequence is controlled by the sampling clocks.
The SMPI bits select the number of acquisition/
convers io n s eq uen ce s that woul d b e p erfo r me d b efo re
an interrupt occurs. This can vary from 1 sample per
interrupt to 16 samples per interrupt.
The BUFM bit splits the 16-word results buffer into two
8-word groups. Writing to the 8-word buffers is
alternated on each interrupt event.
Use of the BUFM bit depends on how much time is
available for moving the buffers after the interrupt.
If the processor can quickly unload a full buffer within
the time it takes to acquire and convert one channel,
the B UFM bit can be ‘0’ a nd up to 16 conversio ns (c or-
responding to the 16 input channels) may be done per
interrupt. The processor has one acquisition and
conversion time to move the sixteen conversions.
If the processor cannot unload the buffer within the
acquisition and conversion time, the BUFM bit should be
‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,
then eight conversions are loaded into 1/2 of the buffer,
following which an interrupt occurs. The next eight con-
versions are loaded into the other 1/2 of the buffer. The
processor has the entire time between interrupts to
move the eight conversio ns.
The ALTS bit can be used to alternate the inputs
selected during the sampling sequence. The input
multiplexer has two sets of sample inputs: MUX A and
MUX B. If the ALTS bit i s ‘0’, onl y the MUX A input s are
selected for sampling. If the ALTS bit is ‘1’ and
SMPI<3:0> = 0000 on the first sample/convert
sequence, the MUX A inputs are selected and on the
next acquire/convert sequence, the MUX B inputs are
selected.
The CSCNA bit (ADCON2<10>) allows the S/H input to
be sequentially scanned across a selected number of
analog inputs for the MUX A group. The inputs are
selected by the ADCSSL register. If a particular bit in
the ADCSSL register is ‘1’, the corresponding input is
selected. The inpu ts are alwa ys sc an ned from low e r to
higher num be red i npu t s, st arting afte r eac h inte rrup t. If
the number of inputs selected is greater than the
number of samples taken per interrupt, the higher
numbered inputs are unused.
Note: The ADCHS, ADPCFG and ADCSSL reg-
isters allow the application to configure
AN13-AN15 as analog input pins. Since
these pins are not physically present on
the device, conversion results from these
pins read ‘0’.
2010 Microchip Technology Inc. DS70138G-page 133
dsPIC30F3014/4013
19.4 Programming the Start of
Conversion Trigger
The conversion trigger terminates acquisition and
starts the requested conversions.
The SSRC<2:0> bits select the source of the conver-
sion tri gger . The SSRC bi ts provide fo r up to 4 alterna te
sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit causes
the conversion trigger.
When SSRC<2:0> = 111 (Auto-Convert mode), the
conversion trigger is under A/D clock control. The
SAMC bits select the number of A/D clocks between
the st art of acqui sitio n and the st art of conv ersion . This
provides the fastest conversion rates on multiple
channels. The SAMC bits must always be at least one
clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
19.5 Aborting a Conversion
Clearing the ADON bit during a conversion aborts the
current co nvers ion and stop s the sampli ng sequ encin g
until the next sampling trigger. The ADCBUF is not
updated with the partially completed A/D conversion
sample. That is, the ADCBUF will continue to contain
the value of the last completed conversion (or the last
value written to the ADCBUF register).
If cleari ng of t he ADON bit c oincide s wi th an a uto-st art,
the clea ring has a highe r priority and a ne w conver sion
does not start.
19.6 Selecti ng the ADC Conversion
Clock
The ADC conversion requires 14 TAD. The source of
the AD C conv ersion cloc k is s oft ware selec ted, u sing a
6-bit counter. There are 64 possible options for TAD.
EQUATION 19-1: ADC CONVERSION
CLOCK
The internal RC oscillator is selected by setting the
ADRC bit.
For correct ADC conversions, the ADC conversion
clock (TAD) mu st be selec ted to ensure a mini mum TAD
time of 33 4 nsec (for VDD = 5V ). Refe r to Section 23.0
“Electrical Characteristics” for minimum TAD under
other operating condition s.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 19-1: ADC CON VERSION
CLOCK AND SAMPLING
RATE CALCULATION
TAD = TCY * (0.5*(ADCS<5:0> + 1))
Minimu m TAD = 334 nsec
ADCS<5:0> = 2 – 1
TAD
TCY
TCY = 33.33 nsec (30 MIPS)
= 2 • – 1
334 nsec
33.33 nsec
= 19
Therefore,
Set ADCS<5 :0> = 19
Actual TAD = (ADCS<5:0> + 1)
TCY
2
= (19 + 1)
33.33 ns e c
2
= 334 ns ec
If SSRC<2:0> = 111 and SAMC<4 :0> = 00001
Since,
Sampling Time = Acquisition Time + Conversion Time
= 1 TAD + 14 TAD
= 15 x 334 nsec
Therefore,
Sampling Rat e =
= ~200 kH z
1
(15 x 33 4 ns e c)
dsPIC30F3014/4013
DS70138G-page 134 2010 Microchip Technology Inc.
19.7 ADC Speeds
The dsPIC30F 12-bit ADC specifications permit a
maximum of 200 ksps sampling rate. The table below
summarizes the conversion speeds for the dsPIC30F
12-bit ADC and the required operating conditions.
TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES
dsPIC30F 12-Bit ADC Conversion Rates
Sp eed TAD
Minimum Sampling
Time Min Rs Max VDD Temperature Channels Configuration
Up to 200
ksps(1) 334 ns 1 TAD 2.5 k4.5V to
5.5V -40°C to +85°C
Up to 100
ksps 668 ns 1 TAD 2.5 k3.0V to
5.5V -40°C to +1 25°C
Note 1: External V REF- and VREF+ pins must be used for correct operation. See Figure 19-2 for recommended
circuit.
VREF-VREF+
ADC
ANx S/HCHX
VREF-VREF+
ADC
ANx S/HCHX
ANx or VREF-
or
AVSS or
AVDD
2010 Microchip Technology Inc. DS70138G-page 135
dsPIC30F3014/4013
Figure 19-2 depicts the recommended circuit for the
conversion rates above 200 ksps. The dsPIC30F3014
is shown as an example.
FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMA TIC
The configuration procedures below give the required
setup values for the conversion speeds above
100 ksps.
19.7.1 200 ksps CONFIGURATION
GUIDELINE
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Compl y with con d i tion s prov id ed in Table 19-2.
• Connect external VREF+ and V REF- pins following
the recommended circuit shown in Figure 19-2.
• Set SSRC<2.0> = 111 in the ADCO N1 regist er to
enable the auto-convert opti on.
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register.
• Write the SMPI<3 .0> con trol bit s in the ADCON2
register for the desired number of conversions
between interrupts.
• Configure the A DC c l ock period to be:
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
• Configure the sampling time to be 1 TAD by
writing: SAMC<4:0> = 00001.
The following figure shows the timing diagram of the
ADC running at 200 ksps. The T AD selection in conjunc-
tion with the guidelines described above allows a con-
version speed of 200 ksp s. See Example 19-1 for code
example.
VDD
VDD
VDD
VDD
R2
10
C2
0.1 FC1
0.01 F
R1
10
C8
1 F
VDD
C7
0.1 F
VDD
C6
0.01 F
AVDD
C5
1 F
AVDD
C4
0.1 F
AVDD
C3
0.01 F
See Note 1
Note 1: Ensure adequate bypass capacitors are provided on each VDD pin.
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
dsPIC30F3014
VSS
VSS
VDD
VDD
VREF-
VREF+
AVSS
AVDD
VSS
VDD
VDD
VDD
1
(14 + 1) x 200,000 = 334 ns
dsPIC30F3014/4013
DS70138G-page 136 2010 Microchip Technology Inc.
FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 ksps, AUTO-SAMPLE START, 1 TAD
SAMPLIN G TIME
19.8 A/D Acquisition Requirements
The ana log i npu t mod el of t he 1 2-bit A/ D conver t er i s
shown i n Figure 19-4. The total sampling time for the
A/D is a function of the internal amplifier settling time
and the hol din g capaci to r char ge ti me.
For the A/D converter to meet its specified accuracy,
the Charge Holding Capacitor (CHOLD) must be
allowed to fully charge to the voltage level on the
analog input pin. The Source Impedance (RS), the
Interconnect Impedance (RIC) and the Internal Sam-
pling Switch (RSS) Impedance combine to directly
affe ct the time required to charg e the cap acitor , CHOLD.
The combined impedance of the analog sources must
therefore be small enough to fully charge the holding
capacitor within the chosen sample time. To minimize
the effects of pin leakage currents on the accuracy of
the A/D con verter , the maxi mum recom mended so urce
impedance, RS, is 2.5 k. After the analog input chan-
nel is selected (changed), this sampling function must
be comp leted prior to starting the conversion. The inter-
nal holding capacitor will be in a discharged state prior
to each sample operation.
FIGURE 19-4: 12-BIT A/D CONVERTER ANALOG INPUT MODEL
TCONV
= 14 TAD
TSAMP
= 1 TAD TSAMP
= 1 TAD
ADCLK
SAMP
DONE
ADCBUF0
ADCBUF1
Instruction Execution BSET ADCON1, ASAM
TCONV
= 14 TAD
CPIN
VA
Rs ANx VT = 0.6V
VT = 0.6V ILEAKAGE
RIC 250Sampling
Switch
RSS
CHOLD
= DAC capacitance
VSS
VDD
= 18 pF
500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
RSS
CHOLD
= Inpu t Capaci tance
= Thresh ol d Voltag e
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 2.5 k.
RSS 3 k
2010 Microchip Technology Inc. DS70138G-page 137
dsPIC30F3014/4013
19.9 Module Power-Down Modes
The module has two internal power modes.
When the ADON bit is ‘1’, the module is in Active mode;
it is fully powered and functional.
When ADON is ‘0’, the module is in Off mode. The
digit al and analo g portions of th e circuit are d isabled for
maximum curr ent savings .
In order to return to the Acti ve mode from Off mode, th e
user must wait for the ADC circuitry to stabilize. The
time required to stabilize is specified in Section 23.0
“Electri cal Characte ristics”.
19.10 A/D Operation During CPU Sleep
and Idle Modes
19.10.1 A/D OPERATION DURING CPU
SLEEP MODE
When the de vice ente rs Sleep mod e, all cl ock sourc es
to the module are shut down and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the
convers ion is abort ed. The conve rter does not con tinue
with a partially completed conversion on exit from
Sleep mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The A/D module can operate during Sleep mode if the
A/D clock source is set to RC (ADRC = 1). When the
RC cloc k sourc e is sel ected , the A/D mo du le wait s on e
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed which
eliminates all digital switching noise from the conver-
sion. (When the conversion sequence is complete, the
DONE bit is set.)
If the A/D interrupt is enabled, the device wakes up
from Sleep. If the A/D interrupt is not enabled, the A/D
module is then turned off, although the ADON bit
remains set.
19.10.2 A/D OPERATION DURING CPU IDLE
MODE
The ADSIDL bit determines if the module stops or
continues on Idle. If ADSIDL = 0, t he m odule co ntinues
operatio n on assertio n of Idle mode. If ADSIDL = 1, the
module stops on Idle.
19.11 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off, and any
conversion and sampling sequence is aborted. The val-
ues that ar e in th e ADCBUF reg isters are not m odifie d.
The A/D Result register contains unknown data after a
Power-on Reset.
19.12 Output Formats
The A/D result is 12 bits wide. The data buffer RAM is
also 12 bits wid e. The 12-bi t data can be read in one
of four different formats. The FORM<1:0> bits select
the for mat. E ach of the o utput form ats tran slate s to a
16-bit result on the data bus. Write data is always in
right- ju s ti fied ( int eg er) for mat .
FIGURE 19-5: A/D OUTPUT DATA FORMATS
RAM Contents: d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional d11 d10d09d08d07d06d05d04d03d02d01d000000
Fractional d11d10d09d08d07d06d05d04d03d02d01d000000
Signed Integer d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Integer 0000d11d10d09d08d07d06d05d04d03d02d01d00
dsPIC30F3014/4013
DS70138G-page 138 2010 Microchip Technology Inc.
19.13 Configuring Analog Port Pins
The use of the ADPC FG and TRIS registers control th e
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) is
converted.
The A/D operation is independent of the state of the
CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits.
When read ing the POR T register, all pins c onfigured as
analog input channels are read as cleared.
Pins configured as digital inputs will not convert an
analog i nput. Analog leve ls on any pin that is defined as
a dig ital inp ut (incl uding t he ANx p ins) ma y cause the
input buffer to consume current that exceeds the
device specifications.
19.14 Connection Considerations
The anal og inp uts h ave diod es to VDD and VSS as ESD
protection. This requires that the analog input be
betwee n VDD and VSS. If the input voltage exceeds this
range by greater th an 0.3V (eit her direct ion), one o f the
diodes becomes forward b iased and it may damage the
device if the input current speci fic ati on is exce ede d.
An external RC filter is sometimes added for anti-
aliasi ng of the input signal. The R component should be
select ed to ens ure that the sampl ing time requi rement s
are satisfied. Any external components connected (via
high-impedance) to an analog input pin (capacitor,
Zener diode, etc.) should have very little leakage
current at the pin.
2010 Microchip Technology Inc. DS70138G-page 139
dsPIC30F3014/4013
TABLE 19-2: A/D CONVERTER REGISTER MAP(1)
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
ADCBUF0 0280 — — — — ADC Data Buffer 0 0000 uuuu uuuu uuuu
ADCBUF1 0282 — — — — ADC Data Buffer 1 0000 uuuu uuuu uuuu
ADCBUF2 0284 — — — — ADC Data Buffer 2 0000 uuuu uuuu uuuu
ADCBUF3 0286 — — — — ADC Data Buffer 3 0000 uuuu uuuu uuuu
ADCBUF4 0288 — — — — ADC Data Buffer 4 0000 uuuu uuuu uuuu
ADCBUF5 028A — — — — ADC Data Buffer 5 0000 uuuu uuuu uuuu
ADCBUF6 028C — — — — ADC Data Buffer 6 0000 uuuu uuuu uuuu
ADCBUF7 028E — — — — ADC Data Buffer 7 0000 uuuu uuuu uuuu
ADCBUF8 0290 — — — — ADC Data Buffer 8 0000 uuuu uuuu uuuu
ADCBUF9 0292 — — — — ADC Data Buffer 9 0000 uuuu uuuu uuuu
ADCBUFA 0294 — — — — ADC Data Buffer 10 0000 uuuu uuuu uuuu
ADCBUFB 0296 — — — — ADC Data Buffer 11 0000 uuuu uuuu uuuu
ADCBUFC 0298 — — — — ADC Data Buffer 12 0000 uuuu uuuu uuuu
ADCBUFD 029A — — — — ADC Data Buffer 13 0000 uuuu uuuu uuuu
ADCBUFE 029C — — — — ADC Data Buff er 14 0000 uuuu uuuu uuuu
ADCBUFF 029E — — — — ADC Data Buffer 15 0000 uuuu uuuu uuuu
ADCON1 02A0 ADON —ADSIDL— — — FORM<1:0> SSRC<2:0> —— ASAM SAMP DONE 0000 0000 0000 0000
ADCON2 02A2 VCFG<2:0> —— CSCNA ——BUFS— SMPI<3:0> BUFM ALTS 0000 0000 0000 0000
ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000
ADCHS 02A6 — — — CH0NB CH0SB<3:0> — — — CH0NA CH0SA<3:0> 0000 0000 0000 0000
ADPCFG 02A8 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
ADCSSL 02AA CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000
Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 140 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 141
dsPIC30F3014/4013
20.0 SYSTEM INTEGRATION
There are several features intended to maximize
system reliability, minimize cost through elimination of
external components, provide power-saving operating
modes and of fer code protection:
• Oscillator Selection
• Reset
- Power-on Reset (P OR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Programmable Brown-out Reset (BOR)
• Watchdog Timer (WDT)
• Low-Voltage Detect
• Power-Saving modes (Sleep and Idle)
• Code Protection
• Unit ID Locations
• In-Circuit Serial Programming (ICSP)
dsPIC30F devices have a Watchdog Timer which is
permanently enabled via the Configuration bits or can
be software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-u p Timer (PWR T) which prov ides a delay on
power-u p only, designed to keep the part in R eset while
the power supply stabilizes. With these two timers on-
chip, most applications need no external Reset
circuitry.
Sleep mode is designed to offer a very low-current
Power-Dow n mode. The us er ca n wa ke -up fro m Slee p
through external Reset, Watchdog Timer wake-up, or
through an inte rrupt. Several os cillator opti ons are also
made available to allow the part to fit a wide variety of
applications. In the Idle mode, the clock sources are
still active but the CPU is shut off. The RC oscillator
option saves system cost while the LP crystal option
saves power.
20.1 Oscillator System Overview
The dsPIC30F oscillator system has the following
modules and features:
• Various external and internal oscillator options as
clock source s
• An on-chip PLL to boost internal operating
frequency
• A clock switching mechanism between various
clock source s
• Programm abl e c loc k pos t s ca ler for system po w er
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• Clock Control register (OSCCON)
• Configuration bits for main oscillator selection
Configuration bits determine the clock source upon
Power-on Reset (POR) and Brown-out Reset (BOR).
Thereafter, the clock source can be changed between
permissible clock sources. The OSCCON register
controls the clock switching and reflects system clock
related status bits.
Table 20-1 provides a summary of the dsPIC30F
oscillator operating modes. A simplified diagram of the
oscillator system is shown in Figure 20-1.
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s Reference Manual”
(DS70157).
dsPIC30F3014/4013
DS70138G-page 142 2010 Microchip Technology Inc.
TABLE 20-1: OSCILLATOR OPERATING MODES
Oscillator Mode Description
XTL 400 kHz-4 MHz crystal on OSC1:OSC2
XT 4 MHz-10 MHz crystal on OSC1:OSC2
XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled
XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled
XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled(1)
LP 32 kHz crystal on SOSCO:SOSCI(2)
HS 10 MHz-25 MHz crystal
HS/2 w/PLL 4x 10 MHz-20 MHz crystal, divide by 2, 4x PLL enabled
HS/2 w/PLL 8x 10 MHz-20 MHz crystal, divide by 2, 8x PLL enabled
HS/2 w/PLL 16x 10 MHz-15 MHz crystal, divide by 2, 16x PLL enabled
HS/3 w/PLL 4x 12 MHz-25 MHz crystal, divide by 3, 4x PLL enabled
HS/3 w/PLL 8x 12 MHz-25 MHz crystal, divide by 3, 8x PLL enabled
HS/3 w/PLL 16x 12 MHz-22.5 MHz crystal, divide by 3, 16x PLL enabled
EC External clock input (0-40 MHz)
ECIO External clock input (0-40 MHz), OSC2 pin is I/O
EC w/PLL 4x External clock input (4-10 MHz), OSC2 pin is I/O, 4x PLL enabled(1)
EC w/PLL 8x External clock input (4-10 MHz), OSC2 pin is I/O, 8x PLL enabled(1)
EC w/PLL 16x External clock input (4-7.5 MHz), OSC2 pin is I/O, 16x PLL enabled(1)
ERC External RC oscillator, OSC2 pin is FOSC/4 output(3)
ERCIO External RC oscillator, OSC2 pin is I/O(3)
FRC 7.37 MHz internal RC oscillator
FRC w/PLL 4x 7.37 MHz Intern al RC oscil lator, 4x PLL enable d
FRC w/PLL 8x 7.37 MHz Intern al RC oscil lator, 8x PLL enable d
FRC w/PLL 16x 7.37 MHz Internal RC oscillator, 16x PLL enabled
LPRC 512 kHz internal RC oscillator
Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met.
2: LP oscillator can be conveniently shared as system clock, as well as Real-Time Clock for Timer1.
3: Requires external R and C. Frequency operation up to 4 MHz.
2010 Microchip Technology Inc. DS70138G-page 143
dsPIC30F3014/4013
FIGURE 20-1: O SCILLATOR SYSTEM BLOCK DIAGRAM
Primary
OSC1
OSC2
SOSCO
SOSCI
Oscillator
32 kHz LP
Clock
and Control
Block
Switching
Oscillator
x4, x8, x16
PLL
Primary
Oscillator
Stability Detector
Stability Detector
Secondary
Oscillator
Programmable
Clock Divider
Oscillator
Start-up
Timer
Fail-Safe Clock
Monitor (FSCM)
Internal Fast RC
Oscillator (FRC)
Internal
Low-Power RC
Oscillator (LPRC)
PWRSAV Instruction
Wake-up Request
Oscillator Configuration bits
System
Clock
Oscillator Trap
To Timer1
LPRC
Secondary Osc
POR Done
Primary Os c
FPLL
POST<1:0>
2
FCKSM<1:0> 2
PLL
Lock COSC<2:0>
NOSC<2:0>
OSWEN
CF
TUN<3:0> 4
dsPIC30F3014/4013
DS70138G-page 144 2010 Microchip Technology Inc.
20.2 Oscillator Configurations
20.2.1 INITIAL CLOCK SOURCE
SELECTION
While coming out of Power-on Reset or Brown-out
Reset, the device sel ects its cl ock source based on:
a) FOS<2:0> Configuration bits that select one of
four oscillator groups,
b) and FP R<4:0> Configu ration bit s that select one
of 13 o scillat or choic es within the prim ary grou p.
The selection is as shown in Table 20-2.
20.2.2 OSCILLATOR START-UP TIMER
(OST)
In order to ensure that a crystal oscillator (or ceramic
resonator) has started and stabilized, an Oscillator
Start-up Timer is included. It is a simple 10-bit counter
that counts 1024 TOSC cycles before releasing the
oscil lator clock t o the rest of the sy stem. The ti me-out
period is designated as TOST. The TOST time is involved
every time the oscillator has to restart (i.e., on POR,
BOR and w ake-u p fro m Sl eep ). Th e O scill ato r Start-up
Timer is applied to the LP, XT, XTL and HS Oscillator
modes (upon wake-up from Sleep, POR and BOR) for
the primary oscillator.
TABLE 20-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode Oscillator
Source FOS<2:0> FPR<4:0> OSC2
Function
ECIO w/PLL 4x PLL 11101101 I/O
ECIO w/PLL 8x PLL 11101110 I/O
ECIO w/PLL 16x PLL 11101111 I/O
FRC w/PLL 4x PLL 11100001 I/O
FRC w/PLL 8x PLL 11101010 I/O
FRC w/PLL 16x PL L 11100011 I/O
XT w/PLL 4x PLL 11100101 OSC2
XT w/PLL 8x PLL 11100110 OSC2
XT w/PLL 16x PLL 11100111 OSC2
HS2 w/PLL 4x PLL 11110001 OSC2
HS2 w/PLL 8x PLL 11110010 OSC2
HS2 w/PLL 16x PLL 11110011 OSC2
HS3 w/PLL 4x PLL 11110101 OSC2
HS3 w/PLL 8x PLL 11110110 OSC2
HS3 w/PLL 16x PLL 11110111 OSC2
ECIO External 01101100 I/O
XT External 01100100 OSC2
HS External 01100010 OSC2
EXT External 01101011 CLKO
ERC External 01101001 CLKO
ERCIO External 01101000 I/O
XTL External 01100000 OSC2
LP Secondary 000XXXXX(Notes 1, 2)
FRC Internal FRC 001XXXXX(Notes 1, 2)
LPRC Intern al LPRC 010XXXXX(Notes 1, 2)
Note 1: The OSC2 pin is either usable as a general purpose I/O pin functionality only depending on the Primary
Oscillator mode selection (FPR<4:0>).
2: Note that OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock
source is selected at all times.
2010 Microchip Technology Inc. DS70138G-page 145
dsPIC30F3014/4013
20.2.3 LP OSCILLATOR CONTROL
Enabling the LP oscillator is controlled with two
elements:
• The current oscillator group bits, COSC<2:0>.
• The LPOSCEN bit (OSCCON register).
The LP oscillator is on (even during Sleep mode) if
LPOSCEN = 1. The LP oscillat or is the de vic e clock if:
• COSC<2:0> = 00 (LP selected as main osc.) and
• LPOSCEN = 1
Keeping t he LP oscillator on at all time s allows for a fast
switch to the 32 kHz system clock for lower power
operation. Returning to the faster main oscillator still
requires a start-up time
20.2.4 PHASE LOCKED LOOP (PLL)
The PLL multi plies the clock wh ic h is gen era ted by the
primary oscillator. The PLL is selectable to have either
gains of x4, x8 and x16. Input and output frequency
ranges are summarized in Table 20-3.
TABLE 20-3: PLL FREQUENCY RANGE
The PLL fea tures a lo ck out put which is assert ed when
the PLL enters a phase locked state. Should the loop
fall out of lock (e.g., due to noise), the lock signal is
rescinded. The state of this signal is reflected in the
read-only LOCK bit in the OSCCON register.
20.2.5 FAST RC OSCILLATOR (FRC)
The FRC oscillator is a fast (7.37 MHz ±2% nominal)
inter nal RC o scil lator. This os ci lla tor i s i nten ded to pro-
vide reasonable device operating speeds without the
use of an external crystal, ceramic resonator, or RC
network. The FRC oscillator can be used with the PLL
to obtain higher clock frequencies.
The dsPIC3 0F o perates from the FRC oscillat or whe n-
ever the current oscillator selection control bits in the
OSCCON register (OSCCON<14:12>) are set to ‘001’.
The four-bit field specified by TUN<3:0>
(OSCTUN<3:0>) allows the user to tune the internal
fast RC oscillator (nominal 7.37 MHz). The user can
tune the FRC oscillator within a range of +10.5%
(840 kHz) and -12% (960 kHz) in steps of 1.50%
around the factory-calibrated setting (see Table 20-4).
If OSCCON<1 4:12> are set to ‘111’ and F PR<4:0> a re
set to ‘00101’, ‘00110’ or ‘00111’, then a PLL
multiplier of 4, 8 or 16 (respectively) is applied.
TABLE 20-4: FRC TUNING
20.2.6 LOW-POWER RC OS CILLATOR (LPRC)
The LPRC oscillator is a component of the Watchdog
Timer (WDT) and oscillates at a nominal frequency of
512 kHz. The LPRC oscillator is the clock source for
the Power-up Timer (PWRT) circuit, WDT and clock
monitor circuits. It may also be used to provide a low-
frequency clock source option for applications where
power consumption is critical and timing accuracy is
not required.
The LPRC oscillator is always enabled at a Power-on
Reset because it is the clock source for the PWRT.
After the PWRT expires, the LPRC oscillator remains
on if one of the following is TRUE:
• The Fail-Safe Clock Monitor is enabled
• The WDT is enabled
• The LPRC oscillator is selected as the system
clock via the COSC<2:0> control bits in the
OSCCON register
If one of the above conditions is not true, the LPRC
shuts off after the PWRT expires.
FIN PLL
Multiplier FOUT
4 MHz-10 MHz x4 16 MHz-40 MHz
4 MHz-10 MHz x8 32 MHz-80 MHz
4 MHz-7.5 MHz x16 64 MHz-120 M Hz
Note: OSCTUN functionality has been provided
to help customers compensate for
temperat ure ef fects on the FRC frequenc y
over a wide range of temperatures. The
tuning step size is an approxi mation and i s
neither chara c ter i zed nor tested.
Note: When a 16x PLL is used, the FRC
frequency must not be tuned to a
frequency greater than 7.5 MHz.
TUN<3:0>
Bits FRC Frequency
0111 +10.5%
0110 +9.0%
0101 +7.5%
0100 +6.0%
0011 +4.5%
0010 +3.0%
0001 +1.5%
0000 Center Frequency (oscillator is
running at calibrated frequency)
1111 -1.5%
1110 -3.0%
1101 -4.5%
1100 -6.0%
1011 -7.5%
1010 -9.0%
1001 -10.5%
1000 -12.0%
Note 1: OSC2 pin function is determined by the
Primary Oscillator mode selection
(FPR<4:0>).
2: OSC1 pin cannot be used as an I/O pin
even if the secondary oscillator or an
internal clock source is selected at all
times.
dsPIC30F3014/4013
DS70138G-page 146 2010 Microchip Technology Inc.
20.2.7 FAIL-SAFE CLOCK MONITOR
The Fail-Saf e Cl oc k Mo nit or (F SCM) al low s the devic e
to conti nue to ope rate even i n th e event o f an oscilla tor
failure. The FSCM functi on i s e nab le d by ap pro pria t el y
programming the FCKSM Configuration bits (clock
switch and monito r sele cti on bits ) in th e FOSC Devi ce
Config uration regi ster. If the FSCM funct ion is ena bled,
the LPRC internal oscillator runs at all times (except
during Sl eep m ode) and is not su bje ct to control by th e
SWDTEN bit.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
syste m cl oc k ov er t o the FRC os cil la t or. Th e u se r th en
has the option to either attempt to restart the oscillator
or exec ute a controlled shutdown. The user may decide
to treat th e tra p as a warm Reset by simply loa din g th e
Reset address into the oscillator fail trap vector. In this
event, the CF (Clock Fail) status bit (OSCCON<3>) is
also set whenever a clock failure is recognized.
In the event of a clock failure, the WDT is unaffected
and continues to run on the LPRC clock.
If th e oscillator h as a very slow st art-up time coming o ut
of POR, BOR or Sleep, it is possible that the PWRT
timer will expire before the oscillator has started. In
such cases, the FSCM is activated and the FSCM initi-
ates a clock failure trap, and the COSC<2:0> bits are
loaded with FRC oscillator selection. This effectively
shuts off the original oscillator that was trying to start.
The user may detect this situation and restart the
oscillator in the clock fail trap ISR.
Upon a clock failure detection, the FSCM module
initiates a clock swi tch to the FRC osci lla tor as fol lo ws:
1. The COSC bits (OSCCON<14:12>) are loaded
with the FRC oscillator selection value.
2. CF bit is set (OSCCON<3>).
3. OSWEN control bit (OSCCON<0>) is cleared.
For the purpose of clock switching, the clock sources
are sectioned into four groups:
• Primary
• Secondary
• Internal FRC
• Internal LPRC
The user can switch between these functional groups
but canno t switch between options within a group. If the
primary group is selected, then the choice within the
group is always determined by the FPR<4:0>
Configuration bits.
The OSC CON register h olds the co ntrol and status bits
related to clock switching.
• COSC<2:0>: Read-only status bits always reflect
the current oscillator group in effect.
• NOSC<2:0>: Control bits which are written to
indicate the new oscillator group of choice.
- On POR and BOR, COSC<2:0> and
NOSC<2:0> are both loaded with the
Configuration bit values, FOS<2:0>.
• LOCK: The LOCK status bit indicates a PLL lock.
• CF: Read-only status bit indicating if a clock fail
detect has occurred.
• OSWEN: Control bit changes from a ‘0’ to a ‘1’
when a clock transition sequence is initiated.
Clearing the OSWEN control bit aborts a clock
transition in progress (used for hang-up
situations).
If Con figurati on bit s, FC KSM<1:0> = 1x, then the cl ock
switching and Fail-Safe Clock Monitor functions are
disabled. This is the default Configuration bit setting.
If clock switching is disabled, then the FOS<2:0> and
FPR<4:0> bits directly control the oscillator selection
and the COSC<2:0> bits do not control the clock
selection. However, these bits reflect the clock source
selection.
20.2.8 PROTECTION AGAINST
ACCIDENTAL WRITES TO OSCCON
A write to the OSCCON register is intentionally made
difficult because it controls clock switching and clock
scaling.
To write to the OSCCON low byte, the following code
sequence must be executed without any other
instructions in between:
Byte Write 0x46 to OSCCON low
Byte Write 0x57 to OSCCON low
Byte wri te is allo wed for one i nstruction cycle. Wr ite the
desired value or use bit manipulation instruction.
To write to the OSCCON high byte, the following
instructions must be executed without any other
instructions in between:
Byte Write 0x78 to OSCCON high
Byte Write 0x9A to OSCCON high
Byte wri te is allo wed for one i nstruction cycle. Wr ite the
desired value or use bit manipulation instruction.
Note: The application should not attempt to
switch to a clock of frequency lower than
100 kH z whe n the Fail-Safe C lo ck M oni tor
is enabled. If such clock switching is
performed, the device may generate an
oscillator fail trap and switch to the Fast
RC os cillator.
2010 Microchip Technology Inc. DS70138G-page 147
dsPIC30F3014/4013
20.3 Oscillator Control Registers
The oscillators are controlled with two SFRs,
OSCCON and OSCTUN and one Configuration
register, FOSC.
Note: The description of the OSCCON and
OSCTUN SFRs, as well as the FOSC
Configuration register provided in this
section are applicable only to the
dsPIC30F3014 and dsPIC30F4013
devices in the dsPIC30F product family.
REGISTER 20-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 R-y R-y R-y U-0 R/W-y R/W-y R/W-y
—COSC<2:0>—NOSC<2:0>
bit 15 bit 8
R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 R/W-0 R/W-0
POST<1:0> LOCK —CF — LPOSCEN OSWEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Group Selection bits (read-only)
111 = PLL oscillator; PLL source selected by FPR<4:0> bits
011 = External oscillator; OSC1/OSC2 pins; external oscillator configuration selected by FPR<4:0>
bits
010 = L PRC internal low-power RC
001 = FRC internal fast RC
000 = LP crystal oscillator; SOSCI/SOSCO pins
Set to FOS<2:0> val ues on POR or BO R. Loaded with NOSC <2 :0> a t the c ompl etio n of a suc cess ful
clock swit ch. Set t o FRC value when FSCM de tects a failure and switches clock to FRC.
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Group Selection bits
111 = PLL Oscillator; PLL source selected by FPR<4:0> bits
011 = External oscillator; OSC1/OSC2 pins; external oscillator configuration selected by FPR<4:0>
bits
010 = L PRC internal low-power RC
001 = FRC internal fast RC
000 = LP crystal oscillator; SOSCI/SOSCO pins
Set to FOS<2:0> values on POR or BOR.
bit 7-6 POST<1:0>: Oscill ator Postscaler S election bits
11 = Oscillator postscaler divides clock by 64
10 = Oscillator postscaler divides clock by 16
01 = Oscillator postscaler divides clock by 4
00 = Oscillator postscaler does not alter clock
dsPIC30F3014/4013
DS70138G-page 148 2010 Microchip Technology Inc.
bit 5 LOCK: PLL Lock Sta tus bit (read-only )
1 = Indicates that PLL is in lock
0 = Indicates that PLL is out of lock (or disabled)
Reset on POR or BOR. Reset when a valid clock switching sequence is initiated. Set when PLL lock
is achie ved af ter a PL L sta rt. Res et when lo ck is l ost. Read zero whe n PLL is not se lected a s a syst em
clock
bit 4 Unimplemented: Read as ‘0’
bit 3 CF: Clock Fail Detect bit (read/clearable by application)
1 = FSCM has detected clock failure
0 = FSCM has NOT detected clock failure
Reset on POR or BOR. Reset when a valid clock switching sequence is initiated. Set when clock fail
detected
bit 2 Unimplemented: Read as ‘0’
bit 1 LPOSCEN: 32 kHz Secondary (LP) Oscillator Enable bit
1 = Secondary oscillator is enabled
0 = Secondary oscillator is disabled
Reset on POR or BOR.
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Request oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is co mplet e
Reset on POR or BOR. Reset after a successful clock switch. Reset after a redundant clock switch.
Reset after FSCM switches the oscillator to (Group 1) FRC.
REGISTER 20-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
2010 Microchip Technology Inc. DS70138G-page 149
dsPIC30F3014/4013
REGISTER 20-2: OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — TUN<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3-0 TUN<3:0>: TUN Field Low er Two bits
The four-bit field specified by TUN<3:0> specifies the user tuning capability for the internal fast RC
oscillator (nominal 7.37 MHz).
0111 = Maximu m frequency
0110 =
0101 =
0100 =
0011 =
0010 =
0001 =
0000 = Center frequency, oscillator is running at calibrated frequency
1111 =
1110 =
1101 =
1100 =
1011 =
1010 =
1001 =
1000 = Minimum fre quency
dsPIC30F3014/4013
DS70138G-page 150 2010 Microchip Technology Inc.
REGISTER 20-3: FOSC: OSCILLATOR CONFIGURATION REGISTER
UUUUUUUU
— — — — — — — —
bit 23 bit 16
R/P R/P U U U R/P R/P R/P
FCKSM<1:0> — — —FOS<2:0>
bit 15 bit 8
U U U R/P R/P R/P R/P R/P
— — —FPR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-16 Unimplemented: Read as ‘0’
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 13-11 Unimplemented: Read as ‘0’
bit 10-8 FOS<2:0>: Oscillator Group Selection on POR bits
111 = PLL oscillator; PLL source selected by FPR<4:0> bits (see Table 20-2)
011 = EXT: External Oscillator; OSC1/OSC2 pins; external oscillator configuration selected by
FPR<4:0> bits
010 = LPRC: Internal Low-Power RC
001 = FRC: Internal Fast RC
000 = LPOSC: Low-Power Crystal Oscillator; SOSCI/SOSCO pins
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 FPR<4:0>: Oscillator Selection within Primary Group bits (see Table 20-2)
2010 Microchip Technology Inc. DS70138G-page 151
dsPIC30F3014/4013
20.4 Reset
The dsPIC30F3014/4013 differentiates between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset (during normal
operation)
e) Programmable Brown-out Reset (BOR)
f) RESET Inst ruction
g) Reset caused by trap lockup (TRAPR)
h) Reset caused by illegal opcode or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
Dif fer ent regi sters a re a ffe cted in dif fe rent w ays by var-
ious Reset conditions. Most registers are not affected
by a WD T wake-u p sinc e this is view ed as the resum p-
tion of normal operation. Status bits from the RCON
register are set or cleared differently in different Reset
situations, as indicated in Table 20-5. These bits are
used in s of twa re to de term in e the natu re of th e Res et.
A block d iag ram of the On -C hi p Res et C irc ui t is sho wn
in Figure 20-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internall y generated Res ets do not drive MCLR pi n low .
FIGURE 20-2: RES E T SYSTEM BLOCK DIAGRAM
20.4.1 POR: POW ER- ON RESE T
A power-on event generates an internal POR pulse
when a VDD rise is detected. The R eset pulse occurs at
the POR ci rcuit thres hold volt age (VPOR) wh ich is nom -
inally 1.85V. The device supply voltage characteristics
must meet specified starting voltage and rise rate
requirements. The POR pulse resets a POR timer and
places the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator configuration fuses.
The POR circuit inserts a small delay, TPOR, which is
nominally 10 s and ensures that the device bias
circuits are stable. Furthermore, a user-selected
power-up time-out (TPWRT) is applied. The TPWRT
parameter is based on device Configuration bits and
can be 0 ms (no delay), 4 ms, 16 ms, or 64 ms. The
total delay is at device power-up, TPOR + TPWRT. When
these de lay s have expired, SYSRST i s ne ga ted o n th e
next lea din g e dge of the Q1 clo ck an d th e PC jumps to
the Reset vector.
The timing for the SYSRST signal is shown in
Figure 20-3 through Figure 20-5.
S
RQ
MCLR
VDD
VDD Rise
Detect POR
SYSRST
Sleep or Idle
Brown-out
Reset BOREN
RESET
Instruction
WDT
Module
Digital
Glitch Filter
BOR
Trap Conflict
Illegal Opcode/
Uninitialized W Register
dsPIC30F3014/4013
DS70138G-page 152 2010 Microchip Technology Inc.
FIGURE 20-3: TIME-OUT SEQU ENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 20-4: TIME-OUT SEQU ENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 20-5: TIME-OUT SEQU ENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL Reset
MCLR
TPWRT
TOST
VDD
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL Reset
MCLR
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL Reset
TPWRT
TOST
2010 Microchip Technology Inc. DS70138G-page 153
dsPIC30F3014/4013
20.4.1.1 POR with Long Crystal S tart-up Time
(with FSCM Enabled)
The osci ll ator s t art-up circuit r y is not linked to the POR
circuitry. Some crystal circuits (especially low-
frequency crystals) have a relatively long start-up time.
Therefore, one or more of the following conditions is
possible after the POR timer and the PWRT have
expired:
• The oscillator circuit has not begun to oscillate.
• The Osc ill ato r Start-up Timer ha s not expi red (if a
crystal oscillator is used).
• The PLL has not achieved a LOCK (if PLL is
used).
If th e FSCM is enabled and one of th e above c onditions
is tr ue, a c lock fa ilure trap occu rs. The devi ce aut omat-
ically switches to the FRC oscillator and the user can
switch to the desired crystal oscillator in the trap ISR.
20.4.1.2 Operating without FSCM and PWRT
If the FSCM is disabled and the Power-up Timer
(PWRT) is also disabled, then the device exits rapidly
from Reset on power-up. If the clock source is FRC,
LPRC, ERC or EC, it will be active immediately.
If the FSCM is disabled and the system clock has not
start ed, the de vice w ill be in a frozen st ate at th e Res et
vector until the system clock starts. From the user’s
perspective, the device appears to be in Reset until a
system clo ck is available.
20.4.2 BOR: PRO GR A MMABL E
BROWN-OUT RESET
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit. The main purpose of
the BOR mod ul e is to ge nerate a devic e Res et whe n a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (i.e.,
missing portions of the AC cycle waveform due to bad
power tr ansmission lines, or voltage sags due to exces-
sive current draw when a larg e in duc tiv e l oad is turne d
on).
The BOR module allows selection of one of the
following voltage trip points (see Table 23-11):
•2.6V-2.71V
•4.1V-4.4V
• 4.58V-4.73V
A BOR generates a Reset pulse, which resets the
device . The BO R select s the cl ock sourc e based on the
device Configuration bit values (FOS<2:0> and
FPR<4:0>). Furthermore, if an oscillator mode is
selected, the BOR activates the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock is held until
the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the POR time-out (TPOR) and the PWRT
time-out (TPWRT) are ap plie d bef ore th e int ernal Res et is
released. If TPWRT = 0 and a crystal oscillator is being
used, then a nomi nal del ay of T FSCM = 100 s is applied.
The total delay in this case is (TPOR + TFSCM).
The BOR status bi t (RCON< 1>) is set to indic ate tha t a
BOR has occurred. The BOR circuit, if enabled, contin-
ues to operate while in Sle ep or Id le m od es a nd res et s
the device should VDD fall below the BOR threshold
voltage.
FIGURE 20-6: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
Note: The BO R voltage tr ip point s indicated here
are nominal values provided for design
guidance only. Refer to the Electrical
Specifications in the specific device data
sheet for BOR voltage limit specifications.
Note: Dedicated supervisory devices, such as
the MCP1XX and MCP8XX, may also be
used as an external Power-on Reset
circuit.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R should be suitably chosen so as to make
sure that the voltage drop across R does not
violate the device’s electrical specifications.
3: R1 should be suitably chosen so as to limit
any current flowing into MCLR from exte r n al
capacitor C, in the event of MCLR/VPP pin
breakdown due to Electrostatic Discharge
(ESD), or Electrical Overst ress (EO S).
C
R1
R
D
VDD
dsPIC30F
MCLR
dsPIC30F3014/4013
DS70138G-page 154 2010 Microchip Technology Inc.
Table 20-5 shows the Reset conditions for the RCON
register. Since the c ontrol bits within the RCON register
are R/W, the informati on in the table means t ha t all the
bits are negated prior to the action specified in the
conditi on column.
TABLE 20-5: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 1
Table 20-6 shows a second example of the bit
conditions for the RCON register. In this case, it is not
assu med th e use r has s et/ cle ared s peci fic bits pr ior to
action specified in the condition column.
TABLE 20-6: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2
Condition Program
Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset 0x000000 000000011
Brown-out Reset 0x000000 000000001
MCLR Reset during normal
operation 0x000000 001000000
Software Reset during
normal ope rati on 0x000000 000100000
MCLR Reset during Sleep 0x000000 001000100
MCLR Reset during Idle 0x000000 001001000
WDT Time- out Reset 0x000000 000010000
WDT Wake- up PC + 2 000010100
Interrupt Wake-up from Sleep PC + 2(1) 000000100
Clock Failure Trap 0x000004 000000000
Trap Reset 0x000000 100000000
Illegal Operation Trap 0x000000 010000000
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’
Note 1: When the wak e-up is due to an en abled interrupt , the PC is loa ded w ith the co rrespondi ng interru pt vec tor.
Condition Program
Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset 0x000000 0 0 0000011
Brown-out Reset 0x000000 u u uuuuu01
MCLR Reset during normal
operation 0x000000 u u 10000uu
Software Reset during
normal ope rati on 0x000000 u u 01000uu
MCLR Reset during Sleep 0x000000 u u 1u001uu
MCLR Reset during Idle 0x000000 u u 1u010uu
WDT Time- out Reset 0x000000 u u 00100uu
WDT Wake- up PC + 2 u u uu1u1uu
Interrupt Wake-up from Sleep PC + 2(1) u u uuuu1uu
Clock Failure Trap 0x000004 u u uuuuuuu
Trap Reset 0x000000 1 u uuuuuuu
Illegal Operation Reset 0x000000 u 1 uuuuuuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’
Note 1: When the wake-up is du e to an enable d interr upt, the PC is loade d with th e corres pondi ng int errupt v ector.
2010 Microchip Technology Inc. DS70138G-page 155
dsPIC30F3014/4013
20.5 Watchdog Timer (WDT)
20.5.1 WATCHDOG TIMER OPERATION
The primary function of the Watchdog Timer (WDT) is
to reset the proces sor in the event of a software mal-
function. The WDT is a free-running timer that runs off
an on-chip RC oscillator, requiring no external compo-
nent. Therefore, the WDT timer continues to operate
even if the main processor clock (e.g., the crystal
oscillator) fails.
20.5.2 ENABLING AND DISABLING
THE WDT
The Watchdog Timer can be “Enabled” or “Disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register, FWDT.
Setting FWDTEN = 1 enables the W atchdog T imer . The
enabling is done when programming the device. By
default, afte r chip erase, FWDT EN bit = 1. Any device
programmer capable of programming dsPIC30F
devices allows programming of this and other
Conf i gu rati on bi ts.
If enabled, the WDT increments until it overflows or
“times out”. A WDT time-out forces a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
If a WDT times out during Sleep, the device wakes up.
The WDTO bit in the RCON register is cleared to
indicate a wake-up result ing from a WDT time-out.
Setting FWDTEN = 0 allows user software to enable/
disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
20.6 Low-Voltage Detect
The Low-Voltage Detect (LVD) module is used to
detect when the VDD of the device drops below a
threshold value, VLVD, which is determined by the
LVDL<3:0> bits (RCON<11:8>) and is thus user pro-
grammable. The internal voltage reference circuitry
requires a nominal amount of time to stabilize, and the
BGST bit (RCON<13>) indicates when the voltage
reference has stabilized.
In some devices, the LVD threshold voltage may be
applied extern al ly on the LVDIN pin.
The LVD module is enabled by setting the LVDEN bit
(RCON<12>).
20.7 Power-Saving Modes
There are tw o power-s avin g st ates that c an be en tered
through the execu tio n of a spe cial inst ruc tion, PWRSAV;
these are Sleep and Idle.
The format of the PWRSAV instruction is as follows:
PWRSAV <parameter>, where ‘parameter’ defines
Idle or Sleep mode.
20.7.1 SLEE P MODE
In Sleep m ode, th e clo ck to the C PU and p eriphe rals i s
shut down. If an on-chip oscillator is being used, it is
shut down .
The Fail-Safe Clock Monitor is not functional during
Sleep since there is no clock to monitor. However, the
LPRC clock remains active if WDT is operational durin g
Sleep.
The brown-out protection circuit and the Low-Voltage
Detect (LVD) circuit, if enabled, remains functional
during Sleep.
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
• any interrupt that is individually enabled and
meets the required priority level
• any Reset (POR, BOR and MCLR)
• WDT time-out
On wakin g up from Sleep mode, th e processo r rest arts
the sam e clo ck th at wa s a ct ive pri or to e ntry in to Slee p
mode. When clock switching is enabled, bits,
COSC<2:0>, determine the oscillator source to be
used on wake-u p. If cloc k switch is disab led, then there
is only one system clock.
If the clock source is an oscillator, the clock to the
device is held off until OST times out (indicating a
stable oscillator). If PLL is used, the system clock is
held off until LOCK = 1 (indicating that the PLL is
stab le). I n eit her c ase, TPOR, TLOCK and TPWRT delay s
are applied.
If EC, FRC, LPRC or ERC oscillators are used, then a
delay of TPOR (~ 10 s) is applied. This is the smallest
delay possible on wake-up from Sleep.
Moreover, if the LP oscillator was active during Sleep
and LP is the oscillator used on wake-up, then the start-
up delay is equal to TPOR. PWRT delay and OST timer
delay are not applied. In order to have the smallest
possible start-up delay when waking up from Sleep,
one of these faste r wake-up op tions shoul d be selecte d
before entering Sleep.
Note: If a POR or BOR occurred, the selection of
the oscillator is based on the FOS<2:0>
and FPR<4:0> Configuration bits.
dsPIC30F3014/4013
DS70138G-page 156 2010 Microchip Technology Inc.
Any interrupt that is individually enabled (using the cor-
responding IE bit) and meets the prevailing priority level
can wake-up the processor. The processor processes
the interrupt and branch to the ISR. The SLEEP status
bit in the RCON register is set upon wake-up.
All Resets wake up the processor from Sleep mode.
Any Reset, other than POR, sets the Sleep status bit.
In a POR, the SLEEP bit is cleared.
If the W a tchdog T im er is enabl ed, the proc essor wakes
up from Sleep mode upon WDT time-out. The SLEEP
and WDTO status bits are both set.
20.7.2 IDLE MODE
In Idle mode, the clock to the CPU is shut down while
peripher als keep running. Unlike Slee p mode, the clock
sour ce rem ains active .
Several peripherals have a control bit in each module
that allows them to operate during Idle.
The LPRC fail-safe clock remains active if clock fail ure
detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions has occurred:
• any interrupt that is individually enabled (IE bit is
‘1’) and meets the required priority level
• any Reset (POR, BOR, MCLR)
• WDT time-out
Upon wake-up from Idle mode, the clock is re-applied
to the CPU and instruction execution begins immedi-
ately, st arti ng with the in struction fol lowi ng the PWRSAV
instruction.
Any interrupt that is individually enabled (using the IE
bit) and meets the prevailing priority level is able to
wake up the processor. The processor processes the
interrupt and branches to the ISR. The IDLE status bit
in the RCON register is set upon wake-up.
Any Res et other than POR set s the IDLE st atu s bit. On
a POR, the IDLE bit is cleared.
If Watchdog Timer is enabled, the processor wakes up
from Idle mode upon WDT time-out. The Idle and
WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involv ed in wa ke -up from Idle.
20.8 Device Confi guration Registers
The Configuration bits in each device Configuration
register specify some of the device modes and are
prog ramme d by a de vice prog ra mmer, or by us ing the
In-Circuit Serial Programming™ (ICSP™) feature of
the device. Each device Configuration register is a
24-bit register, but only the lower 16 bits of each regis-
ter are used to hold configuration data. There are five
device Configuration registers available to the user:
1. FOSC (0xF80000): Oscillator Configuration
Register
2. FWDT (0xF80002): Watchdog Timer
Configu ration Register
3. FBORPOR (0xF80004): BOR and POR
Configu ration Register
4. FGS (0xF8000A): General Code Segment
Configu ration Register
5. FICD (0xF8000C): Debug Configuration
Register
The placement of the Configuration bits is automati-
cally ha ndled when you sel ect the device in your device
programmer . The desired state of the Configuration bit s
may be sp ecified i n the source code (depen dent on the
language tool used), or through the programming
interface. After the device has been programmed, the
application software may read the Configuration bit
values through the table read instructions. For
addition al informa tion, please refer to the Programming
Specifications of the devic e.
Note: In spite of various delays applied (TPOR,
TLOCK and TPWRT), the crystal oscillator
(and PLL) may not be active at the end of
the time-out (e.g., for low-frequency crys-
tals). In such cases, if FSCM is enabled, the
device detects this as a clock failure and
processes the clock failure trap, the FRC
oscil lator is e nab led an d the user will have
to re-enabl e the crystal oscillator. If FSCM
is not enabled, the device simply suspends
execution of code until the clock is stable
and remain in Sleep until the oscillator clock
has started.
Note: If the code protection Configuration fuse
bits (FGS<GCP> and FGS<GWRP>)
have been programmed, an erase of the
entire code-protected device is only
possib le at vol tages VDD 4.5V.
2010 Microchip Technology Inc. DS70138G-page 157
dsPIC30F3014/4013
20.9 Peripheral Module Disable (PMD)
Registers
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a pe rip heral is di sa bled via t he a ppropri ate PMD
control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled so
writes to those regis ters have no e ffect and r ead values
are invalid.
A peripheral module is only enabled if both the
associated bit in the PMD register is cleared and the
periphera l is supported by the spec ific dsPIC DSC vari-
ant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
20.10 In-Circuit Debugger
When M PLAB® ICD 2 is sele cted as a debugger , the in-
circuit debugg ing fun ctiona lity i s enab led. Thi s func tion
allows simple debugging functions when used with
MPLAB IDE. When the device has this feature e nabled,
some of the resources are not available for general
use. These resources include the first 80 bytes of data
RAM and two I/O pins.
One of fo ur pair s of deb ug I/O p ins m ay b e se lec t ed b y
the user using configuration options in MPLAB IDE.
These pin pairs are named EMUD/EMUC, EMUD1/
EMUC1, EMUD2/EMUC2 and MUD3/EMUC3.
In each c as e, th e se lec te d EMU D p in i s th e Em ula tion/
Debu g Data li ne, and th e EMUC pi n is the E mulati on/
Debug Clock line. These pins interface to the MPLAB
ICD 2 module available from Microchip. The selected
pair of de bug I/O pi ns is used by MPL AB ICD 2 to send
commands and receive responses, as well as to send
and receive data. To use the in-circuit debugger
function of the device, the design must i mplement ICSP
connections to MCLR, VDD, VSS, PGC, PGD and the
selected EMUDx/EMUCx pin pair.
This gives rise to two possibilities:
1. If EMUD/EMUC is selected as the debug I/O pi n
pair, then only a 5-pin interface is required, as
the EMUD and EMUC pin functions are multi-
plexed with the PGD and PGC pin functions in
all dsPIC30F devices.
2. If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/
EMUC3 is selected as the debug I/O pin pair,
then a 7-pin interface is required, as the
EMUDx/EMUCx pin functions (x = 1, 2 or 3) are
not multiplexed with the PGD and PGC pin
functions.
Note 1: If a PMD bit is set, the corresponding
module is disabled after a delay of 1
inst ruct io n cy cl e. Sim il arly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of 1 instruction
cycle (assuming the module control reg-
isters are already configured to enable
module operation).
2: In the dsPIC30F3014 device, the T4MD,
T5MD, IC7MD, IC8MD, OC3MD,
OC4MD and DCIMD are readable and
writable, and are read as “1” when set.
dsPIC30F3014/4013
DS70138G-page 158 2010 Microchip Technology Inc.
TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP(1)
TABLE 20-8: DEVICE CONFIGURATION REGIS TER MAP(1)
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
RCON 0740 TRAPR IOPUWR BGST LVDEN LVDL<3:0> EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 2)
OSCCON 0742 — COSC<2:0> — NOSC<2:0> POST<1:0> LOCK —CF — LPOSCEN OSWEN (No te 3)
OSCTUN 0744 — — — — — — — — — — — — TUN3 TUN2 TUN1 TUN0 0000 0000 0000 0000
PMD1 0770 T5MD(4) T4MD(4) T3MD T2MD T1MD —— DCIMD(4) I2CMD U2MD U1MD —SPI1MD — C1MD ADCMD 0000 0000 0000 0000
PMD2 0772 IC8MD(4) IC7MD(4) — — — —IC2MDIC1MD— — — —OC4MD
(4) OC3MD(4) OC2MD OC1MD 0000 0000 0000 0000
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of regi ster bi t fields.
2: Reset state depends on type of Reset.
3: Reset state depends on Configuration bits.
4: These bits are not available in dsPIC30F3014 devices.
Name Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FOSC F80000 FCKSM<1:0> — — —FOS<2:0>— — — FPR<4:0>
FWDT F80002 FWDTEN — — — — — — — — — FWPSA<1:0> FWPSB<3:0>
FBORPOR F80004 MCLREN — — — —
PWMPIN
(2)
HPOL
(2)
LPOL
(2)
BOREN —BORV<1:0>——FPWRT<1:0>
FBS F80006 —— Reserved(3) ——— Reserved(3) — — — — Reserved(3)
FSS F80008 —— Reserved(3) —— Reserved(3) — — — — Reserved(3)
FGS F8000A — — — — — — — — — — — — — Reserved(4) GCP GWRP
FICD F8000C BKBUG COE — — — — — — — — — — — —ICS<1:0>
Legend: — = unimplemented bit, read as ‘0’
Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
2: These bits are reserved (read as ‘1’ and must be programmed as ‘1’).
3: Reserved bits read as ‘1’ and must be programmed as ‘1’.
4: The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
2010 Microchip Technology Inc. DS70138G-page 159
dsPIC30F3014/4013
21.0 INSTRUCTION SET SUMMARY
The dsPIC30F instruction set adds many
enhancements to the previous PIC® MCU instruction
sets , while mai ntaining an easy mi gration from PIC
MCU instruction sets.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode which specifies the instruction
type, and one or more operands which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five bas ic ca tegories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• DSP operations
• Control operations
Table 21-1 shows the general symbols used in
des c ribing the instructions.
The dsPIC30F instruction set summary in Table 21-2
lists all the instructions, along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand which is typically a
register ‘Wb’ without any address modifier
• The second source operand which is t ypically a
register ‘Ws’ with or without an address modifier
• The destination of the result which is typically a
register ‘Wd’ with or without an address modifier
However , word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could either be the file
register ‘f’ or the W0 regis ter, which is de not ed a s
‘WREG’
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register ‘Wb’)
The litera l instruct ions that invo lve data m ovement ma y
use some of the following operands:
• A lite ral value to b e load ed into a W regi ster or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand which is a register ‘Wb’
without any addre s s modifier
• The second source operand which is a literal
value
• The dest ination of the result (only if not the s ame
as the first source operand) which is typically a
register ‘Wd’ with or without an address modifier
The MAC class of DSP instructions may use some of the
following operands:
• The accumulator (A or B) to be used (required
operand)
• The W re gisters to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accu mulat or write-back destinatio n
The other DSP instructions do not involve any
multipl ic ati on, and may include:
• The accumulator to be used (required )
• The source o r destin ation ope rand (des ignated as
Wso or Wdo, respectively) with or without an
address modifier
• The amou nt of shif t spe cifie d by a W re giste r ‘Wn’
or a literal value
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the table read and table write
instructions
All instructions are a single word, except for certain
double word instructions, which were made double
word instructions so that all the required information is
available in these 48 bits. In the second word, the
8MSbs are ‘0’s. I f t hi s se cond w o rd i s ex ec ut ed as an
ins truction (by its elf) , it execut es as a NOP.
Note: This data sheet summarizes features of
this gr oup of dsPIC30F d evice s and is not
intended to be a complete reference
source. For m ore in formati on on the CPU ,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Pro-
grammer’s Reference Manual”
(DS70157).
dsPIC30F3014/4013
DS70138G-page 160 2010 Microchip Technology Inc.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or
the program counter is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles with the additional instruction
cycle(s) executed as a NOP. Notab le excep tions are th e
BRA (unconditional/computed branch), indirect CALL/
GOTO, all t able reads and writes, and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles. Certain instructions that involve
skip ping over the subs equent instru ction require either
two or three cycles if the skip is performed, depending
on whether the instruction being skipped is a single-
word or two-word instruction. Moreover, double-word
moves require two cycles. The double-word
ins truct ions execute in two instru ction cycles.
Note: For more details on the instruction set,
refer to the “16-bit DSC and MCU Pro-
grammer’s Reference Manual”
(DS70157).
TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field Description
#tex t Me ans literal de fined by “text”
(text) Means “content of text”
[text] Means “the location addressed by text”
{ } Optional field or operation
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
Acc One of two accumulators {A, B}
AWB Accumulator Write-Back Destination Address register {W13, [W13]+=2}
bit4 4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address {0x0000...0x1FFF}
lit1 1-bit unsigned literal {0,1}
lit4 4-bit unsigned literal {0...15}
lit5 5-bit unsigned literal {0...31}
lit8 8-bit unsigned literal {0...255}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14 14-bit unsigned literal {0...16384}
lit16 16-bit unsigned literal {0...65535}
lit23 23-bit unsigned literal {0...8388608}; LSB must be 0
None Field does not require an entry, may be blank
OA, OB, SA, SB DSP Status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Slit16 16-bit signed literal {-32768...32767}
Slit6 6-bit signed literal {-16...16}
2010 Microchip Technology Inc. DS70138G-page 161
dsPIC30F3014/4013
Wb Base W register {W0..W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Di vi den d, Divi so r Working regist er p air (direct addressing)
Wm*Wm Multiplicand and Multiplier working register pair for Square instructions
{W4*W4,W5*W5,W6*W6,W7*W7}
Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions
{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}
Wn One of 16 working registers {W0..W15}
Wnd One of 16 destination working registers {W0..W15}
Wns One of 16 source working registers {W0..W15}
WREG W0 (working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X data space prefetch address register for DSP instructions
{[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,
[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,
[W9+W12],none}
Wxd X data space prefetch destination register for DSP instructions {W4..W7}
Wy Y data space prefetch address register for DSP instructions
{[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,
[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,
[W11+W12], none}
Wyd Y data space prefetch destination register for DSP instructions {W4..W7}
TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field Description
dsPIC30F3014/4013
DS70138G-page 162 2010 Microchip Technology Inc.
TABLE 21-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemoni
cAssembly Syntax Description # of
Words # of
Cycles Status Flag s
Affected
1ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB
ADD f f = f + WREG 1 1 C,DC,N,OV,Z
ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB
2ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z
3AND AND f f = f .AND. WREG 1 1 N,Z
AND f,WREG WREG = f .AND. WREG 1 1 N,Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z
4ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z
5BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
6BRA BRA C,Expr Branch if Carry 1 1 (2) None
BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None
BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None
BRA GT,Expr Branch if Greater than 1 1 (2) None
BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None
BRA LE,Expr Bra nch if Less than or Equal 1 1 (2) None
BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None
BRA LT,Expr Branch if Less than 1 1 (2) None
BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None
BRA N,Expr Branch if Negative 1 1 (2) None
BRA NC,Expr Branch if Not Carry 1 1 (2) None
BRA NN,Expr Branch if Not Negative 1 1 (2) None
BRA NOV,Expr Branch if Not Overflow 1 1 (2) None
BRA NZ,Expr Branch if Not Zero 1 1 (2) None
BRA OA,Expr Branch if Accumulator A Overflow 1 1 (2) None
BRA OB,Expr Branch if Accumulator B Overflow 1 1 (2) None
BRA OV,Expr Branch if Overflow 1 1 (2) None
BRA SA,Expr Branch if Accumulator A Saturated 1 1 (2) None
BRA SB,Expr Branch if Accumulator B Saturated 1 1 (2) None
BRA Expr Branch Unconditionally 1 2 None
BRA Z,Expr Branch if Zero 1 1 (2) None
BRA Wn Computed Branch 1 2 None
7BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
8BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
2010 Microchip Technology Inc. DS70138G-page 163
dsPIC30F3014/4013
9BTG BTG f,#bit4 Bi t Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1
(2 or 3) None
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1
(2 or 3) None
11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1
(2 or 3) None
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1
(2 or 3) None
12 BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
14 CALL CALL lit23 Call Subroutine 2 2 None
CALL Wn Call Indirect Subroutine 1 2 None
15 CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB
16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep
17 COM COM f f = f 11 N,Z
COM f,WREG WREG = f 11 N,Z
COM Ws,Wd Wd = Ws 11 N,Z
18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z
CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z
19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z
CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z
20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,Ws Compare Wb with Ws, with Borrow
(Wb – Ws – C)1 1 C,DC,N,OV,Z
21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, Skip if = 1 1
(2 or 3) None
22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, Skip if > 1 1
(2 or 3) None
23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, Skip if < 1 1
(2 or 3) None
24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, Skip if 11
(2 or 3) None
25 DAW DAW Wn Wn = Decimal Adjust Wn 1 1 C
26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z
DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z
DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z
27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z
DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z
28 DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None
TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemoni
cAssembly Syntax Description # of
Words # of
Cycles Status Flag s
Affected
dsPIC30F3014/4013
DS70138G-page 164 2010 Microchip Technology Inc.
29 DIV DIV.S Wm,Wn Signed 16/16-Bit Integer Divide 1 18 N,Z,C,OV
DIV.SD Wm,Wn Signed 32/16-Bit Integer Divide 1 18 N,Z,C,OV
DIV.U Wm,Wn Unsigned 16/16-Bit Integer Divide 1 18 N,Z,C,OV
DIV.UD Wm,Wn Unsigned 32/16-Bit Integer Divide 1 18 N,Z,C,OV
30 DIVF DIVF Wm,Wn Sign ed 16/16-bit Fractional Divide 1 18 N,Z,C,OV
31 DO DO #lit14,Expr Do Code to PC+Expr, lit14 + 1 Times 2 2 None
DO Wn,Expr Do Code to PC+Expr, (Wn) + 1 Times 2 2 None
32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,
SA,SB,SAB
33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,
SA,SB,SAB
34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C
36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
38 GOTO GOTO Expr Go to address 2 2 None
GOTO Wn Go to indirect 1 2 None
39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z
INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z
INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z
41 IOR IOR f f = f .IOR. WREG 1 1 N,Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z
42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
43 LNK LNK #lit14 Li nk Fr ame Poin ter 1 1 None
44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z
45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
,
AWB
Multiply and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accum ulate 1 1 OA,OB,O A B,
SA,SB,SAB
46 MOV MOV f,Wn Move f to Wn 1 1 None
MOV f Move f to f 1 1 N,Z
MOV f,WREG Move f to WREG 1 1 N,Z
MOV #lit16,Wn Move 16-Bit Literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-Bit Literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 N,Z
MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None
47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Pr efe tch and Store Accumulato r 1 1 No ne
TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemoni
cAssembly Syntax Description # of
Words # of
Cycles Status Flag s
Affected
2010 Microchip Technology Inc. DS70138G-page 165
dsPIC30F3014/4013
48 MPY MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
49 MPY.N MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None
50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
,
AWB
Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
51 MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) *
Unsigned(Ws) 11 None
MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) *
Signed(Ws) 11 None
MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) *
Unsigned(Ws) 11 None
MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) *
Unsigned(lit5) 11 None
MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) *
Unsigned(lit5) 11 None
MUL f W3:W2 = f * WREG 1 1 None
52 NEG NEG Acc Negate Accumu lato r 1 1 OA,OB,OA B,
SA,SB,SAB
NEG f f = f + 1 1 1 C,DC,N,OV,Z
NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
NEG Ws,Wd Wd = Ws + 1 1 1 C,DC, N,OV,Z
53 NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
54 POP POP f Pop f from Top-of-S tack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to
W(nd):W(nd+1) 12 None
POP.S Pop Shadow Registers 1 1 All
55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W (ns+1 ) to Top-of-Stack (TOS) 1 2 None
PUSH.S Push Shadow Registers 1 1 None
56 PWRSAV PWRSAV #lit1 Go in to Sle ep or Idle mo de 1 1 WDTO, Sleep
57 RCALL RCALL Expr Relative Call 1 2 None
RCALL Wn Computed Call 1 2 None
58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14+1 Times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn)+1 Times 1 1 None
59 RESET RESET Software Device Reset 1 1 None
60 RETFIE RETFIE Return from Interrupt 1 3 (2) None
61 RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None
62 RETURN RETURN Return from Subroutine 1 3 (2) None
63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z
64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z
65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z
TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemoni
cAssembly Syntax Description # of
Words # of
Cycles Status Flag s
Affected
dsPIC30F3014/4013
DS70138G-page 166 2010 Microchip Technology Inc.
66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z
67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None
SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None
68 SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C,N,Z
69 SETM SETM f f = 0xFFFF 1 1 None
SETM WREG WREG = 0xFFFF 1 1 None
SETM Ws Ws = 0xFFFF 1 1 None
70 SFTAC SFTAC Acc,Wn Ar ithm etic Shift Accumulato r by (Wn) 1 1 OA,OB,O A B,
SA,SB,SAB
SFTAC Acc,#Slit6 Arithm etic Shift Accum ulator by Slit6 1 1 OA ,OB,O A B,
SA,SB,SAB
71 SL SL f f = Left Shift f 1 1 C,N,OV,Z
SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z
72 SUB SUB Acc Subtract Accum ulato rs 1 1 OA,OB,OA B,
SA,SB,SAB
SUB f f = f – WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z
73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z
74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG– f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z
75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z
76 SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None
SWAP Wn Wn = Byte Swap Wn 1 1 None
77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None
78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None
79 TBLWTH TBLWTH Ws,Wd Write Ws <7:0 > to Prog<23:16> 1 2 None
80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog< 15: 0> 1 2 None
81 ULNK ULNK Unlink Frame Pointer 1 1 None
82 XOR XOR f f = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
83 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N
TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemoni
cAssembly Syntax Description # of
Words # of
Cycles Status Flag s
Affected
2010 Microchip Technology Inc. DS70138G-page 167
dsPIC30F3014/4013
22.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Progra mmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-C ost D emonstr ation/Development Boards,
Evaluation Kits, and Starter Kits
22.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Deb ugger (so ld separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Exten si ve on-l in e help
• Integration of select third party tools, such a s
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source f iles ( eithe r C or assembly)
• One-tou ch compile o r assemble , and downl oad to
emulator and simulator tools (automatically
updates all project information)
• Debug us ing :
- Source files (C or a s sembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
dsPIC30F3014/4013
DS70138G-page 168 2010 Microchip Technology Inc.
22.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compil ers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
22.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcont rollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compil ers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
process or , and one-s tep driver , and can run on multipl e
platforms.
22.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly co de
• Conditional assembly for multi-purpose
sour ce fil es
• Directives that allow complete control over the
assembly process
22.5 MPLINK Object Linker /
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLA B C18 C Compiler. It can link re locatable ob jects
from precompiled libraries, using directives from a
linker script.
The MPLIB O bject Li brarian manage s the cre ation an d
modification of library files of precompiled code. When
a rout in e from a l ibra ry is cal led fro m a so urc e f ile, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, re placement, delet ion and extraction
22.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the asse mbler to pro duce i ts o bje ct file . The ass embl er
generates relocatable object files that can then be
archived or linke d with other relocatable ob ject files and
arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB IDE compatibility
2010 Microchip Technology Inc. DS70138G-page 169
dsPIC30F3014/4013
22.7 MPLAB SIM Sof tware Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most periph erals and i nternal regi sters.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
developm ent tool .
22.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated D evelopment Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgrad able through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
22.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
device s. It debugs and programs PIC® Flash mi crocon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nect ed to t he des ign e nginee r's PC using a hig h-spee d
USB 2.0 i nte rfac e a nd is co nnected to the t arget with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports al l
MPLAB ICD 2 headers.
22.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most af fordable price point using the powerful graphica l
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller , hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
dsPIC30F3014/4013
DS70138G-page 170 2010 Microchip Technology Inc.
22.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The P ICkit™ 2 Develo pment Program mer/Debu gger i s
a low-cost development tool with an easy to use inter-
face fo r programmin g and debu gging Micr ochip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 famil ies o f 8 -bi t, 1 6-b it, and 32-b it
microcontrollers, and many Microchip Serial EEPROM
produ cts . With Mic rochip ’s power ful MPL AB Integrate d
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file reg ist ers can be ex amin ed and m odifie d.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller , hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
22.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64 ) for me nus an d err or messag es an d a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is in cluded
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer can rea d, verify an d program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPL AB PM3 has high-spe ed comm unications and
optimized algorithms for quick programming of large
memory devices and inc orporates an MMC card for file
storage and data applications.
22.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards includ e prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The board s suppo rt a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory .
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience t he specified d evice. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2010 Microchip Technology Inc. DS70138G-page 171
dsPIC30F3014/4013
23.0 ELECTRIC AL CHARACTERISTICS
This section provides an overview of dsPIC30F electrical characterist ics. Additional information will be provided in future
revisions of this document as it becomes available.
For detailed information about the dsPIC30F architecture and core, refer to the “ds PIC30 F F am il y R ef e ren c e M an u al ”
(DS70046).
Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for
extende d peri ods may af fec t devi ce re liabil ity. Func tional opera tio n of t he de vice at th ese or a ny ot her co ndi tions abov e
the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) (Note 1).....................................-0.3V to (VDD + 0.3V)
Vo lt a ge on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Vo lt a ge on MCLR with respect to VSS .......................................................................................................0V to +13.25V
Maximum curr ent out of VSS pin ...........................................................................................................................300 mA
Maximum curr ent into VDD pin (Note 2)................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (N ote 2)....................................................................................................200 mA
Note 1: V oltage spikes below Vss at the MCLR/VPP pin, induci ng cu rrent s g reater th an 80 m A, may caus e latc h-up.
Thus, a s eries resist or of 50-1 00W sh ould be used when apply ing a “lo w” level to the M CLR/VPP pin, rather
than pulling this pin directly to Vss.
2: Maximum allowable current is a function of device maximum power dissipation. See Table 23-4
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . Thi s is a stress rating on ly and functio nal ope rati on of the de vice a t those or a ny ot her cond itions abo ve those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific
devices, please refer to the dsPIC30F3014/4013 Controller Family table.
dsPIC30F3014/4013
DS70138G-page 172 2010 Microchip Technology Inc.
23.1 DC Characteristics
TABLE 23-1: OPERATING MIPS vs. VOLTAGE
VDD Range Temp Range Max MIPS
dsPIC30FXXX-30I dsPIC30FXXX-20E
4.5-5.5V -40°C to 85°C 30 —
4.5-5.5V -40°C to 125°C — 20
3.0-3.6V -40°C to 85°C 15 —
3.0-3.6V -40°C to 125°C — 10
2.5-3.0V -40°C to 85°C 10 —
TABLE 23-2: THERMAL OPERATING CONDITIONS
Rating Symbol Min Typ Max Unit
dsPIC30F3014-30I
dsPIC30F4013-30I
Operating Junction Temperature Range TJ-40 — +125 °C
Operating Ambient Temperature Range TA-40 — +85 °C
dsPIC30F3014-20E
dsPIC30F4013-20E
Operati ng Junction Temperature Rang e TJ-40 — +150 °C
Operating Ambient Temperature Range TA-40 — +125 °C
Power Dissipation:
Internal ch ip pow er dis sipation:
PDPINT + PI/OW
I/O Pin power dissipation:
Maximum Allo wed Power Dissipation PDMAX (TJ – TA)/JA W
PINT VDD IDD IOH
–=
PI/OVDD VOH–
IOH
VOL IOL
+=
TABLE 23-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol Typ Max Unit Notes
Package Thermal Resistance, 40-pin DIP (P) JA —47°C/W1
Package Thermal Resistance, 44-pi n TQFP (10x10x1mm) JA —39.3°C/W1
Package Thermal Resistance, 44-pin QFN JA —27.8°C/W1
Note 1: Junction to ambient thermal resistance, Theta-ja (JA) numbers are achieved by package simulations.
2010 Microchip Technology Inc. DS70138G-page 173
dsPIC30F3014/4013
TABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise st ated)
Operating temperature -40°C TA +85° C for Industri al
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1) Max Units Conditions
Operating Voltage(2)
DC10 VDD Supply Voltage 2.5 — 5.5 V Indu stri al tem pera ture
DC11 VDD Supply Voltage 3.0 — 5.5 V Extended temperature
DC12 VDR RAM Data Retention Voltage(3) 1.75 — — V
DC16 VPOR VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
——VSS V
DC17 SVDD VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05 — — V/ms 0- 5V in 0.1 sec
0-3V in 60 ms
Note 1: Data in “Typ” column is a t 5V, 2 5°C unles s othe rwise st ate d. Par ameters are for d esign guidan ce onl y and
are not t ested.
2: These parameters are characterized but not tested in manufacturing.
3: This is the limit to which VDD can be lowered without losing RAM data.
dsPIC30F3014/4013
DS70138G-page 174 2010 Microchip Technology Inc.
TABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperat ure -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical Max Units Conditions
Operating Current (IDD)(1)
DC31a 2 4 mA 25°C 3.3V 0.128 MIPS
LPRC (512 kHz)
DC31b 2 4 mA 85°C
DC31c 2 4 mA 125°C
DC31e 4 6 mA 25°C 5VDC31f 4 6 mA 85°C
DC31g 4 6 mA 125°C
DC30a 6 11 mA 25°C 3.3V 1.8 MIPS
FRC (7.37 MHz)
DC30b 6 11 mA 85°C
DC30c 7 11 mA 125°C
DC30e 11 16 mA 25°C 5VDC30f 11 16 mA 85°C
DC30g 11 16 mA 125°C
DC23a 13 20 mA 25°C 3.3V
4 MIPS
DC23b 13 20 mA 85°C
DC23c 14 20 mA 125°C
DC23e 22 31 mA 25°C 5VDC23f 22 31 mA 85°C
DC23g 22 31 mA 125°C
DC24a 27 39 mA 25°C 3.3V
10 MIPS
DC24b 28 39 mA 85°C
DC24c 28 39 mA 125°C
DC24e 46 64 mA 25°C 5VDC24f 46 64 mA 85°C
DC24g 46 64 mA 125°C
DC27d 86 120 mA 25°C 5V 20 MIPSDC27e 85 120 mA 85°C
DC27f 85 120 mA 125°C
DC29a 123 170 mA 25°C 5V 30 MIPS
DC29b 122 170 mA 85°C
Note 1: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loa din g an d s w itc hi ng ra te, os cil la tor ty pe , internal cod e e xe cut ion p attern and te mp erature, also h av e
an imp act on the current c onsumpti on. The tes t condi tions fo r all IDD measureme nt s are as foll ows : OSC1
driven with external square wave from rail-to-rail. All I/O pins are configured as inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disa bled. C PU, SRAM, prog ram m emory and da ta mem ory
are operational. No peripheral modules are operating.
2010 Microchip Technology Inc. DS70138G-page 175
dsPIC30F3014/4013
TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical Max Units Conditions
Operating Current (IDD)(1)
DC51a 1.4 3 mA 25°C 3.3V
0.128 MIPS
LPRC (512 kHz)
DC51b 1.5 3 mA 85°C
DC51c 1.5 3 mA 125°C
DC51e 3 5 mA 25°C 5VDC51f 3 5 mA 85°C
DC51g 3 5 mA 125°C
DC50a 4 6 mA 25°C 3.3V
1.8 MIPS
FRC (7.37 MHz)
DC50b 4 6 mA 85°C
DC50c 4 6 mA 125°C
DC50e 8 11 mA 25°C 5VDC50f 8 11 mA 85°C
DC50g 8 11 mA 125°C
DC43a 7 11 mA 25°C 3.3V
4 MIPS
DC43b 7 11 mA 85°C
DC43c 8 11 mA 125°C
DC43e 13 17 mA 25°C 5VDC43f 13 17 mA 85°C
DC43g 13 17 mA 125°C
DC44a 16 22 mA 25°C 3.3V
10 MIPS
DC44b 16 22 mA 85°C
DC44c 17 22 mA 125°C
DC44e 27 36 mA 25°C 5VDC44f 27 36 mA 85°C
DC44g 28 36 mA 125°C
DC47d 50 65 mA 25°C 5V 20 MIPSDC47e 51 65 mA 85°C
DC47f 52 65 mA 125°C
DC49a 74 95 mA 25°C 5V 30 MIPS
DC49b 75 95 mA 85°C
Note 1: Base IIDLE current is measured with core off, clock on and all modules turned off.
dsPIC30F3014/4013
DS70138G-page 176 2010 Microchip Technology Inc.
TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operati ng tem pera ture -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typical Max Units Conditions
Power-Down Current (IPD)(1)
DC60a 1 — A 25°C 3.3V
Base Power-Down Current(2)
DC60b 3 30 A 85°C
DC60c 30 60 A 125°C
DC60e 2 — A 25°C 5VDC60f 6 45 A 85°C
DC60g 55 90 A 125°C
DC61a 7 11 A 25°C 3.3V
Watchdog Timer Current: IWDT(2)
DC61b 7 11 A 85°C
DC61c 7 11 A 125°C
DC61e 14 21 A 25°C 5VDC61f 14 21 A 85°C
DC61g 14 21 A 125°C
DC62a — — A 25°C 3.3V
Time r1 w/32 kHz Crystal: ITI32(2)
DC62b — — A 85°C
DC62c — — A 125°C
DC62e — — A 25°C 5VDC62f — — A 85°C
DC62g 30 45 A 125°C
DC63a 30 45 A 25°C 3.3V
BOR on: IBOR(2)
DC63b 33 50 A 85°C
DC63c 34 51 A 125°C
DC63e 34 51 A 25°C 5VDC63f 37 56 A 85°C
DC63g 37 56 A 125°C
DC66a 18 27 A 25°C 3.3V
Low-Voltage Detect: ILVD(2)
DC66b 20 30 A 85°C
DC66c 21 32 A 125°C
DC66e 22 33 A 25°C 5VDC66f 23 35 A 85°C
DC66g 24 36 A 125°C
Note 1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. LVD, BOR, WDT, etc. are all switch ed off.
2: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
2010 Microchip Technology Inc. DS70138G-page 177
dsPIC30F3014/4013
TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extende d
Param
No. Symbol Characteristic Min Typ(1) Max Units Conditions
VIL Input Low Voltage(2)
DI10 I/O Pins:
with Schmitt Trigger Buffer VSS —0.2VDD V
DI15 MCLR VSS —0.2VDD V
DI16 OSC1 (in XT, HS and LP modes) VSS —0.2VDD V
DI17 OSC1 (in RC mode)(3) VSS —0.3VDD V
DI18 SDA, SCL VSS —0.3VDD V SM bus disable d
DI19 SDA, SCL VSS — 0.8 V SM bus enabled
VIH Input High Voltage(2)
DI20 I/O Pins:
with Schmitt Trigger Buffer 0.8 VDD —VDD V
DI25 MCLR 0.8 VDD —VDD V
DI26 OSC1 (in XT, HS and LP modes) 0.7 V DD —VDD V
DI27 OSC1 (in RC mode)(3) 0.9 VDD —VDD V
DI28 SDA, SCL 0.7 VDD —VDD V SM bus disable d
DI29 SDA, SCL 2.1 — VDD V SM bus enabled
ICNPU CNXX Pull-up Current(2)
DI30 50 250 400 AVDD = 5V, VPIN = VSS
IIL Input Leakage Current(2,4,5)
DI50 I/O Ports — 0.01 ±1 AVSS VPIN VDD,
Pin at hi gh-i mpedance
DI51 Analog Inp ut Pins — 0.50 — AV
SS VPIN VDD,
Pin at hi gh-i mpedance
DI55 MCLR —0.05±5AVSS VPIN VDD
DI56 OSC1 — 0.05 ±5 AVSS VPIN VDD, XT, HS
and LP Osc mode
Note 1: Data in “Typ” column is a t 5V, 2 5°C unles s othe rwise st ate d. Par ameters are for d esign guidan ce onl y and
are not t ested.
2: These parameters are characterized but not tested in manufacturing.
3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that
the dsPIC30F device be driven with an external clock while in RC mode.
4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
5: Negative current is defined as current sourced by the pin.
dsPIC30F3014/4013
DS70138G-page 178 2010 Microchip Technology Inc.
FIGURE 23-1: LOW-VOLTAGE DETECT CHARACTERISTICS
TABLE 23-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85° C for Industri al
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1) Max Units Conditions
VOL Output Low Voltage(2)
DO10 I/O Ports — — 0.6 V IOL = 8.5 mA, VDD = 5V
——0.15VIOL = 2.0 mA, VDD = 3V
DO16 OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 5V
(RC or EC Oscillator mode) — — 0.72 V IOL = 2.0 mA, VDD = 3V
VOH Output High Voltage(2)
DO20 I/O Ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 5V
VDD – 0.2 — — V IOH = -2.0 mA, VDD = 3V
DO26 OSC2/CLKO VDD – 0.7 — — V IOH = -1.3 mA, VDD = 5V
(RC or EC Oscillator mode) VDD – 0.1 — — V IOH = -2.0 mA, VDD = 3V
Capacitive Loading Specs
on Output Pins(2)
DO50 COSC2 OSC2/SO SC2 Pin — — 15 pF In XTL, XT, HS and LP modes
when e xternal cloc k is used to
drive OSC1.
DO56 CIO All I/O Pins and OSC2 — — 50 pF RC or EC Oscillator mode
DO58 CBSCL, SDA — — 400 pF In I2C mode
Note 1: Data i n “Typ” colum n i s at 5V, 25°C unless ot he rwis e s t ate d. Pa ram ete rs are for desig n guidance on ly and
are not tested.
2: These parameters are characterized but not tested in manufacturing.
LV10
LVDIF
VDD
(LVDIF set by hardware)
2010 Microchip Technology Inc. DS70138G-page 179
dsPIC30F3014/4013
FIGURE 23-2: BROWN-OUT RESET CHARACTERISTICS
TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL
DC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ Max Units Conditions
LV10 VPLVD LVDL Voltage on VDD
Transition High-to-Low LVDL = 0000(2) ———V
LVDL = 0001(2) ———V
LVDL = 0010(2) ———V
LVDL = 0011(2) ———V
LVDL = 0100 2.50 — 2.65 V
LVDL = 0101 2.70 — 2.86 V
LVDL = 0110 2.80 — 2.97 V
LVDL = 0111 3.00 — 3.18 V
LVDL = 1000 3.30 — 3.50 V
LVDL = 1001 3.50 — 3.71 V
LVDL = 1010 3.60 — 3.82 V
LVDL = 1011 3.80 — 4.03 V
LVDL = 1100 4.00 — 4.24 V
LVDL = 1101 4.20 — 4.45 V
LVDL = 1110 4.50 — 4.77 V
LV15 VLVDIN External LVD Input Pin
Threshold Voltage LVDL = 1111 ———V
Note 1: These parameters are characterized but not tested in manufacturing.
2: These values not in usable operating range.
BO10
RESET (due to BOR)
VDD
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
Power-up Time-out
BO15
dsPIC30F3014/4013
DS70138G-page 180 2010 Microchip Technology Inc.
23.2 AC Characteri stics and Timing Parameters
The information contained in this section defines dsPIC30F AC characteristics and timing parameters.
TABLE 23-11: ELECTRICAL CHARACTERISTICS: BOR
DC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operati ng tem per ature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1) Max Units Conditions
BO10 VBOR BOR Voltage on VDD
T ransition
High-to-Low(2)
BORV = 11(3) — — — V Not in operating
range
BORV = 10 2.6 — 2.71 V
BORV = 01 4.1 — 4.4 V
BORV = 00 4.58 — 4.73 V
BO15 VBHYS —5—mV
Note 1: Data in “Typ” column is a t 5V, 2 5°C unles s othe rwise st ate d. Par ameters are for d esign guidan ce onl y and
are not t ested.
2: These parameters are characterized but not tested in manufacturing.
3: ‘11’ values not in usable operating range.
TABLE 23-12: DC CHARACTERISTICS: PROGRAM AND EEPROM
DC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Indu stri al
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1) Max Units Conditions
Data EEPROM Memory(2)
D120 EDByte Endurance 100K 1M — E/W -40C TA +85°C
D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/W ri te Cyc le Time 0. 8 2 2.6 ms RTSP
D123 TRETD Characteri sti c R eten tio n 40 100 — Year Provided no o ther speci fic ati ons
are violat ed
D124 IDEW IDD During Programming — 10 30 mA Row Erase
Program Flash Memory(2)
D130 EPCell Endurance 10K 100K — E/W -40C TA +85°C
D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating
voltage
D132 VEB VDD for Bulk Erase 4.5 — 5.5 V
D133 VPEW VDD for Erase/Write 3.0 — 5.5 V
D134 TPEW Erase/W ri te Cy c le Time 0.8 2 2.6 ms RTSP
D135 TRETD Characteri sti c R eten tio n 40 100 — Year Provided no o ther speci fic ati ons
are violat ed
D137 IPEW IDD During Programming — 10 30 mA Row Erase
D138 IEB IDD During Programming — 10 30 mA Bulk Erase
Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
2: These parameters are characterized but not tested in manufacturing.
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FIGURE 23-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
FIGURE 23-4: EXTERNAL CLOCK TIMING
TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise st ated)
Operati ng tem pera ture -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operati ng voltage VDD range as described in Table 23-1.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL= 464
CL= 50 pF for all pins except OSC2
5 pF for OSC2 output
Load Cond itio n 1 – for all pins except OSC2 Load Condition 2 – for OSC2
Legend:
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
OS20
OS25
OS30 OS30
OS40 OS41
OS31 OS31
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DS70138G-page 182 2010 Microchip Technology Inc.
TABLE 23-14: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ(1) Max Units Conditions
OS10 FOSC External CLKI Frequency
(ext ernal cloc ks allowed
only in EC mode)(2)
DC
4
4
4
—
—
—
—
40
10
10
7.5(3)
MHz
MHz
MHz
MHz
EC
EC with 4x PLL
EC with 8x PLL
EC with 16x PLL
Oscill ator Frequency(2) DC
0.4
4
4
4
4
10
10
10
10
12(4)
12(4)
12(4)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32.768
4
4
10
10
10
7.5(3)
25
20(4)
20(4)
15(3)
25
25
22.5(3)
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
RC
XTL
XT
XT with 4x PLL
XT with 8x PLL
XT with 16x PLL
HS
HS/2 with 4x PLL
HS/2 with 8x PLL
HS/2 with 16x PLL
HS/3 with 4x PLL
HS/3 with 8x PLL
HS/3 with 16x PLL
LP
OS20 TOSC TOSC = 1/FOSC — — — — Se e parameter OS10
for FOSC value
OS25 TCY Instr uction Cycle Time(2,5) 33 — DC ns See Table 23-16
OS30 TosL,
TosH External Clock in (OSC1)
High or Low Time(2) .45 x TOSC ——nsEC
OS31 TosR,
TosF External Clock in (OSC1)
Rise or Fall Time(2) ——20nsEC
OS40 TckR CLKO Ri se Time(2,6) — — — ns See parameter DO31
OS41 TckF CLKO Fall Time(2,6) — — — ns See parameter DO32
Note 1: Data i n “Typ” column i s at 5 V, 25 °C unles s othe rwise s tate d. Param eters are for d esign guida nce on ly and
are not t ested.
2: These parameters are characterized but not tested in manufacturing.
3: Limited by the PLL output frequency range.
4: Limited by the PLL input frequency range.
5: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
6: Measur eme nts are t ak en in EC or ER C mod es . The CL KO signal is mea sur ed on the OSC 2 p in. CL KO i s
low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
2010 Microchip Technology Inc. DS70138G-page 183
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TABLE 23-15: PLL JITTER
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Characteristic Min Typ(1) Max Units Conditions
OS61 x4 PLL — 0.251 0.413 % -40°C TA +85°C VDD = 3.0 to 3.6V
— 0.251 0.413 % -40°C TA +125°C VDD = 3.0 to 3.6V
— 0.256 0.47 % -40°C TA +85°C VDD = 4.5 to 5.5V
— 0.256 0.47 % -40°C TA +125°C VDD = 4.5 to 5.5V
x8 PLL — 0.355 0.584 % -40°C TA +85°C VDD = 3.0 to 3.6V
— 0.355 0.584 % -40°C TA +125°C VDD = 3.0 to 3.6V
— 0.362 0.664 % -40°C TA +85°C VDD = 4.5 to 5.5V
— 0.362 0.664 % -40°C TA +125°C VDD = 4.5 to 5.5V
x16 PLL — 0.67 0.92 % -40°C TA +85°C VDD = 3.0 to 3.6V
— 0.632 0.956 % -40°C TA +85°C VDD = 4.5 to 5.5V
— 0.632 0.956 % -40°C TA +125°C VDD = 4.5 to 5.5V
Note 1: These parameters are characterized but not tested in manufacturing.
TABLE 23-16: INTERNAL CLOCK TIMING EXAMPLES
Clock
Oscillator
Mode
FOSC
(MHz)(1) TCY (sec)(2) MIPS
w/o PLL(3) MIPS
w/PLL x4(3) MIPS
w/PLL x8(3) MIPS
w/PLL x16(3)
EC 0.200 20.0 0.05 — — —
41.01.04.08.016.0
10 0.4 2.5 10.0 20.0 —
25 0.16 6.25 — — —
XT 4 1.0 1.0 4.0 8.0 16.0
10 0.4 2.5 10.0 20.0 —
Note 1: Assumption: Oscillator Postscaler is divide by 1.
2: Ins truction Ex ecution C ycle Ti me: TCY = 1/MIPS.
3: Ins truction Execution Frequen cy: MIPS = (FOSC * PLLx)/4 [si nce th ere a re 4 Q cl ocks per instruction
cycle].
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DS70138G-page 184 2010 Microchip Technology Inc.
TABLE 23-17: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Characteristic Min Typ Max Units Conditions
Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1)
OS63 FRC — — ±2.00 % -40°C TA +85°C VDD = 3.0-5.5V
— — ±5.00 % -40°C TA +125°C VDD = 3.0-5.5V
Note 1: Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN bits (OSCCON<3:0>) can be used to
compensate for temperature drift.
TABLE 23-18: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Characteristic Min Typ Max Units Conditions
LPRC @ Freq. = 512 kHz(1)
OS65A -50 — +50 % VDD = 5.0V, ±10%
OS65B -60 — +60 % VDD = 3.3V, ±10%
OS65C -70 — +70 % VDD = 2.5V
Note 1: Change of LPRC frequency as VDD changes.
2010 Microchip Technology Inc. DS70138G-page 185
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FIGURE 23-5: CLKO AND I/O TIMING CHARACTERISTICS
TABLE 23-19: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operati ng tem pera ture -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1,2,3) Min Typ(4) Max Units Conditions
DO31 TIOR Port Output Rise Time — 7 20 ns
DO32 TIOF Port Output Fall Time — 7 20 ns
DI35 TINP INTx Pin High or Low Time (output) 20 — — ns
DI40 TRBP CNx High or Low Time (input) 2 TCY ——ns
Note 1: These parameters are asynchronous events not related to any internal clock edges
2: Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC.
3: These parameters are characterized but not tested in manufacturing.
4: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
Note: Refer to Figure 23-3 for load co nditions.
I/O Pin
(Input)
I/O Pin
(Output)
DI35
Old Value New Value
DI40
DO31
DO32
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FIGURE 23-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER T IMING CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY11
SY10
SY20
SY13
I/O Pins
SY13
Note: Refer to Figure 23-3 for load conditions.
FSCM
Delay
SY35
SY30
SY12
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FIGURE 23-7: BAND GAP START-UP TIME CHARACTERISTICS
TABLE 23-20: RESET, WATCHDOG T I MER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operati ng tem per ature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions
SY10 TmcL MCLR Pulse Width (l ow) 2 — — s -40°C to +85°C
SY11 TPWRT Power-up Timer Period 2
10
43
4
16
64
8
32
128
ms -40°C to +85°C,
VDD = 5V
User programmable
SY12 TPOR Power-on Reset Delay 3 10 30 s -40°C to +85°C
SY13 TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset —0.81.0s
SY20 TWDT1
TWDT2
TWDT3
W atch dog T i mer Time-ou t Period
(no prescaler) 1.1
1.2
1.3
2.0
2.0
2.0
6.6
5.0
4.0
ms
ms
ms
VDD = 2.5V
VDD = 3.3V, ±10%
VDD = 5V, ±10%
SY25 TBOR Brown-out Reset Pulse Width(3) 100 — — sVDD VBOR (D034)
SY30 TOST Oscillator Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period
SY35 TFSCM Fa il- Safe C loc k Mo nito r Del ay — 500 900 s -40°C to +85°C
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
3: Refer to Figure 23-2 and Table 23-11 for BOR.
TABLE 23-21: BAND GAP START-UP TIME REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperat ure -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions
SY40 TBGAP Ba nd Ga p St art-up Time — 40 65 s Defined as the time between the
instant that the band gap is enabled
and the moment that the band gap
reference voltage is stable
(RCON<13> status bit)
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.
VBGAP
Enable Band Gap(1)
Band Gap
0V
Stable
Note 1: Note: Set LVDEN bit (RCON<12>) or FBORPOR<7>set.
SY40
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FIGURE 23-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS
TABLE 23-22: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operati ng tem pe rature -40 °C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
TA10 TTXH TxCK High Time Synchronous,
no prescaler 0.5 TCY + 20 — — ns Must also meet
parameter TA15
Synchronous,
with prescaler 10 — — ns
Asynchronous 10 — — ns
TA11 TTXL TxCK Low Time Synchronous,
no prescaler 0.5 TCY + 20 — — ns Must also meet
parameter TA15
Synchronous,
with prescaler 10 — — ns
Asynchronous 10 — — ns
TA15 TTXP TxCK Input Period Synchronous,
no prescaler TCY + 10 — — ns
Synchronous,
with prescaler Greater of:
20 ns or
(TCY + 40)/N
———N = prescale
value
(1, 8, 64, 256)
Asynchronous 20 — — ns
OS60 Ft1 SOSC1/T1CK Oscillator Input
Frequency Range (oscillator
enabled by set ting bit, TCS
(T1CON<1>)
DC — 50 kHz
TA20 TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment 0.5 TCY —1.5 TCY —
Note 1: Timer1 is a Type A.
Note: Refer to Figure 23-3 for load conditions.
Tx11
Tx15
Tx10
Tx20
TMRX OS60
TxCK
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T ABLE 23-23: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operati ng tem pe rature -40 °C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
TB10 TtxH TxCK High T im e Synchronous,
no prescaler 0.5 TCY + 20 — — ns Must also meet
parameter TB15
Synchronous,
with prescaler 10 — — ns
TB11 TtxL TxCK Low Ti me Synchro nou s,
no prescaler 0.5 TCY + 20 — — ns Must also meet
parameter TB15
Synchronous,
with prescaler 10 — — ns
TB15 TtxP TxCK Input Period Synchro nous,
no prescaler TCY + 10 — — ns N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler Greater of:
20 ns or
(TCY + 40)/N
TB20 TCKEXTMRL Delay from External TxCK Cl ock
Edge to Timer Increment 0.5 TCY — 1.5 TCY —
Note 1: Timer2 and Timer4 are Type B.
T ABLE 23-24: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet
parameter TC15
TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet
parameter TC15
TC15 TtxP TxCK Input Period Synchronous,
no prescaler TCY + 10 — — n s N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler Greater of:
20 ns or
(TCY + 40)/N
TC20 TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment 0.5 TCY —1.5
TCY —
Note 1: Timer3 and Timer5 are Type C.
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DS70138G-page 190 2010 Microchip Technology Inc.
FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
FIGURE 23-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
TABLE 23-25: INPUT CAPTURE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Indu strial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Max Units Conditions
IC10 TccL ICx Input Low Time No prescaler 0 .5 TCY + 20 — ns
With prescaler 10 — ns
IC11 TccH ICx Input High Time No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
IC15 TccP ICx Input Period (2 TCY + 40)/N — ns N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.
TABLE 23-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwis e stated)
Ope rati ng temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions
OC10 TccF OCx Output F all Time — — — ns See Parameter DO32
OC11 TccR OCx Outp ut Rise Time — — — ns See Par ameter DO31
Note 1: These parameters are characterized but not tested in manufacturing.
2: Dat a in “Typ” colum n is a t 5V, 25° C unl ess o therw ise s tate d. Param eters a re for de sign guidan ce only and
are not t ested.
ICX
IC10 IC11
IC15
Note: Refer to Figure 23-3 for load conditions.
OCx
OC11 OC10
(Output Compare
Note: Refer to Figure 23-3 for load conditions.
or PWM Mode)
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FIGURE 23-11: OCx/PWM MODULE TIMING CHARACTERISTICS
TABLE 23-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwis e stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions
OC15 TFD Fault Input to PWM I/O
Change ——50ns
OC20 TFLT Fault Input Pulse Width 50 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Dat a in “Typ” column is a t 5V, 2 5°C un less othe rwis e st ated. Par ameters are for d esign guidan ce onl y and
are not t ested.
OCFA/OCFB
OCx
OC20
OC15
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DS70138G-page 192 2010 Microchip Technology Inc.
FIGURE 23-12: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING CHARACTERISTICS
COFS
CSCK
(SCKE =
0
)
CSCK
(SCKE =
1
)
CSDO
CSDI
CS11 CS10
CS40 CS41
CS21
CS20
CS35
CS21
MSb LSb
MSb IN LSb IN
CS31
HIGH-Z HIGH-Z
70
CS30
CS51 CS50
CS55
Note: Refer to Figure 23-3 for load conditions.
CS20
CS56
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TABLE 23-28: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unles s oth erwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions
CS10 TcSCKL CSCK Input Low Time
(CSCK pin is an input) TCY/2 + 20 — — ns
CSCK Output Low Time
(CSCK pin is an output)(3) 30 — — ns
CS11 TcSCKH CSCK Input High Time
(CSCK pin is an input) TCY/2 + 20 — — ns
CSCK Output High Time
(CSCK pin is an output)(3) 30 — — ns
CS20 TcSCKF CSCK Output Fall Time
(CSCK pin is an output)(4) —1025ns
CS21 TcSCKR CSCK Ou tput Rise Time
(CSCK pin is an output)(4) —1025ns
CS30 TcSDOF CSDO Data Output Fall Time(4) —1025ns
CS31 TcSDOR CSDO Data Output Rise Time(4) —1025ns
CS35 TDV Clock Edge to CSDO Data Valid — — 10 ns
CS36 TDIV Clock Edge to CSDO Tri-Stated 10 — 20 ns
CS40 TCSDI Setup Time of CSDI Data Input
to CSCK Edge (CSCK pin is
input or output)
20 — — ns
CS41 THCSDI Hold Time of CSDI Data Input to
CSCK Edge (CSCK pin is input
or output)
20 — — ns
CS50 TcoFSF COFS Fall Time
(COFS pin is output) —1025nsNote 1
CS51 TcoFSR COFS Rise Time
(COFS pin is output) —1025nsNote 1
CS55 TscoFS Setup Time of COFS Data Input
to CSCK edge (COFS pin is
input)
20 — — ns
CS56 THCOFS Hold Time of COFS Data In put to
CSCK Edge (COFS pin is input) 20 — — ns
CS57 TPCSCK CSCK Clock Period 100 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Dat a in “Typ” colu mn is at 5V, 25°C unless otherw ise st ated. Pa ramete rs are f or d esign gu ida nce only and
are not t ested.
3: The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all DCI pins.
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FIGURE 23-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS
SYNC
BIT_CLK
SDOx
SDIx
CS61 CS60
CS65 CS66
CS80
CS21
MSb In
CS75
LSb
CS76
(COFS)
(CSCK)
LSb
MSb
CS72
CS71 CS70
CS76 CS75
(CSDO)
(CSDI)
CS62 CS20
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FIGURE 23-14 : SPI MOD UL E MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
TABLE 23-29: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1,2) Min Typ(3) Max Units Conditions
CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns
CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns
CS62 TBCLK BIT_CLK Period — 81.4 — ns Bit clock is input
CS65 TSACL Input Setup Time to
Fal ling Edge of BIT_CLK ——10ns
CS66 THACL Input Hold Time from
Fal ling Edge of BIT_CLK ——10ns
CS70 TSYNCLO SYNC Data Output Low Time — 19.5 — sNote 1
CS71 TSYNCHI SYNC Data Output High Time — 1.3 — sNote 1
CS72 TSYNC SYNC Data Output Period — 20.8 — sNote 1
CS75 TRACL Rise Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V
CS76 TFACL Fall Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V
CS80 TOVDACL Output Valid Delay from Rising
Edge of BIT_CLK ——15ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: These values assume BIT_CLK frequency is 12.288 MHz.
3: Dat a in “T yp” c olumn is at 5V, 25°C unles s otherwise s tated. Para meters are for de sign guid ance only an d
are not t ested.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP11 SP10
SP40 SP41
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
MSb In LSb In
Bit 14 - - - -1
SP30
SP31
Note: Refer to Figure 23-3 for load conditions.
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FIGURE 23-15 : SPI MOD UL E MASTER MODE (CKE =1) TIMING CHARACTERISTICS
TABLE 23-30: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operati ng tem per ature -40 °C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions
SP10 TscL SCKX Output Low Time(3) TCY/2 — — ns
SP11 TscH SCKX Output High Time(3) TCY/2 — — ns
SP20 TscF SCKX Output Fall Time(4 — — — ns See parameter
DO32
SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter
DO31
SP30 TdoF SDOX Data Output Fall Time(4) — — — ns See parameter
DO32
SP31 TdoR SDOX Data O utput Rise Time(4) — — — ns See parameter
DO31
SP35 TscH2doV,
TscL2doV SDOX Data Output Valid after
SCKX Edge — — 30 ns
SP40 TdiV2scH,
TdiV2scL Setup Time of SDIX Data Input
to SCKX Edge 20 — — ns
SP41 TscH2diL,
TscL2diL Hold Time of SDIX Data Input
to SCKX Edge 20 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Dat a in “Typ” column is a t 5V, 2 5°C un less othe rwis e st ated. Par ameters are for d esign guidan ce onl y and
are not t ested.
3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SDOX
SDIX
SP36
SP30,SP31
SP35
MSb
MSb In
Bit 14 - - - - - -1
LSb In
Bit 14 - - - -1
LSb
Note: Refer to Figure 23-3 for load conditions.
SP11 SP10 SP20
SP21
SP21
SP20
SP40
SP41
2010 Microchip Technology Inc. DS70138G-page 197
dsPIC30F3014/4013
FIGURE 23-16: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
TABLE 23-31: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unles s oth erwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions
SP10 TscL SCKX Output Low Time(3) TCY/2 — — ns
SP11 TscH SCKX Output High Time(3) TCY/2 — — ns
SP20 TscF SCKX Output Fall Time(4) — — — ns See parameter
DO32
SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter
DO31
SP30 TdoF SDOX Data Output Fall
Time(4) — — — ns See parameter
DO32
SP31 TdoR SDOX Data Output Rise
Time(4) — — — ns See parameter
DO31
SP35 TscH2do,
TscL2doV SDOX Data Output Valid after
SCKX Edge — — 30 ns
SP36 TdoV2sc,
TdoV2scL SDOX Data Output Setup to
First SCKX Edge 30 — — ns
SP40 TdiV2scH,
TdiV2scL Setup Time of SDIX Data
Input to SCKX Edge 20 — — ns
SP41 TscH2diL,
TscL2diL Hold Time of SDIX Data Input
to SCKX Edge 20 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Dat a in “Typ” column is a t 5V, 2 5°C un less othe rwis e st ated. Par ameters are for d esign guidan ce onl y and
are not t ested.
3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI pins.
SS
X
SCK
X
(CKP =
0
)
SCK
X
(CKP =
1
)
SDO
X
SDI
SP50
SP40 SP41
SP30,SP31 SP51
SP35
SDI
X
MSb LSb
Bit 14 - - - - - -1
MSb In Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP71 SP70
Note: Refer to Figure 23-3 for load conditions.
dsPIC30F3014/4013
DS70138G-page 198 2010 Microchip Technology Inc.
TABLE 23-32: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Indu stri al
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions
SP70 TscL SCKX Input Low Time 30 — — ns
SP71 TscH SCKX Input High Time 30 — — ns
SP72 TscF SCKX Input Fall Time(3) — — 25 ns
SP73 TscR SCKX Input Rise Time(3) — — 25 ns
SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter
DO32
SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter
DO31
SP35 TscH2do,
TscL2doV SDOX Data Output Valid after
SCKX Edge — — 30 ns
SP40 TdiV2scH,
TdiV2scL Setup Time of SDIX Data Input
to SCKX Edge 20 — — ns
SP41 TscH2diL,
TscL2diL Hold Time of SDIX Data Input
to SCKX Edge 20 — — ns
SP50 TssL2scH,
TssL2scL SSX to SCKX or SCKX Input 120 — — ns
SP51 TssH2doZ SSX to SDO X Output
High-impedance(3) 10 — 50 ns
SP52 TscH2ssH
TscL2ssH SSX afte r SCKx Edge 1.5 TCY + 40 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Dat a in “T yp” colum n is at 5V, 25°C unless oth erwise sta ted. Parameter s are for design gui dance only and
are not t ested.
3: Assumes 50 pF load on all SPI pins.
2010 Microchip Technology Inc. DS70138G-page 199
dsPIC30F3014/4013
FIGURE 23-17: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SSX
SCKX
(CKP = 0)
SCKX
(CKP = 1)
SDOX
SDI
SP50
SP60
SDIX
SP30,SP31
MSb Bi t 14 - - - - - -1 LSb
SP51
MSb In Bit 14 - - - -1 LSb In
SP35
SP52
SP52
SP73
SP72
SP72
SP73
SP71 SP70
SP40 SP41
Note: Refer to Figure 23-3 for load conditions.
dsPIC30F3014/4013
DS70138G-page 200 2010 Microchip Technology Inc.
TABLE 23-33: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions
SP70 TscL SCKX Input Low Time 30 — — ns
SP71 TscH SCKX Input High Time 30 — — ns
SP72 TscF SCKX Input Fall Time(3) — — 25 ns
SP73 TscR SCKX Input Rise Time(3) — — 25 ns
SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter
DO32
SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter
DO31
SP35 TscH2do,
TscL2doV SDOX Data Output Valid after
SCKX Edge — — 30 ns
SP40 TdiV2scH,
TdiV2scL Setup Time of SDIX Data Input
to SCKX Edge 20 — — ns
SP41 TscH2diL,
TscL2diL Hold Time of SDIX Data Input
to SCKX Edge 20 — — ns
SP50 TssL2scH,
TssL2scL SSX to SCKX or SCKX Input 120 — — ns
SP51 TssH2doZ SSx to SDOX Output
High-Impedance(4) 10 — 50 ns
SP52 TscH2ssH
TscL2ssH SSX after SCKX Edge 1.5 TCY + 40 — — ns
SP60 TssL2doV SDOX Data Output Valid after
SCKX Edge — — 50 ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data i n “Typ” column i s at 5V, 25°C unless o the rwis e s tated. Param ete rs ar e for design gu ida nc e on ly and
are not tested.
3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specificat ion.
4: Assumes 50 pF load on all SPI pins.
2010 Microchip Technology Inc. DS70138G-page 201
dsPIC30F3014/4013
FIGURE 23-18 : I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
FIGURE 23-19 : I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
TABLE 23-34: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min(1) Max Units Conditions
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2) TCY/2 (BRG + 1) — s
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2) TCY/2 (BRG + 1) — s
IM20 TF:SCL SDA and SCL
Fall Time 100 kHz mode — 300 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(2) — 100 ns
Note 1: BRG is the value of the I2C Baud Rat e Genera tor. Refer to Secti on 21. “Inter-Integr ated Circuit™ (I 2C)”
in the “dsPIC30F Fa mily Reference Manual” (DS70046).
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
IM31 IM34
SCL
SDA
Start
Condition Stop
Condition
IM30 IM33
Note: Refer to Figure 23-3 for load conditions.
IM11 IM10 IM33
IM11 IM10
IM20
IM26 IM25
IM40 IM40 IM45
IM21
SCL
SDA
In
SDA
Out
Note: R e fe r to Figure 23-3 for load conditions.
dsPIC30F3014/4013
DS70138G-page 202 2010 Microchip Technology Inc.
IM21 TR:SCL SDA and SCL
Rise Time 100 kHz mode — 1000 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(2) — 300 ns
IM25 TSU:DAT Data Input
Setup Time 100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode(2) — — ns
IM26 THD:DAT Data Input
Hold Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
1 MHz mode(2) — — ns
IM30 TSU:STA Start Condition
Setup Time 100 kHz mode TCY/2 (BRG + 1) — s Only releva nt for
Repeated Start
condition
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2) TCY/2 (BRG + 1) — s
IM31 THD:STA Start Condition
Hold Time 100 kHz mode TCY/2 (BRG + 1) — s After this period, the
first clock pulse is
generated
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2) TCY/2 (BRG + 1) — s
IM33 TSU:STO Stop Con dition
Setup Time 100 kHz mode TCY/2 (BRG + 1) — s
400 kHz mode TCY/2 (BRG + 1) — s
1 MHz mode(2) TCY/2 (BRG + 1) — s
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns
Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns
1 MHz mode(2) TCY/2 (BRG + 1) — ns
IM40 TAA:SCL Output Valid
From Clock 100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode(2) ——ns
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Tim e the bus mus t be
free before a new
transmission can start
400 kHz mode 1.3 — s
1 MHz mode(2) ——s
IM50 CBBus Capacitive Loading — 400 pF
TABLE 23-34: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min(1) Max Units Conditions
Note 1: BRG is the value of the I2C Baud Rat e Genera tor. Refer to Secti on 21. “Inter-Integr ated Circuit™ (I 2C)”
in the “dsPIC30F Fa mily Reference Manual” (DS70046).
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
2010 Microchip Technology Inc. DS70138G-page 203
dsPIC30F3014/4013
FIGURE 23-20 : I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
FIGURE 23-21 : I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS31 IS34
SCL
SDA
Start
Condition Stop
Condition
IS30 IS33
IS30 IS31 IS33
IS11
IS10
IS20
IS26 IS25
IS40 IS40 IS45
IS21
SCL
SDA
In
SDA
Out
dsPIC30F3014/4013
DS70138G-page 204 2010 Microchip Technology Inc.
TABLE 23-35: I2C™ BUS DATA TI MING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Max Units Conditions
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz.
1 MHz mode(1) 0.5 — s
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
1 MHz mode(1) 0.5 — s
IS20 TF:SCL SDA and SCL
Fall Time 100 kHz mode — 300 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1) — 100 ns
IS21 TR:SCL SDA and SCL
Rise Time 100 kHz mode — 1000 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1) — 300 ns
IS25 TSU:DAT Data Input
Setup Time 100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode(1) 100 — ns
IS26 THD:DAT Data Input
Hold Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
1 MHz mode(1) 00.3s
IS30 TSU:STA Start Cond iti on
Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated
Start condition
400 kHz mode 0.6 — s
1 MHz mode(1) 0.25 — s
IS31 THD:STA Start Conditi on
Hold Time 100 kHz mode 4.0 — s After this period, the first
clock pulse is generated
400 kHz mode 0.6 — s
1 MHz mode(1) 0.25 — s
IS33 TSU:STO Stop Condition
Setup Time 100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
1 MHz mode(1) 0.6 — s
IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 — ns
1 MHz mode(1) 250 ns
IS40 TAA:SCL Output V alid From
Clock 100 kHz mode 0 3500 ns
400 kHz mode 0 1000 ns
1 MHz mode(1) 0 350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — s
1 MHz mode(1) 0.5 — s
IS50 CBBus Capacitive
Loading — 400pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
2010 Microchip Technology Inc. DS70138G-page 205
dsPIC30F3014/4013
FIGURE 23-22: CAN MODULE I/O TIMING CHARACTERISTICS
TABLE 23-36: CAN MODULE I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions
CA10 TioF Port Outpu t Fall Time — 10 25 ns
CA11 TioR Port Output Rise Time — 10 25 ns
CA20 Tcwf Pulse Width to Trigger
CAN W ake-up Filter 500 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Dat a in “Typ” column is a t 5V, 2 5°C un less othe rwis e st ated. Par ameters are for d esign guidan ce onl y and
are not t ested.
CXTX Pin
(output)
CA10 CA11
Old Value New Value
CA20
CXRX Pin
(input)
dsPIC30F3014/4013
DS70138G-page 206 2010 Microchip Technology Inc.
TABLE 23-37: 12-BIT A/D MODULE SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
Device Supply
AD01 AVDD Module VDD Supply Greater of
VDD – 0.3
or 2.7
— Lesser of
VDD + 0.3
or 5.5
V
AD02 AVSS Module VSS Supply VSS - 0.3 — VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High AVSS + 2.7 — AVDD V
AD06 VREFL Reference Voltage Low AVSS —AVDD – 2.7 V
AD07 VREF Absolute Reference
Voltage AVSS – 0.3 — AVDD + 0.3 V
AD08 IREF Current Drain — 200
.001 300
2A
AA/D operating
A/D off
Analog Input
AD10 VINH-VINL Full-Scale Input Span VREFL —VREFH VNote 1
AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V
AD12 — Leakage Current — ±0.001 ±0.610 AVINL = AVSS = VREFL = 0V,
AVDD = V REFH = 5V
Source Im pe dan c e = 2.5 k
AD13 — Leakage Current — ±0.001 ±0.610 AV
INL = AVSS = VREFL = 0V,
AVDD = V REFH = 3V
Source Im pedan ce =
2.5 k
AD15 RSS Switch Resistance — 3.2 K —
AD16 CSAMPLE Sample Capacitor — 18 pF
AD17 RIN Recomm ended Impe dance
of Analog Voltage Source — — 2.5K
DC Accuracy
AD20 Nr Resolution 12 data bits bits
AD21 INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V,
AVDD = V REFH = 5V
AD21A INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V,
AVDD = V REFH = 3V
AD22 DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V,
AVDD = V REFH = 5V
AD22A DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V,
AVDD = V REFH = 3V
AD23 GERR Gain Error +1.25 +1.5 +3 LSb V INL = AVSS = VREFL = 0V,
AVDD = V REFH = 5V
AD23A GERR Gain Error +1.25 +1.5 +3 LSb V INL = AVSS = VREFL = 0V,
AVDD = V REFH = 3V
Note 1: The A/D convers io n resul t neve r decre as es with an inc r ea se in the inp ut vol t ag e, and has no miss in g
codes.
2010 Microchip Technology Inc. DS70138G-page 207
dsPIC30F3014/4013
AD24 EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD24A EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD25 — Monotonicity(1) — — — — Guaranteed
Dynamic Performance
AD30 THD Tot al Harm oni c Di sto rtio n — -71 — dB
AD31 SINAD Signal to Noise and
Distortion —68—dB
AD32 SFDR Spurious Free Dynamic
Range —83—dB
AD33 FNYQ Input Signal Bandwidth — — 100 kHz
AD34 ENOB Effective Number of Bits 10.95 11.1 — bits
TABLE 23-37: 12-BIT A/D MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
Note 1: The A/D convers io n resul t neve r decre as es with an inc r ea se in the inp ut vol t ag e, and has no miss in g
codes.
dsPIC30F3014/4013
DS70138G-page 208 2010 Microchip Technology Inc.
FIGURE 23-23: 12-BIT A/D CONVERSION TIMING CHARACTERISTICS
(ASAM = 0, SSRC = 000)
AD55
TSAMP
Clear SAMPSet SAMP
AD61
ADCLK
Instruction
SAMP
ch0_dischrg
ch0_samp
AD60
DONE
ADIF
ADRES(0)
1 2 3 4 5 6 87
1- Software sets ADCON. SAMP to start sampling.
2- Sampling starts after discharge period.
3- Software clears ADCON. SAMP to start conversion.
4- Sampling ends, conversion sequence starts.
5- Convert bit 11.
9- One TAD for end of conversion.
AD50
eoc
9
6- Convert bit 10.
7- Convert bit 1.
8- Convert bit 0.
Execution
TSAMP is described in Section 18. “12-bit A/D Converter” of the dsPIC30F Family Reference Manual (DS70046).
2010 Microchip Technology Inc. DS70138G-page 209
dsPIC30F3014/4013
TABLE 23-38: 12-BIT A/D CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.7V to 5.5V
(unless otherwise stated)
Operati ng tem pe rature -40 °C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
Clock Parameters
AD50 TAD A/D Clock Period 334 — — ns VDD = 3-5.5V (Note 1)
AD51 tRC A/D Interna l RC Oscillat or Period 1.2 1 .5 1.8 s
Conversion Rate
AD55 tCONV Conversion Time — 14 TAD ns
AD56 FCNV Throughput Rate — 200 — ksps VDD = VREF = 5V
AD57 TSAMP Sampling Time 1 TAD ——nsVDD = 3-5.5V source
resistance
RS = 0-2.5 k
Timing Parameters
AD60 tPCS Conversion Start from Sample
Trigger —1 TAD —ns
AD61 tPSS Samp le St a rt from Setti ng
Sample (SAMP) Bit 0.5 TAD —1.5
TAD ns
AD62 tCSS Conversion Completion to
Sample Start (ASAM = 1)—0.5 TAD —ns
AD63 tDPU(2) Time to Stabilize Analog Stage
from A/D Off to A/D On ——20s
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: tDPU is the time required for the ADC module to stabilize when it is turned on (ADCON1<ADON> = 1).
During this time the ADC result is indeterminate.
dsPIC30F3014/4013
DS70138G-page 210 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 211
dsPIC30F3014/4013
24.0 PACKAGING INFORMATION
24.1 Package Marking Information
Example
dsPIC30F4013
0810017
40-Lead PDIP
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
XXXXXXXXXX
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC
Example
0810017
0810017
dsPIC
30F4013
-301/PT
-30I/ML
30F4013
-30I/P
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanume ric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
3
e
3
e
dsPIC30F3014/4013
DS70138G-page 212 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS70138G-page 213
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2010 Microchip Technology Inc. DS70138G-page 217
dsPIC30F3014/4013
APPENDIX A: REVISION HISTORY
Revision D (June 2006)
Previous versions of this data sheet contained
Advance or Preliminary Information. They were
distributed with incomplete characterization data.
This revision reflects these changes:
• Revised I2C Slave Addresses
(see Table 14-1)
• Updated example for ADC Conversion Clock
selection (see Section 19.0 “12-bit Analog-to-
Digital Converter (ADC) Module”)
• Base instruction CP1 eliminated from instruction
set (seeTable 21-2)
• Revised electrical characteristics:
- Operating Current (IDD) Specifications
(see Table 23-5)
- Idle Current (IIDLE) Specifications
(see Table 23-6)
- Power-down Current (IPD) Specifications
(see Table 23-7)
- I/O pin Input Specific ations
(see Table 23-8)
- Brown Out Reset (BOR) Specifications
(see Table 23-11)
- Watchdo g Timer time-out li mits
(see Table 23-20)
Revision E (January 2007)
This revision includes updates to the packaging
diagrams.
Revision F (April 2008)
This revision reflects these updates:
• Added FUSE Configuration Register (FICD)
deta ils (see Section 20.8 “Device Configuration
Registers” and Table 20-8)
• Added Note 2 in Device Configuration Registers
table (Table 20-8)
• Removed erroneous statement regarding genera-
tion of CAN receive errors (see Section 17.4.5
“Receive Errors”)
• Updated ADC Conversion Clock and Sampling
Rate Calculation (se e Example 19-1). Minimum
TAD is 334 nsec.
• Updated details related to the Input Change
Notification module:
- Updated last sentence in the first paragraph
of Section 7.3 “Input Change Notification
Module”
- Updated Table 7-2
- Removed Table 7-3, Table 7-4, and Table 7-5
• Electrical S pecifications:
- Resolved TBD values for parameters DO10,
DO16, DO20, and DO26 (see Table 23-9)
- 10-bit High-Speed ADC tPDU timing parame-
ter (time to stabilize) has been updated from
20 µs typical to 20 µs maximum (see
Table 23-38)
- Parameter OS65 (Internal RC Accuracy) has
been expanded to reflect multiple Min and
Max v alues for different temperatures (see
Table 23-18)
- Parameter DC12 (RAM Data Retention Volt-
age) has been update d to inclu de a Min valu e
(see Table 23-4)
- Parameter D134 (Erase/Write Cycle Time)
has been updated to include Min and Max
values and the Typ value has been removed
(see Table 23-12)
- Removed parameters OS62 (Internal FRC
Jitter) and OS64 (Internal FRC Drift) and
Note 2 from AC Characteristics (see
Table 23-17)
- Parameter OS63 (Internal FRC Accuracy)
has been expanded to reflect multiple Min
and Max values for different temperatures
(see Table 23-17)
- Removed parameters DC27a, DC27b,
DC4 7a, and DC47b (references to IDD,
20 MIPs @ 3.3V) in Table 23-5 and
Table 23-6
- Removed parameters CS77 and CS78
(reference s to T RACL and TFACL @ 3.3V) in
Table 23-29
- Updated Mi n and Ma x valu es and C ondit ion s
for parameter SY11 and updated Min, Typ,
and Max values and Conditions for
parameter SY20 (see Table 23-20)
• Additional mino r corrections throughout the
document
dsPIC30F3014/4013
DS70138G-page 218 2010 Microchip Technology Inc.
Revision G (November 2010)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in Table A-1.
TABLE A-1: MAJOR SECTION UPDATES
Section Name Update Descripti on
“High-Performance, 16-Bit Digital
Signal Controll er s”Added Note 1 to all QFN pin diagrams (see “Pin Diagrams”).
Section 1.0 “Device Overview” Removed th e “DCI” pe ripheral bl ock fr om the dsPIC 30F3014 Block Diag ram
(see Figure 1-1).
Updated the Pinout I/O Descriptions for AVDD and AVSS (see Table 1-1).
Section 20.0 “System Integration” Added a note on OSCTUN functionality in Section 20.2.5 “Fast RC
Oscillator (FRC)”.
Updated the ope rati ng freq uen ci es for the f oll owin g Os cil la tor Ope rati ng
Modes (see Table 20-1):
•XTL
•XT w/PLL 16x
• HS/2 w/PLL 4x, 8x, and 16x
• HS/3 w/PLL 4x, 8x, and 16x
• EC w/PLL 4x, 8x, and 16x
Section 23.0 “Electrical
Characteristics” Updated the max imum va lue for p arame ter DI19 and the min imum val ue for
parameter DI29 in the I/O Pin Input Specifications (see Table 23-8).
Removed parameter D136 and updated the minimum, typical, maximum,
and conditions for parameters D122 and D134 in the Program and
EEPROM specifications (see Table 23-12).
2010 Microchip Technology Inc. DS70138G-page 219
dsPIC30F3014/4013
INDEX
Numerics
12-Bit Analog-to-Digital Converter (A/D) Module..............131
A
A/D....................................................................................131
Aborti n g a Conversion ................... ..................... ......133
ADCHS Register.......................................................131
ADCON1 Register.....................................................131
ADCON2 Register.....................................................131
ADCON3 Register.....................................................131
ADCSSL Register.....................................................131
ADPCFG Register.....................................................131
Configuring Analog Port Pins..............................54, 138
Connection Considerations................................... .. ..138
Conversi o n Op e ration..... ............... .............. .............132
Effects of a Reset......................................................137
Operation During CPU Idle Mode.............................137
Operation During CPU Sleep Mode..........................137
Outpu t Fo r mats......... ........................... .....................137
Power-Down Modes ..................................................137
Programming the Sample Trigger............................. 133
Register Map..................... ..................... ...................139
Result Buffer............... ..................... ..................... ....132
Sampling Requirements........................... .. ....... .... .. ..136
Selecting the Conversion Sequence.........................132
AC Characteristics ............................................................180
Load Conditions............................. .... .. .. .. .... ..... .... .. ..181
AC Temperature and Voltage Specifications....................181
AC-Link Mode Operation ........ .... .. .. ....... .... .. .. .... .. ....... .... ..128
16-Bit Mode...... ............................ ........................... ..128
20-Bit Mode...... ............................ ........................... ..129
ADCSele c t i n g th e C o n ve rsion C l o ck.......... .. ...... ..... ...... .. .13 3
ADC Conversion Speeds..................................................134
Address Generator Units ....................................................37
Alternate Vector Table........................................................64
Analog-to-Digital Converter. See A/D.
Assembler
MPASM Assembler...................................................168
Automatic Clock Stretch......................................................94
During 10-Bit Addressing (STREN = 1) ......................94
During 7-Bit Addressing (STREN = 1)........................94
Receive Mode.............................................................94
Transmit Mode...... ..................... ........................... ......94
B
Band Gap Start-up Time
Requirements............................................................187
Barrel Shifter.......................................................................23
Bit-Reversed Addr e ssing .............. ..................... .................40
Example......................................................................40
Implementation ...........................................................40
Modifier Values Tab l e........... ..................... .................41
Sequence Table (16-Entry)....................................... ..41
Block Diagrams
12-Bit A/D Functi o n al................................. ...............131
16-Bit Timer1 Module................................................ ..67
16-Bit Timer2 ..... ............................ ........................... ..73
16-Bit Timer3 ..... ............................ ........................... ..73
16-Bit Timer4 ..... ............................ ........................... ..78
16-Bit Timer5 ..... ............................ ........................... ..78
32-Bit Timer2/3 ................... ............................ ............72
32-Bit Timer4/5 ................... ............................ ............77
CAN Buffers and Protocol Engine............................ 112
DCI Module.......................... .. .. .. .. .. .. .. .. ....... .. .. .. .. .. .. .. 122
Dedica te d Po rt Struct u re ......... ................................. .. 53
DSP Engin e........ ..................... ........................... ........ 20
dsPIC30F3014............................................................ 11
dsPIC30F4013............................................................ 12
External Power-on Reset Circuit .............................. 153
I2C .............................................................................. 92
Input Capture Mode.................................................... 81
Oscillat or S ys tem.... ........ ......... ........ ......... .............. .. 143
Output Compare Mode............................................... 85
Reset System ........................................................... 151
Shared Po rt Structu re....................................... .......... 54
SPI............................................................................ 100
SPI Master/Slave Connection . .................................. 100
UAR T R e c e i ve r.... .. ...... ..... ...... .......... ..... ...... ...... ...... . 104
UAR T Tran smitte r............. ...... ...... ...... ..... ...... ...... ..... 1 0 3
BOR Characteristics......................................................... 180
BOR. See Brown-out Reset.
Brown-out Reset
Timing Requirements ............................................... 187
C
C Compilers
MPLAB C18.............................................................. 168
CAN Module .......................................... .... ......... .. .... .... .. .. 111
Baud Rate Setting .................................................... 116
CAN1 Register Map.................................................. 118
Frame Types ............................................................ 111
I/O Timing Requirements.......................................... 205
Message Reception.................................................. 114
Message Transmission............................................. 115
Modes of Operation.................................................. 113
Overview................................................................... 111
CLKOUT and I/O Timing
Requirements........................................................... 185
Code Examples
Data EEPROM Block Erase ....................................... 50
Data EEPROM Block Write ........................................ 52
Data EEPROM Read.................................................. 49
Data EEPROM Word Erase ....................................... 50
Data EEPROM Word Write ........................................ 51
Erasing a Row of Program Memory ........................... 45
Initiating a Programming Sequence ................... .. .... .. 46
Loading Write Latches................. .. .. .. ....... .. .... .. .. .. .... .. 46
Port Write/Read.......................................................... 54
Code Protection................................................................ 141
Control Registers................................................................ 44
NVMADR.................................................................... 44
NVMADRU ................................................................. 44
NVMCON.................................................................... 44
NVMKEY .................................................................... 44
Core Architecture
Overview..................................................................... 15
CPU Architecture Overview................................................ 15
Customer Change Notification Service............................. 225
Custome r Notification Ser vice ............................ .............. 225
Customer Support.................................... ............. ...... ...... 225
D
Data Accumulators and Adder/Subtracter.......................... 21
Data Accumulators and Adder/Subtractor
Dat a Sp a c e Write Sa t u r a ti o n...... ...... ..... ...... .......... ..... 2 3
Overflow and Saturation............................................. 21
dsPIC30F3014/4013
DS70138G-page 220 2010 Microchip Technology Inc.
Round Logic................................................................22
Write-Back ..................................................................22
Data Address Space...........................................................30
Alignment....................................................................32
Alignment (Figure) ......................................................32
Effect of Invalid Memory Accesses (Table).................32
MCU and DSP (MAC Class) Instructions Example.....31
Memory Map...............................................................30
Near Data Space ........................................................33
Softwa re Stack.............. ........................... ...................33
Spaces........................................................................32
Width...........................................................................32
Data Converter Interface (DCI) Module ............................121
Data EEPROM Memory......................................................49
Erasing........................................................................50
Erasing, Block.............................................................50
Erasing, Word.............................................................50
Protection Agains t Spurious Write................... ...........52
Reading.......................................................................49
Write Verify .................................................................52
Writing.........................................................................51
Writing , Block.................. ..................... ..................... ..51
Writing , Wo rd ........... ............... ..................... ...............51
DC Characteristics............................................................172
BOR..........................................................................180
I/O Pin Input Specifications.......................................178
I/O Pin Output Specifications....................................178
Idle Current (IIDLE) ....................................................175
LVDL.........................................................................179
Operating Current (IDD).............................................174
Power-Down Current (IPD)........................................176
Program and EEPROM.............................................180
Temperature and Voltage Specifications..................172
DCI Module
Bit Clock Generator...................................................125
Buffer Alignment with Data Frames ..........................127
Buffe r Con trol....... ............... ..................... .................121
Buffe r Data Alignment....... .............. ..................... .....121
Buffer Length Control............................... .. .... .. .... .....127
COFS Pin.......................... ..................... ...................121
CSCK Pin.......................... ..................... ...................121
CSDI Pin...... .............. ..................... ............... ...........121
CSDO Mode Bit ........................................................128
CSDO Pin .................................................................121
Data Justification Control Bit.....................................126
Device Frequencies for Common Codec CSCK Frequen-
cies (Table).......................................................125
Digital Loopback Mode .............................................128
Enable.......................................................................123
Frame Sync Generator .............................................123
Frame Sync Mode Control Bits.................................123
I/O Pi n s.... ..................... ........................... .................121
Interrupts...................................................................128
Introduction ...............................................................121
Master Frame Sync Operation..................................123
Operation ..................................................................123
Operation During CPU Idle Mode.............................128
Operation During CPU Sleep Mode..........................128
Receive Slot Enable Bits.................................... .. .....126
Receive Status Bits...................................................127
Register Map...... ............... ..................... ...................130
Sample Clock Edge Control Bit.......................... .......126
Slave Frame Sync Operation....................................124
Slot Enable Bits Operation with Frame Sy nc............126
Slot Status Bits.............. ................................. ...........128
Synchronous Data Transfers.................................... 126
Timing Requirements
AC-Link Mode................................................... 195
Multichannel, I2S Modes.................... .. ....... .. .. .. 193
Transmit Slot Enable Bits ......................................... 126
Transmit Status Bits.................................................. 127
Transmit/Receive Shift Register............................... 121
Underflow Mode Control Bit......................... ....... .... ..128
Word-Size Selection Bits.......................................... 123
Development Support.......................................................167
Device Configuration
Register Map ............ ..................... ..................... ...... 158
Device Configuration Registers
FBORPOR................................................................ 156
FGS .......................................................................... 156
FOSC........................................................................ 156
FWDT ....................................................................... 156
Device Overview................................................................. 11
Disabling the UART........ ..................................... ......... .... 105
Divide Support ........................................... .. .... .... ....... .... .... 18
Instructions (Table)..................................................... 18
DSP Engine ........................................................................ 19
Multiplier ..................................................................... 21
Dual Output Compare Match Mode.................................... 86
Continuous Pulse Mode............................... ......... .... .. 86
Single Pulse Mode...................................................... 86
E
Elect r i ca l C h a ra c t e r i stics ... .. ...... ...... ..... .. ...... ...... ..... ...... .. . 171
AC............................................................................. 180
DC ............................................................................ 172
Enabling and Setting Up UART
Altern a te I/O ....................... ..................... ................. 105
Enabling and Setting up UART
Setting up Data, Parity and Stop Bit Selections........ 105
Enabling the UART........................................................... 105
Equations
ADC Conversion Clock............................................. 133
Baud Rate................................................................. 107
Bit Clock Frequency.................................................. 125
COFSG Perio d...... ..................... . .................... .......... 123
Serial Clock Rate........................................................ 96
Time Quantum for Clock Generation........................ 117
Errata.................................................................................... 9
Exception Sequence
Trap Sou rces................................. ........................... .. 62
Exter n a l C l o ck T iming Re quireme n t s ... ...... ...... ..... ...... ..... 182
Type A Timer............................................................ 188
Type B Timer............................................................ 189
Type C Timer............................................................ 189
External Interrupt Requests................................................ 64
F
Fast Context Saving ........................................................... 64
Flash Program Memory...... ................................. ............... 43
I
I/0 Ports
Register Map ............ ..................... ..................... ........ 55
I/O Pin Specifications
Input.......................................................................... 178
Output....................................................................... 178
I/O Ports................................ .................................. ............ 53
Parallel (PIO).............................................................. 53
I2C 10-Bit Slave Mode Operation ... ....... .... .. .... .. ....... .... .. .... 93
Reception ................................................................... 94
2010 Microchip Technology Inc. DS70138G-page 221
dsPIC30F3014/4013
Transmission...............................................................93
I2C 7-Bit Slave Mode Operation...................................... .. ..93
Reception....................................................................93
Transmission...............................................................93
I2C Master Mode Operation................................................95
Baud Rate Generator..................................................96
Clock Arbitration..........................................................96
Multi-Master Communication,
Bus Collision and Bus Arbitration .. .. ........... ........96
Reception....................................................................96
Transmission...............................................................95
I2C Master Mode Support ...................................................95
I2C Module..........................................................................91
Addresses...................................................................93
Bus Data Timing Requirements
Master Mode.....................................................201
Slave Mode.......................................................204
General Call Address Support....................................95
Interrupts.....................................................................95
IPMI Support...............................................................95
Operating Function Description ..................................91
Operation During CPU Sleep and Idle Modes............96
Pin Configuration ........................................................91
Programmer’s Model...................................... .............91
Register Map..................... ..................... .....................97
Registers.....................................................................91
Slope Control..............................................................95
Software Controlled Clock Stretching (STREN = 1)....94
Various Modes............................... .... .. .... .... ......... .. ....91
I2S Mode Operation..........................................................129
Data Just ification............. ............... ..................... ......129
Frame and Data Word Length Selection...................129
Idle Current (IIDLE) ............................................................175
In-Circuit Serial Programming (ICSP).........................43, 141
Input Capture Module ............... .... .. ....... .... .. .... .. ....... .... .. ....81
Interrupts.....................................................................82
Register Map..................... ..................... .....................83
Input Capture Operation During Sleep and Idle Modes......82
CPU Idle Mode............................................................82
CPU Sleep Mode........................................................82
Input Capture Timing Requirements.................................190
Input Change Notification Module................................. .... ..56
Register Map..................... ..................... .....................57
Instruction Addressing Modes.............................................37
File Register Instructions............................................37
Fundamental Modes Supported..................................37
MAC Instru ctions..................... ............... .....................38
MCU Inst ructions ......................... ..................... ..........37
Move and Accumulator Instructions............................38
Other Instructions........................................................38
Instruction Set
Overview...................................................................162
Summary...................................................................159
Internal Clock Timing Examples .......................................183
Inter net Address.................... ........................... .................225
Interrupt Controller
Register Map..................... ..................... .....................66
Inter rupt Priori ty ........................ ........................... ...............60
Traps...........................................................................62
Interrupt Sequence .................................... .... .... ............. ....63
Inter rupt Stack Frame..... .................................. ..........63
Interrupts.............................................................................59
L
Load Conditions........................ .... .. ....... .. .. .. .... .. .. ....... .. .. ..181
Low-Voltage Detect (LVD) ................................................155
LVDL Characteristics........................................................ 179
M
Memory Organization ......................................................... 25
Core Register Map ..................................................... 33
Microc h i p In te rnet Web Site.. ..................... ....................... 225
Modes of Operation
Disable...................................................................... 113
Initialization............................................................... 113
Listen All Messages................................................ .. 113
Listen On ly.......... ..................... ............... .................. 113
Loopback.................................................................. 113
Normal Operation........... ............... ......... .............. .... 113
Modulo Ad d ressi n g.... ...... ...... ..... .......... ...... ..... ...... ...... ....... 38
Applicability................................................................. 40
Incr e menti n g Bu f fe r Oper a t io n Examp l e ... .. ...... ...... ... 39
Start and End Address ............................................... 39
W Address Register Selection.................................... 39
MPLAB ASM30 Assembler, Linker, Librarian................... 168
MPLAB Integrated Development Environment Software.. 167
MPL AB PM3 D e v i ce Progr a mmer.. .. ...... .. ..... ...... ...... .. ..... 1 7 0
MPLAB REA L IC E In -Circuit Em ulator Syst e m...... .......... 169
MPL IN K Ob j e ct Linker/ MPLIB O b j ec t Li b ra ri a n... .. ...... ..... 1 6 8
N
NVMRegister Map.............................................................. 47
O
Operating Current (IDD) .................................................... 174
Operating Frequency vs Voltage
dsPIC30FXXXX -20 (Ex tended) ................................ 172
Oscillator
Configurations .......................................................... 144
Fail - Safe C l o c k Mon it o r ...... . . ...... ......... ...... ....... 14 6
Fast RC (FRC).................................................. 145
Initial Clock Source Selection........................... 144
Low- Powe r R C (L PR C ) ...... .. ...... ..... ...... ...... .. ... 14 5
LP Oscillator Control......................................... 145
Phase Locked Loop (PLL).......................... .. .... 145
Start- up Timer (OST).............................. .......... 144
Control Registers...................................................... 147
Ope ra ting M ode s ( Ta b l e ).. .. ...... ...... ...... ......... ...... ..... 14 2
System Overview...................................................... 141
Oscillat o r Selection... ...................................... .............. .... 141
Oscillator Start-up Timer
Timing Requirements ............................................... 187
Output Compare Interrupts................................................. 88
Outpu t Compare Module............. ..................... .................. 85
Register Map dsPIC30F3014..................................... 89
Register Map dsPIC30F4013..................................... 89
Timing Requirements ............................................... 190
Output Compare Operation During CPU Idle Mode ........... 88
Output Compare Sleep Mode Operation............................ 88
P
Packagi n g Information......................... ..................... ........ 211
Marking..................................................................... 211
Peripheral Module Disable (PMD) Registers.................... 157
Pinout Descriptions........................ .... .... .... .. ......... .... .... .... .. 13
POR. See Power-on Reset.
Power Saving Modes
Sleep and Idle........................................................... 141
Power-Down Current (IPD)................................................ 176
Power-Saving Modes........................................................ 155
Idle............................................................................ 156
dsPIC30F3014/4013
DS70138G-page 222 2010 Microchip Technology Inc.
Sleep.........................................................................155
Power-up Timer
Timing Requirements.................... .. ....... .... .. .... .. .. .....187
Program Address Space.....................................................25
Construction................................................................26
Data Access from Program Memory
Using Program Space Visibility...........................28
Data Access From Program Memory
Using Table Instructions .....................................27
Data Access from, Address Generation......................26
Data Space Window into Operation..................... .......29
Data Table Ac cess (lsw)..... ............... .........................27
Data Table Access (MSB)....... ........................... .........28
dsPIC30F3014 Memory Map......................................25
dsPIC30F4013 Memory Map......................................25
Table Instructions
TBLRDH..............................................................27
TBLRDL..............................................................27
TBLWTH.............................................................27
TBLWTL..............................................................27
Program and EEPROM Charac teristics.... ........................180
Program Counter. ................................................................16
Programmable...................................................................141
Programmer’s Model. ..........................................................16
Diagram ......................................................................17
Programming Operatio n s.............. ..................... .................45
Algorithm for Program Flash.......................................45
Erasing a Row of Program Memory............................45
Initiating the Programming Sequence.........................46
Loading Write Latches ........................... .... .. .. .... .. .......46
Protection Against Accidental Writes to OSCCON ...........146
R
Reader Response.............................................................226
Registers
OSCCON (Oscillator Control) ...................................147
OSCTUN (Oscillator Tuning) ....................................149
Reset.........................................................................141, 151
BOR, Programmable................................ .................153
Brown-out Reset (BOR)............................................141
Oscillator Start-up Timer (OST)................................141
PORO perating without FSCM and PWRT................153
With Long Crystal Start-up Time.......................153
POR (Power-on Reset).............................................151
Power-on Res e t (POR).......................... .............. .....141
Power-up Timer (PWRT) ................ ............... ...........141
Reset Sequence.................................. .... ......... .... .... .... .......61
Reset Sources ................ ..................... .......................61
Reset Sources
Brown-out Reset (BOR)..............................................61
Illegal Instruction Trap.................................................61
Trap Lock o ut...... ..................... ..................... ...............61
Uninitializ e d W Regis te r Trap ..... ................................61
Watchdog Time-out......................... ....... .. .... .. .... .. .......61
Reset Timing Requirements......................................... .....187
Revision History................................................................217
Run-Time Self-Programming (RTSP) .................................43
S
Simpl e Captu re Event Mode.......................... .....................81
Buffe r Ope ration.................. ..................... ...................82
Hall Sensor Mod e ..................... ............... ...................82
Prescaler.....................................................................81
Timer2 and Timer3 Selection Mode............................82
Simple OCx/PWM Mode Timing Requirements................191
Simp le Output Co m p a re Ma tch Mo d e .... ...... ...... ..... ...... ..... 86
Simple PWM Mode.............................................................86
Input Pin Fault Protection ........................................... 86
Period ......................................................................... 87
Software Simulator (MPLAB SIM) .................................... 169
Softwar e Stack Point e r, Frame Pointer ........... ................... 16
CALL Stack Fr a me..... ..................... ............... ............ 33
SPI Module......................................................................... 99
Framed SPI Support................................................. 100
Operating Function Description.................................. 99
Operation During CPU Idle Mode............................. 101
Operation During CPU Sleep Mode.......................... 101
SDOx Disabl e....................... ..................... ............... ..99
Slave Select Synchro n ization............ ..................... .. 101
SPI1 R e g i s t e r M a p . ...... ...... ...... ..... .. ...... ...... ..... ...... ... 102
Timing Requirements
Master Mode (CKE = 0). ................................... 196
Master Mode (CKE = 1). ................................... 197
Slave Mode (CKE = 0)...................................... 198
Slave Mode (CKE = 1)...................................... 200
Word and Byte Communication.................................. 99
Status Bits, Their Significance and the Initialization Condition
for RCON Register, Case 1......................................154
Status Bits, Their Significance and the Initialization Condition
for RCON Register, Case 2......................................154
STATUS Regi ster......................... ............... ..................... ..16
Symb o l s U se d i n Op c ode De scrip ti o n s .. .. ...... .. ..... ...... .. ... 160
System Integration............................................................ 141
Register Map ............ ..................... ..................... ...... 158
T
Table Instructi o n Oper a tion Summary................. ............... 43
Temperature and Voltage Specifications
AC............................................................................. 181
DC ............................................................................ 172
Timer1 Module.................................................................... 67
16-Bit Asynchronous Counter Mode........................... 67
16-Bit Synchronous Counter Mode............................. 67
16-Bit Timer Mode............................... ....................... 67
Gate Operation........................................................... 68
Interrupt ...................................................................... 68
Operation During Sleep Mode. . .................................. 68
Prescaler .................................................................... 68
Real-Time Clock......................................................... 68
Interrupts ............................................................ 68
Oscillato r Operation........ ......... ........ ......... .......... 68
Register Map ............ ..................... ..................... ........ 69
Timer2 and Timer3 Selection Mode.............................. .... ..85
Timer2/3 Module.............................................. .... ....... .... .... 71
16-Bit Timer Mode............................... ....................... 71
32-Bit Synchronous Counter Mode............................. 71
32-Bit Timer Mode............................... ....................... 71
ADC Event Trigger...................................................... 74
Gate Operation........................................................... 74
Interrupt ...................................................................... 74
Operation During Sleep Mode. . .................................. 74
Register Map ............ ..................... ..................... ........ 75
Timer Prescaler.......................................................... 74
Timer4/5 Module.............................................. .... ....... .... .... 77
Register Map ............ ..................... ..................... ........ 79
Timing Diagrams
A/D Conversion
Low-Speed (ASAM = 0, SSRC = 000).............. 208
Band Gap Start-up Time........................................... 187
Brown-ou t Re set Characteris tic s....... ........ ............... 179
CAN Bit..................................................................... 116
2010 Microchip Technology Inc. DS70138G-page 223
dsPIC30F3014/4013
CAN Module I/O........................................................205
CLKOUT and I/O. . .....................................................185
DCI Module
AC-Li n k Mode..... ..................... ..................... ....194
Multichannel, I2S Modes...................................192
External Clock...........................................................181
Frame Sync, AC-Link Start-Of-Frame .......................124
Frame Sync, Multichannel Mode ..............................124
I2C Bus Data
Master Mode.....................................................201
Slave Mode.......................................................203
I2C Bus Start/Stop Bits
Master Mode.....................................................201
Slave Mode.......................................................203
I2S Interface Frame Sync..........................................124
Input Capture (CAPx)............................................ .. ..190
Low-Voltage Detect...................................................178
OCx/PWM Module....................................................191
Oscillator Start-up Timer...........................................186
Output Co mpa re Module.................... ..................... ..190
Power-up Timer ............................. ..................... ......186
PWM Output..................... ........................... ...............87
Reset.........................................................................186
SPI Module
Master Mode (CKE = 0)....................................195
Master Mode (CKE = 1)....................................196
Slave Mode (CKE = 0)......................................197
Slave Mode (CKE = 1)......................................199
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1.............. ........152
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2.............. ........152
Time-out Sequence on Power-up
(MCLR Tied to VDD)..........................................152
Type A, B and C Timer External Clock.....................188
Watchdog Timer............................. .... .. .... .. ......... .. ....186
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy...............183
Timing Diagrams.See Timing Characteristics
Timing Requirements
A/D Conversion
Low-Speed........................................................209
Band Gap Start-up Time...........................................187
Brown-out Reset.......................................................187
CAN Module I/O........................................................205
CLKOUT and I/O. . .....................................................185
DCI Module
AC-Li n k Mode..... ..................... ..................... ....195
Multichannel, I2S Modes...................................193
External Clock...........................................................182
I2C Bus Data (Master Mode) .....................................201
I2C Bus Data (Slave Mode).......................................204
Input Capture.......................... ....... .. .... .. .... .. ....... .... ..190
Oscillator Start-up Timer...........................................187
Output Co mpa re Module.................... ..................... ..190
Power-up Timer ............................. ..................... ......187
Reset.........................................................................187
Simple OCx/PWM Mode...........................................191
SPI Module
Master Mode (CKE = 0)....................................196
Master Mode (CKE = 1)....................................197
Slave Mode (CKE = 0)......................................198
Slave Mode (CKE = 1)......................................200
Type A Time r Ex ternal Clock............... .....................188
Type B Time r Ex ternal Clock............... .....................189
Type C Ti m er Extern al Clo ck.... .. ...... ..... .. ...... ...... .. ... 18 9
Watchdog Timer ...................... .... .... .. ......... .... .. .... .... 187
Trap Vectors...................................... ................................. 63
U
UART Module
Addr e s s D e tect Mo d e......... ...... .. ...... ..... ...... ...... ...... . 107
Auto-Baud Support................................................... 108
Baud Rate Generator ............................................... 107
Enabling and Setting Up.............. .. .... .. ....... .. .. .... .. .. .. 105
Fram i n g Error (FERR ) . .. .. ..... ...... ...... ..... .. ...... ...... .. ... 107
Idle Status................................................................. 107
Loopback Mode............................. .... .. ......... .. .... .. .... 107
Operation During CPU Sleep and Idle Modes.......... 108
Overview................................................................... 103
Parity Error (PERR).................................................. 107
Receive Bre a k............ ..................... ............... .......... 107
Receive Buffer (UxRXB)........................................... 106
Receive Buffer Overrun Er r o r ( OERR Bit)................ 106
Receive Interrupt........ ............... ............... .............. .. 106
Rece i vi n g D a ta ...... ...... ..... ...... ...... ...... ..... ...... ...... ..... 1 0 6
Receiving in 8-Bit or 9-Bit Data Mode ...................... 106
Reception Error Handling ......................................... 106
Tran s mit Bre a k ........ ...... ..... ...... ...... .. ..... ...... ...... ...... . 106
Transmit Buffer (UxTXB) .......................................... 105
Tran s mit Interru p t .. .. ...... ..... ...... ...... ...... ..... .......... ..... 1 0 6
Tran s mitt ing D a ta ...... ...... ..... ...... ...... ..... ...... ...... ...... . 105
Tran s mitt ing i n 8- Bi t D a ta Mod e. ...... .. ..... ...... ...... ..... 1 0 5
Tran s mitt ing i n 9- Bi t D a ta Mod e. ...... .. ..... ...... ...... ..... 1 0 5
UAR T1 R e g i s t e r Ma p ....... ...... ...... ...... ......... ...... ...... . 109
UAR T2 R e g i s t e r Ma p ....... ...... ...... ...... ......... ...... ...... . 109
UART Operation
Idle Mode.................................................................. 108
Sleep Mode .............................................................. 108
Unit ID Locations.............................................................. 141
Universal Asynchronous Receiver Transmitter
(UART) Module.................................. .. ....... .... .... .. .... 103
W
Wake - u p f r o m Sl e e p.... .. ...... ..... ...... .. ...... ...... ..... ...... ...... .. . 141
Wake-up from Sleep and Idle............................................. 64
Watchdog Timer
Timing Requirements ............................................... 187
Watchdog Timer (WDT)............................................ 141, 155
Enabling and Disabling............................................. 155
Operation.................................................................. 155
WWW Address ............................ ................................. .... 22 5
WWW, On-Line Support....................................................... 9
dsPIC30F3014/4013
DS70138G-page 224 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS70138G-page 225
dsPIC30F3014/4013
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dsPIC30F3014/4013
DS70138G-page 226 2010 Microchip Technology Inc.
READER RESP ONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
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DS70138GdsPIC30F3014/4013
1. W hat ar e the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
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2010 Microchip Technology Inc. DS70138G-page 227
dsPIC30F3014/4013
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC30F4013AT-30I/PT-ES
Example:
dsPIC30F4013AT-30I/PT = 30 MIPS, Industrial temp., TQFP package, Rev. A
Trademark
Architecture
Flash
E = Extended High Temp -40°C to +125°C
I = Industrial -40°C to +85°C
Temperature
Device ID
Memory Size in Bytes
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
Cu stom ID (3 d ig i ts) o r
T = Tape and Reel
A,B,C… = Revision Level
Engineering Sample (ES)
Speed
20 = 20 MIPS
30 = 30 MIPS
Package
P = 40-pin PDIP
PT = 44-pin TQFP (10x10)
ML = 44-pin QFN (8x8)
S = Die (Waffle Pack)
W = Die (Wafers)
DS70138G-page 228 2010 Microchip Technology Inc.
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