1
2
3
4
5
6
GND
NR/FB
OUT
GND
IN
EN
1
KTT (DDPAK) PACKAGE
(TOP VIEW)
2
3
4
5
EN
IN
GND
OUT
NR/FB
EN
NC
GND
NR/FB
8
7
6
5
IN
IN
OUT
OUT
1
2
3
4
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
Ripple Rejection − dB
Output Spectral Noise Density V/- m Hz
Ö
DCQ PACKAGE
SOT223-6
(TOP VIEW)
0
10
20
30
40
50
60
70
80
Frequency (Hz)
1 10k 10M1k
IOUT = 1 mA
TPS78630
RIPPLE REJECTION
vs
FREQUENCY
IOUT = 1.5 A
VIN = 4 V
COUT = 10 mF
CNR = 0.01 mF
10 100 100k 1M
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Frequency (Hz)
100 10k 100k1k
IOUT = 1 mA
TPS78630
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
IOUT = 1.5 A
VIN = 5.5 V
COUT = 2.2 mF
CNR = 0.1 mF
TPS786xx
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 1.5-A
LOW-DROPOUT LINEAR REGULATORS
Check for Samples: TPS786xx
1FEATURES DESCRIPTION
234• 1.5-A Low-Dropout Regulator With Enable The TPS786xx family of low-dropout (LDO)
low-power linear voltage regulators features high
• Available in Fixed and Adjustable (1.2-V to power-supply rejection ratio (PSRR), ultralow noise,
5.5-V) Output Versions fast start-up, and excellent line and load transient
• High PSRR (49 dB at 10 kHz) responses in small outline, SOT223-6 and DDPAK-5
• Ultralow Noise (48 mVRMS, TPS78630) packages. Each device in the family is stable, with a
small 1-mF ceramic capacitor on the output. The
• Fast Start-Up Time (50 ms) family uses an advanced, proprietary BiCMOS
• Stable With a 1-mF Ceramic Capacitor fabrication process to yield extremely low dropout
• Excellent Load/Line Transient Response voltages (for example, 390 mV at 1.5 A). Each device
achieves fast start-up times (approximately 50 ms with
• Very Low Dropout Voltage (390 mV at Full a 0.001-mF bypass capacitor) while consuming very
Load, TPS78630) low quiescent current (265 mA, typical). Moreover,
• 3 × 3 SON PowerPAD™, 6-Pin SOT223 and when the device is placed in standby mode, the
5-Pin DDPAK Package supply current is reduced to less than 1 mA. The
TPS78630 exhibits approximately 48 mVRMS of output
APPLICATIONS voltage at 3.0-V output noise with a 0.1-mF bypass
• RF: VCOs, Receivers, ADCs capacitor. Applications with analog components that
are noise sensitive, such as portable RF electronics,
• Audio benefit from the high PSRR, low noise features, and
• Bluetooth®, Wireless LAN the fast response time.
• Cellular and Cordless Telephones
• Handheld Organizers, PDAs
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments Inc.
3Bluetooth is a registered trademark of Bluetooth SIG, Inc.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS786xx
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT (2)
TPS786xx yyy zXX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).
YYY is package designator.
Zis package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Output voltages from 1.3 V to 5.0 V in 100-mV increments are available; minimum order quantities may apply. Contact factory for details
and availability.
ABSOLUTE MAXIMUM RATINGS
Over operating temperature (unless otherwise noted)(1)
VALUE
VIN range –0.3 V to 6 V
VEN range –0.3 V to VIN + 0.3 V
VOUT range 6 V
Peak output current Internally limited
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
Continuous total power dissipation See Thermal Information table
Junction temperature range, TJ–40°C to +150°C
Storage temperature range, Tstg –65°C to +150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
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TPS786xx
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
THERMAL INFORMATION TPS786xx(3)
THERMAL METRIC(1)(2) DRB DCQ KTT UNITS
8 PINS 6 PINS 5 PINS
qJA Junction-to-ambient thermal resistance(4) 47.8 70.4 25
qJCtop Junction-to-case (top) thermal resistance(5) 83 70 35
qJB Junction-to-board thermal resistance(6) N/A N/A N/A °C/W
yJT Junction-to-top characterization parameter(7) 2.1 6.8 1.5
yJB Junction-to-board characterization parameter(8) 17.8 30.1 8.52
qJCbot Junction-to-case (bottom) thermal resistance(9) 12.1 6.3 0.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
.ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
.iii. KTT: The exposed pad is connected to the PCB ground layer through a 5x4 thermal via array.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
.ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
.iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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TPS786xx
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ= –40°C to +125°C), VEN = VIN, VIN = VOUT(nom) + 1 V(1), IOUT = 1 mA,
COUT = 10 mF, and CNR = 0.01 mF, unless otherwise noted. Typical values are at +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage, VIN (1) 2.7 5.5 V
Internal reference, VFB (TPS78601) 1.200 1.225 1.250 V
Continuous output current IOUT 0 1.5 A
Output voltage range TPS78601 1.225 5.5 – VDO V
TPS78601(2) 0mA≤IOUT ≤1.5 A, VOUT + 1 V ≤VIN ≤5.5 V(1) (0.98)VOUT VOUT (1.02)VOUT V
Output Fixed VOUT 0mA≤IOUT ≤1.5 A, VOUT + 1 V ≤VIN ≤5.5 V(1) –2.0 +2.0 %
voltage Accuracy < 5 V
Fixed VOUT 0mA≤IOUT ≤1.5 A, VOUT + 1 V ≤VIN ≤5.5 V(1) –3.0 +3.0 %
= 5 V
Output voltage line regulation (ΔVOUT%/VIN)(1) VOUT + 1 V ≤VIN ≤5.5 V 5 12 %/V
Load regulation (ΔVOUT%/VOUT) 0 mA≤IOUT ≤1.5 A 7 mV
TPS78628 IOUT = 1.5 A 410 580
TPS78630 IOUT = 1.5 A 390 550
Dropout voltage(3) mV
VIN = VOUT(nom) – 0.1 V TPS78633 IOUT = 1.5 A 340 510
TPS78650 IOUT = 1.5 A 310 470
Output current limit VOUT = 0 V 2.4 4.2 A
Ground pin current 0 mA≤IOUT ≤1.5 A 260 385 mA
Shutdown current(4) VEN = 0 V, 2.7 V ≤VIN ≤5.5 V 0.07 1 mA
FB pin current VFB = 1.225 V 1 mA
f = 100 Hz, IOUT = 10 mA 59
f = 100 Hz, IOUT = 1.5 A 52
Power-supply ripple rejection TPS78630 dB
f = 10 kHz, IOUT = 1.5 A 49
f = 100 kHz, IOUT = 1.5 A 32
CNR = 0.001 mF 66
CNR = 0.0047 mF 51
BW = 100 Hz to 100 kHz,
Output noise voltage (TPS78630) mVRMS
IOUT = 1.5 A CNR = 0.01 mF 49
CNR = 0.1 mF 48
CNR = 0.001 mF 50
Time, start-up (TPS78630) RL= 2 Ω, COUT = 1 mF CNR = 0.0047 mF 75 ms
CNR = 0.01 mF 110
High-level enable input voltage 2.7 V ≤VIN ≤5.5 V 1.7 VIN V
Low-level enable input voltage 2.7 V ≤VIN ≤5.5 V 0 0.7 V
EN pin current VEN = 0 –1 1 mA
UVLO threshold VCC rising 2.25 2.65 V
UVLO hysteresis 100 mV
(1) Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater. The TPS78650 is tested at VIN = 5.5 V.
(2) Tolerance of external resistors not included in this specification.
(3) Dropout is not measured for TPS78618 or TPS78625 since minimum VIN = 2.7 V.
(4) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
4Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS786xx
Current
Sense
Thermal
Shutdown
UVLO
UVLO
R1
FB
R2
External to
the Device
Overshoot
Detect
250 kΩ
Quickstart
Bandgap
Reference
1.225 V
IN
VIN
EN
GND
OUT
300Ω
VREF
ILIM SHUTDOWN
Current
Sense
Thermal
Shutdown
UVLO
UVLO
R1
R2
R2= 40 kΩ
Overshoot
Detect
250 kΩ
Quickstart
Bandgap
Reference
1.225 V
IN
VIN
EN
GND
NR
OUT
300Ω
VREF
ILIM SHUTDOWN
TPS786xx
www.ti.com
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
PIN CONFIGURATIONS
TERMINAL
DCQ KTT DRB
NAME (SOT223) (DDPAK) (SON) DESCRIPTION
Noise-reduction pin for fixed versions only. An external bypass capacitor, connected to this terminal, in
NR 5 5 5 conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise.
The EN terminal is an input that enables or shuts down the device. When EN is a logic high, the device
EN 1 1 8 is enabled. When the device is a logic low, the device is in shutdown mode.
FB 5 5 5 Feedback input voltage for the adjustable device.
GND 3, 6 3, TAB 6 Regulator ground
IN 2 2 1, 2 Input supply
OUT 4 4 3, 4 Regulator output
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2.95
2.96
2.97
2.98
2.99
3.00
3.01
3.02
3.03
3.04
3.05
0.0 0.3 0.6 0.9 1.2 1.5
VOUT (V)
IOUT (A)
VIN = 4 V
COUT = 10 µF
TJ = 25°C
0
1
2
3
4
5
−40−25−10 5 20 35 50 65 80 95 110 125
VOUT (V)
TJ (°C)
IOUT = 1 mA
2.798
2.794
2.790
2.782
2.778
IOUT = 1.5 A
VIN = 3.8 V
COUT = 10 µF
2.786
290
300
310
320
330
340
350
−40−25−10 5 20 35 50 65 80 95 110 125
IGND (µA)
TJ (°C)
VIN = 3.8 V
COUT = 10 µF
IOUT = 1 mA
IOUT = 1.5 A
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
Frequency (Hz)
100 10k 100k1k
Output Spectral Noise Density (µV//Hz)
IOUT = 1 mA
IOUT = 1.5 A
VIN = 5.5 V
COUT = 2.2 µF
CNR = 0.1 µF
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency (Hz)
100 10k 100k1k
Output Spectral Noise Density (µV//Hz)
IOUT = 1 mA
IOUT = 1.5 A
VIN = 5.5 V
COUT = 10 µF
CNR = 0.1 µF
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Frequency (Hz)
100 10k 100k1k
Output Spectral Noise Density − (µV//Hz)
VIN = 5.5 V
COUT = 10 µF
IOUT = 1.5 A
CNR = 0.1 µF
CNR = 0.01 µF
CNR = 0.0047 µF
CNR = 0.001 µF
TPS786xx
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
TPS78630 TPS78628 TPS78628
OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENT
vs vs vs
OUTPUT CURRENT JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2. Figure 3.
TPS78630 TPS78630 TPS78630
OUTPUT SPECTRAL OUTPUT SPECTRAL OUTPUT SPECTRAL
NOISE DENSITY NOISE DENSITY NOISE DENSITY
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 4. Figure 5. Figure 6.
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Product Folder Link(s): TPS786xx
0
10
20
30
40
50
60
70
80
RMS Output Noise (µVRMS)
CNR (µF)
IOUT = 1.5 A
COUT = 10 µF
BW = 100 Hz to 100 kHz
0.001 µF0.01 µF0.1 µF0.0047 µF
0
10
20
30
40
50
60
70
80
f (Hz)
1 10k 10M1k
Ripple Rejection − (dB)
IOUT = 1 mA
IOUT = 1.5 A
VIN = 4 V
COUT = 10 µF
CNR = 0.01 µF
10 100 100k 1M
0
10
20
30
40
50
60
70
80
f (Hz)
1 10k 10M1k
Ripple Rejection (dB)
IOUT = 1 mA
IOUT = 1.5 A
VIN = 4 V
COUT = 10 µF
CNR = 0.1 µF
10 100 100k 1M
0
10
20
30
40
50
60
70
80
f (Hz)
1 10k 10M1k
Ripple Rejection (dB)
IOUT = 1 mA
IOUT = 1.5 A
VIN = 4 V
COUT = 2.2 µF
CNR = 0.01 µF
10 100 100k 1M
0
10
20
30
40
50
60
70
80
f (Hz)
1 10k 10M1k
Ripple Rejection (dB)
IOUT = 1 mA
IOUT = 1.5 A
VIN = 4 V
COUT = 2.2 µF
CNR = 0.1 µF
10 100 100k 1M
5
4
2
−30
−60
3
0
30
60
VIN (V)
t (µs)
6040200 80 100 120 140 160 180 200
IOUT = 1.5 A
COUT = 10 µF
CNR = 0.01 µF
dv
dt +1 V
ms
∆VOUT (mV)
t (µs)
6
5
3
−40
−80
4
0
40
80
6040200 80 100 120 140 160 180 200
IOUT = 1.5 A
COUT = 10 µF
CNR = 0.01 µF
dv
dt +1 V
ms
VIN (V)
∆VOUT (mV)
∆VOUT (mV)
t (µs)
2
1
−1
−75
−150
0
0
75
150
IOUT (A)
3002001000 400 500 600 700 800 900 1000
VIN = 3.8 V
COUT = 10 µF
CNR = 0.01 µF
di
dt +1.5 A
ms
TPS786xx
www.ti.com
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
TYPICAL CHARACTERISTICS (continued)
TPS78630
ROOT MEAN SQUARED TPS78628 TPS78630
OUTPUT NOISE DROPOUT VOLTAGE RIPPLE REJECTION
vs vs vs
BYPASS CAPACITANCE JUNCTION TEMPERATURE FREQUENCY
Figure 7. Figure 8. Figure 9.
TPS78630 TPS78630 TPS78630
RIPPLE REJECTION RIPPLE REJECTION RIPPLE REJECTION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 10. Figure 11. Figure 12.
TPS78618 TPS78630 TPS78628
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 13. Figure 14. Figure 15.
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Time (µs)
4.0
3.5
2.5
0.5
0
3.0
1.0
1.5
2.0
VOUT (V)
4000 800 1200 1600 2000
VOUT = 2.5 V
RL = 1.6 Ω
CNR = 0.01 µF
VIN
VOUT
0
100
200
300
400
500
600
0 200 400 600 800 1000 1200 1400
VDO (mV)
IOUT (mA)
TJ = 125°C
TJ = −40°C
TJ = 25°C
0
50
100
150
200
250
300
350
400
450
500
2.5 3.0 3.5 4.0 4.5 5.0
VDO (mV)
VIN (V)
TJ = 125°C
TJ = −40°C
TJ = 25°C
IOUT = 1.5 A
COUT = 10 µF
CNR = 0.01 µF
ESR − Equivalent Series Resistance (Ω)
IOUT (mA)
Region of
Instability
100
10
1
0.1
0.01
COUT = 1 µF
Region of Stability
1 500 1000 150030 125
ESR − Equivalent Series Resistance (Ω)
IOUT (mA)
Region of
Instability
100
10
1
0.1
0.01
COUT = 2.2 µF
Region of Stability
1 500 1000 150030 125
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.5 2.0 2.5 3.0 3.5 4.0
MinimumVIN (V)
VOUT (V)
TJ=+125°C
IOUT =1.5A
TJ=+25°C
TPS786xx
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TPS78630 TPS78601
TPS78625 DROPOUT VOLTAGE DROPOUT VOLTAGE
POWER-UP/ vs vs
POWER-DOWN OUTPUT CURRENT INPUT VOLTAGE
Figure 16. Figure 17. Figure 18.
TPS78630 TPS78630
TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY
MINIMUM REQUIRED EQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCE
INPUT VOLTAGE (ESR) (ESR)
vs vs vs
OUTPUT VOLTAGE OUTPUT CURRENT OUTPUT CURRENT
Figure 19. Figure 20. Figure 21.
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0
0.25
0.50
0.75
1
1.25
1.50
1.75
2
2.25
2.50
2.75
3
0 100 200 300 400 500 600
t (µs)
VIN = 4 V,
COUT = 10 µF,
IIN = 1.5 A
Enable
CNR =
0.01 µF
CNR =
0.001 µF
CNR =
0.0047 µF
VOUT (V)
ESR − Equivalent Series Resistance (Ω)
IOUT (mA)
Region of
Instability
100
10
1
0.1
0.01
COUT = 10 µF
Region of Stability
1 500 1000 150030 125
TPS786xx
www.ti.com
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
TYPICAL CHARACTERISTICS (continued)
TPS78630
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT START-UP
Figure 22. Figure 23.
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS786xx
VIN VOUT
2.2 Fm
0.01 Fm
2.2 Fm
IN
EN GND
OUT
NR
TPS786xx
TPS786xx
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
APPLICATION INFORMATION
order for the regulator to operate properly, the current
The TPS786xx family of low-dropout (LDO) regulators flow out of the NR pin must be at a minimum,
has been optimized for use in noise-sensitive because any leakage current creates an IR drop
equipment. The device features extremely low across the internal resistor, thus creating an output
dropout voltages, high PSRR, ultralow output noise, error. Therefore, the bypass capacitor must have
low quiescent current (265 mA, typically), and enable minimal leakage current. The bypass capacitor
input to reduce supply currents to less than 1 mAshould be no more than 0.1-mF to ensure that it is
when the regulator is turned off. fully charged during the quickstart time provided by
the internal switch shown in the functional block
A typical application circuit is shown in Figure 24.diagram.
For example, the TPS78630 exhibits only 48 mVRMS
of output voltage noise using a 0.1-mF ceramic
bypass capacitor and a 10-mF ceramic output
capacitor. Note that the output starts up slower as the
bypass capacitance increases due to the RC time
constant at the bypass pin that is created by the
internal 250-kΩresistor and external capacitor.
Figure 24. Typical Application Circuit
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
EXTERNAL CAPACITOR REQUIREMENTS To improve ac measurements like PSRR, output
A 2.2-mF or larger ceramic input bypass capacitor, noise, and transient response, it is recommended that
connected between IN and GND and located close to the board be designed with separate ground planes
the TPS786xx, is required for stability and improves for VIN and VOUT, with each ground plane connected
transient response, noise rejection, and ripple only at the ground pin of the device. In addition, the
rejection. A higher-value input capacitor may be ground connection for the bypass capacitor should
necessary if large, fast-rise-time load transients are connect directly to the ground pin of the device.
anticipated and the device is located several inches
from the power source. REGULATOR MOUNTING
Like most low-dropout regulators, the TPS786xx The tab of the SOT223-6 package is electrically
requires an output capacitor connected between OUT connected to ground. For best thermal performance,
and GND to stabilize the internal control loop. The the tab of the surface-mount version should be
minimum recommended capacitor is 1 mF. Any 1 mFsoldered directly to a circuit-board copper area.
or larger ceramic capacitor is suitable. Increasing the copper area improves heat dissipation.
The internal voltage reference is a key source of Solder pad footprint recommendations for the devices
noise in an LDO regulator. The TPS786xx has an NR are presented in Application Report SBFA015,Solder
pin which is connected to the voltage reference Pad Recommendations for Surface-Mount Devices,
through a 250-kΩinternal resistor. The 250-kΩavailable from the TI web site at www.ti.com.
internal resistor, in conjunction with an external
bypass capacitor connected to the NR pin, creates a
low pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In
10 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS786xx
C1+(3 x 10−7) x (R1)R2)
(R1x R2)
VOUT +VREF ǒ1)R1
R2Ǔ
R1+ǒVOUT
VREF *1Ǔ R2
VIN VOUT
2.2 FmC1
R2
2.2 Fm
IN
EN
GND
OUT
FB
TPS78601 R1
1.8V 14.0kW30.1kW
57.9kW30.1kW
33pF
15pF3.6V
OUTPUT
VOLTAGE R1R2C1
OUTPUTVOLTAGE
PROGRAMMINGGUIDE
TPS786xx
www.ti.com
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
PROGRAMMING THE TPS78601 The approximate value of this capacitor can be
ADJUSTABLE LDO REGULATOR calculated using Equation 3:
The output voltage of the TPS78601 adjustable
regulator is programmed using an external resistor (3)
divider as shown in Figure 25. The output voltage is The suggested value of this capacitor for several
calculated using Equation 1:resistor ratios is shown in the table below. If this
capacitor is not used (such as in a unity-gain
configuration), then the minimum recommended
(1) output capacitor is 2.2 mF instead of 1 mF.
where: REGULATOR PROTECTION
• VREF = 1.2246 V typ (the internal reference
voltage) The TPS786xx PMOS-pass transistor has a built-in
back diode that conducts reverse current when the
Resistors R1and R2should be chosen for input voltage drops below the output voltage (for
approximately 40-mA divider current. Lower value example, during power down). Current is conducted
resistors can be used for improved noise from the output to the input and is not internally
performance, but the device wastes more power. limited. If extended reverse voltage operation is
Higher values should be avoided, as leakage current anticipated, external limiting might be appropriate.
at FB increases the output voltage error. The TPS786xx features internal current limiting and
The recommended design procedure is to choose thermal protection. During normal operation, the
R2= 30.1 kΩto set the divider current at 40 mA, TPS786xx limits output current to approximately
C1= 15 pF for stability, and then calculate R1using 2.8 A. When current limiting engages, the output
Equation 2:voltage scales back linearly until the overcurrent
condition ends. While current limiting is designed to
prevent gross device failure, care should be taken not
(2) to exceed the power dissipation ratings of the
In order to improve the stability of the adjustable package. If the temperature of the device exceeds
version, it is suggested that a small compensation approximately +165°C, thermal-protection circuitry
capacitor be placed between OUT and FB. shuts it down. Once the device has cooled down to
below approximately +140°C, regulator operation
resumes.
Figure 25. TPS78601 Adjustable LDO Regulator Programming
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS786xx
PD+ǒVIN *VOUTǓ IOUT
160
140
120
100
80
60
40
20
0
qJA ( C/W)
°
0 1 2 3 4 5 678 9 10
Board Copper Area ( )in2
DCQ
DRB
KTT
RqJA +()125OC*TA)
PD
TPS786xx
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
THERMAL INFORMATION
Knowing the maximum RqJA, the minimum amount of
POWER DISSIPATION PCB copper area needed for appropriate heatsinking
can be estimated using Figure 26.
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation.
Power dissipation of the device depends on input
voltage and load conditions and can be calculated
using Equation 4:
(4)
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
On the SON (DRB) package, the primary conduction
path for heat is through the exposed pad to the
printed circuit board (PCB). The pad can be Note: qJA value at board size of 9in2(that is, 3in ×
connected to ground or be left floating; however, it 3in) is a JEDEC standard.
should be attached to an appropriate amount of
copper PCB area to ensure the device does not Figure 26. qJA vs Board Size
overheat. On both SOT-223 (DCQ) and DDPAK
(KTT) packages, the primary conduction path for heat Figure 26 shows the variation of qJA as a function of
is through the tab to the PCB. That tab should be ground plane copper area in the board. It is intended
connected to ground. The maximum only as a guideline to demonstrate the effects of heat
junction-to-ambient thermal resistance depends on spreading in the ground plane and should not be
the maximum ambient temperature, maximum device used to estimate actual thermal performance in real
junction temperature, and power dissipation of the application environments.
device and can be calculated using Equation 5:NOTE: When the device is mounted on an
application PCB, it is strongly recommended to use
(5) ΨJT and ΨJB, as explained in the Estimating Junction
Temperature section.
12 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS786xx
Y Y
JT J T JT D
:T =T + P·
Y Y
JB J B JB D
:T =T + P·
35
30
25
20
15
10
5
0
Y Yand ( C/W)
JT JB °
0 2 46 8 10
Board Copper Area (in )
2
51 3 7 9
DCQ YJT
DCQ
DRB
KTT
KTT YJT
DRB YJT
YJB
(a) Example DRB (SON) Package Measurement (b) Example DCQ (SOT-223) Package Measurement
1mm
T on top
of IC
T
T on PCB
surface
B
(c) Example KTT (DDPAK) Package Measurement
1mm X
X
TT
TB
1mm
T on of IC
Ttop (1)
T on PCB
surface
B
(2)
TPS786xx
www.ti.com
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
ESTIMATING JUNCTION TEMPERATURE
Using the thermal metrics ΨJT and ΨJB, as shown in
the Thermal Information table, the junction
temperature can be estimated with corresponding
formulas (given in Equation 6). For backwards
compatibility, an older qJC,Top parameter is listed as
well.
(6)
Where PDis the power dissipation shown by
Equation 5, TTis the temperature at the center-top of
the IC package, and TBis the PCB temperature
measured 1mm away from the IC package on the
PCB surface (as Figure 28 shows). Figure 27. ΨJT and ΨJB vs Board Size
NOTE: Both TTand TBcan be measured on actual
application boards using a thermo-gun (an infrared For a more detailed discussion of why TI does not
thermometer). recommend using qJC(top) to determine thermal
characteristics, refer to application report SBVA025,
For more information about measuring TTand TB, see Using New Thermal Metrics, available for download
the application note SBVA025,Using New Thermal at www.ti.com. For further information, refer to
Metrics, available for download at www.ti.com.application report SPRA953,IC Package Thermal
By looking at Figure 27, the new thermal metrics (ΨJT Metrics, also available on the TI website.
and ΨJB) have very little dependency on board size.
That is, using ΨJT or ΨJB with Equation 6 is a good
way to estimate TJby simply measuring TTor TB,
regardless of the application board size.
(1) TTis measured at the center of both the X- and Y-dimensional axes.
(2) TBis measured below the package lead on the PCB surface.
Figure 28. Measuring Points for TTand TB
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS786xx
TPS786xx
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (August, 2010) to Revision L Page
• Corrected typo in Figure 28 ................................................................................................................................................ 13
Changes from Revision J (May, 2009) to Revision K Page
• Replaced the Dissipation Ratings table with the Thermal Information Table ....................................................................... 3
• Revised Thermal Information section ................................................................................................................................. 12
14 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS786xx
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS78601DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78601DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78601DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78601DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78601KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS78601KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78601KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78601KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78601KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78618DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78618DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78618DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78618DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78618KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS78618KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78618KTTRE3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78618KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS78618KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78618KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78625DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78625DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78625DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78625DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78625KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS78625KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78625KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78625KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78625KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78628DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78628DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78628KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS78628KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78628KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78630DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78630DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS78630DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78630DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78630KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS78630KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78630KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78633DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78633DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78633DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78633DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78633KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS78633KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78633KTTRE3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78633KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78633KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS78633KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 4
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS78601DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS78601DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS78601DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS78601KTTR DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78601KTTT DDPAK/
TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78618DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS78618KTTR DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78618KTTRE3 DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78618KTTT DDPAK/
TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78625DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS78625KTTR DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78625KTTT DDPAK/
TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78628DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS78628KTTT DDPAK/
TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78630DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS78630KTTT DDPAK/
TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78633DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS78633KTTR DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78633KTTRE3 DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS78633KTTT DDPAK/
TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS78601DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS78601DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS78601DRBT SON DRB 8 250 210.0 185.0 35.0
TPS78601KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
TPS78601KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0
TPS78618DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS78618KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
TPS78618KTTRE3 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
TPS78618KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0
TPS78625DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS78625KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
TPS78625KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0
TPS78628DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS78628KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0
TPS78630DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS78630KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0
TPS78633DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS78633KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
TPS78633KTTRE3 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
TPS78633KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 3
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