DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN NR/FB
OUT
1
2
34
5
EN OUT
LDO
1.8 V
SENSE RESET
SVS
3.3 V
SENSE RESET
SVS
1.8 V
EN OUT
LDO
3.3 V
TPS73219
TPS73619
or TPS73534
TPS73734
or
TPS3808G01
51 kW
10 kW10 kW
91 kW
15 kW13 kW
C2000
1.8 V
3.3 V
XRS
TPS3808G01
TPS3808G19
or
TPS73219
www.ti.com
SBVS166 –JUNE 2011
250mA Low-Dropout Regulator for C2000™
Check for Samples: TPS73219
1FEATURES DESCRIPTION
The TPS73219 family is a low-dropout (LDO) voltage
23•Optimal Output Voltage for Core Rail of C2000 regulator that offers very good line and load transient
•Good Line/Load Transient Response for MCUs response even without the use of an output capacitor.
•250mA LDO Voltage Regulator with Enable The TPS73219 is ideal for driving the C2000 MCUs
•Very Low Dropout Voltage: 40mV (typ) at fron Texas Instruments. The device offers very low
250mA dropout voltage, thereby reducing power loss.
•Reverse Current Protection In combination with a voltage supervisor such as the
•Stable with or without Output Capacitor TPS3808G19 or TPS3808G01, the TPS73219 can
•1% Overall Accuracy (Line, Load, and deliver tight VCORE voltages and generate accurate
Temperature) power-good signals that meet or exceed power
requirements for the C2000.
•Available in a 5-Pin SOT23 Package The TPS73219 is available in a 5-pin SOT23
APPLICATIONS package.
•C2000 Core Power Rail Supply
Figure 1. Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2C2000 is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS73219
SBVS166 –JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT (2)
TPS732xx yy yz XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).
YYY is package designator.
Zis package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com.
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available through the use of innovative factory EEPROM
programming; minimum order quantities may apply. Contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
Over operating junction temperature range unless otherwise noted.(1)
PARAMETER TPS73219 UNIT
VIN range –0.3 to 6.0 V
VEN range –0.3 to 6.0 V
VOUT range –0.3 to 5.5 V
VNR, VFB range –0.3 to 6.0 V
Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Thermal Information Table
Junction temperature range, TJ–55 to +150 °C
Storage temperature range –65 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2Copyright ©2011, Texas Instruments Incorporated
TPS73219
www.ti.com
SBVS166 –JUNE 2011
THERMAL INFORMATION TPS73219(3)
THERMAL METRIC(1)(2) DBV UNITS
5 PINS
θJA Junction-to-ambient thermal resistance(4) 180
θJCtop Junction-to-case (top) thermal resistance(5) 64
θJB Junction-to-board thermal resistance(6) 35 °C/W
ψJT Junction-to-top characterization parameter(7) N/A
ψJB Junction-to-board characterization parameter(8) N/A
θJCbot Junction-to-case (bottom) thermal resistance(9) N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) There is no exposed pad with the DBV package.
(b) The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in ×3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright ©2011, Texas Instruments Incorporated 3
TPS73219
SBVS166 –JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ=–40°C to +125°C), VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and
COUT = 0.1μF, unless otherwise noted. Typical values are at TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 2.05 5.5 V
Nominal TJ= +25°C–0.5 +0.5
VOUT Accuracy %
VOUT + 0.5V ≤VIN ≤5.5V;
VIN, IOUT, and T –1.0 ±0.5 +1.0
10 mA ≤IOUT ≤250mA
ΔVOUT%/ΔVIN Line regulation VOUT(nom) + 0.5V ≤VIN ≤5.5V 0.01 %/V
1mA ≤IOUT ≤250mA 0.002
ΔVOUT%/ΔIOUT Load regulation %/mA
10mA ≤IOUT ≤250mA 0.0005
Dropout voltage
VDO IOUT = 250mA 40 150 mV
(VIN = VOUT (nom) –0.1V)
ZO(DO) Output impedance in dropout 1.7 V ≤VIN ≤VOUT + VDO 0.25 Ω
ICL Output current limit VOUT = 0.9 ×VOUT(nom) 250 425 600 mA
ISC Short-circuit current VOUT = 0V 300 mA
IREV Reverse leakage current(1) (–IIN) VEN ≤0.5V, 0V ≤VIN ≤VOUT 0.1 10 μA
IOUT = 10mA (IQ) 400 550
IGND GND pin current μA
IOUT = 250mA 650 950
VEN ≤0.5V, VOUT ≤VIN ≤5.5,
ISHDN Shutdown current (IGND) 0.02 1 µA
–40°C≤TJ≤+100°C
f = 100Hz, IOUT = 250 mA 58
Power-supply rejection ratio
PSRR dB
(ripple rejection) f = 10kHz, IOUT = 250 mA 37
COUT = 10μF, No CNR 27 ×VOUT
Output noise voltage
VNμVRMS
BW = 10Hz –100kHz COUT = 10μF, CNR = 0.01μF 8.5 ×VOUT
VOUT = 3V, RL= 30Ω
tSTR Startup time 600 μs
COUT = 1 μF, CNR = 0.01 μF
VEN(HI) EN pin high (enabled) 1.7 VIN V
VEN(LO) EN pin low (shutdown) 0 0.5 V
IEN(HI) EN pin current (enabled) VEN = 5.5V 0.02 0.1 μA
Shutdown Temp increasing +160
TSD Thermal shutdown temperature °C
Reset Temp decreasing +140
TJOperating junction temperature –40 +125 °C
(1) Fixed-voltage versions only; refer to Applications section for more information.
4Copyright ©2011, Texas Instruments Incorporated
Servo
Error
Amp
Ref
27kΩ
8kΩ
Current
Limit
Thermal
Protection
Bandgap
NR
OUT
R1
R2
EN
GND
IN
R1+ R2= 80kΩ
4MHz
Charge Pump
TPS73219
www.ti.com
SBVS166 –JUNE 2011
FUNCTIONAL BLOCK DIAGRAM
Figure 2. Fixed Voltage Version
Copyright ©2011, Texas Instruments Incorporated 5
DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN NR/FB
OUT
1
2
34
5
TPS73219
SBVS166 –JUNE 2011
www.ti.com
PIN CONFIGURATION
PIN DESCRIPTIONS
SOT23
(DBV)
NAME PIN NO. DESCRIPTION
IN 1 Input supply
GND 2 Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
EN 3 shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN
can be connected to IN if not used.
Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by
NR 4 the internal bandgap, reducing output noise to very low levels.
Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set
FB 4 the output voltage of the device.
OUT 5 Output of the Regulator. There are no output capacitor requirements for stability.
6Copyright ©2011, Texas Instruments Incorporated
0.5
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
Change in VOUT (%)
0 50 100 150 200 250
IOUT (mA)
Referred to IOUT = 10mA
−40_C
+125_C
+25_C
0.20
0.15
0.10
0.05
0
−0.05
−0.10
−0.15
−0.20
Change in VOUT (%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIN −VOUT (V)
+125_C+25_C
−40_C
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
100
80
60
40
20
0
VDO (mV)
0 50 100 150 200 250
IOUT (mA)
+125_C
+25_C
−40_C
TPS73225DBV
100
80
60
40
20
0
VDO (mV)
−50 −25 0 25 50 75 100 125
Temperature (_C)
TPS73225DBV
IOUT = 250mA
30
25
20
15
10
5
0
Percent of Units (%)
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VOUT Error (%)
IOUT = 10mA
TPS73219
www.ti.com
SBVS166 –JUNE 2011
TYPICAL CHARACTERISTICS
For all voltage versions at TJ= 25°C, VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted.
LOAD REGULATION LINE REGULATION
Figure 3. Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
Figure 5. Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM
Figure 7. Figure 8.
Copyright ©2011, Texas Instruments Incorporated 7
1000
900
800
700
600
500
400
300
200
100
0
IGND (µA)
0 50 100 150 200 250
IOUT (mA)
VIN = 5.5V
VIN = 4V
VIN = 2V
800
700
600
500
400
300
200
100
0
IGND (µA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
IOUT = 250mA
VIN = 5.5V
VIN = 4V
VIN = 2V
500
450
400
350
300
250
200
150
100
50
0
OutputCurrent(mA)
-0.5 0 1.0 1.5 2.0 2.5 3.0 3.5
OutputVoltage(V)
0.5
TPS73233
ISC
ICL
1
0.1
0.01
IGND (µA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
VENABLE = 0.5V
VIN = VOUT + 0.5V
600
550
500
450
400
350
300
250
Current Limit (mA)
1.5 2.5 3.0 3.5 4.0 4.5 5.02.0 5.5
VIN (V)
600
550
500
450
400
350
300
250
Current Limit (mA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
TPS73219
SBVS166 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted.
GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE
Figure 9. Figure 10.
GROUND PIN CURRENT IN SHUTDOWN
vs TEMPERATURE CURRENT LIMIT vs VOUT (FOLDBACK)
Figure 11. Figure 12.
CURRENT LIMIT vs VIN CURRENT LIMIT vs TEMPERATURE
Figure 13. Figure 14.
8Copyright ©2011, Texas Instruments Incorporated
40
35
30
25
20
15
10
5
0
PSRR(dB)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V V-(V)
IN OUT
Frequency=10kHz
C =10 F
V =2.5V
I =100mA
m
OUT
OUT
OUT
10k10
90
80
70
60
50
40
30
20
10
0
Ripple Rejection (dB)
100 1k 100k 1M 10M
Frequency (Hz)
IOUT = 1mA
COUT = 1µF
IOUT = Any
COUT = 0µF
VIN = VOUT + 1V
IOUT = 1mA
COUT = Any
IOUT = 1mA
COUT = 10µF
IOUT = 100mA
COUT = Any
IOUT = 100mA
COUT = 10µF
IO=100mA
CO=1µF
1
0.1
0.01
eN(µV/√Hz)
10 100 1k 10k 100k
Frequency (Hz)
COUT = 1µF
COUT = 0µF
COUT = 10µF
IOUT = 150mA
1
0.1
0.01
eN(µV/√Hz)
10 100 1k 10k 100k
Frequency (Hz)
IOUT = 150mA
COUT = 1µF
COUT = 0µF
COUT = 10µF
60
50
40
30
20
10
0
VN(RMS)
COUT (µF)
0.1 1 10
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
CNR = 0.01µF
10Hz < Frequency < 100kHz
140
120
100
80
60
40
20
0
VN(RMS)
CNR (F)
1p 10p 100p 1n 10n
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
COUT = 0µF
10Hz < Frequency < 100kHz
TPS73219
www.ti.com
SBVS166 –JUNE 2011
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN - VOUT
Figure 15. Figure 16.
NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY
CNR = 0µF CNR = 0.01µF
Figure 17. Figure 18.
RMS NOISE VOLTAGE vs COUT RMS NOISE VOLTAGE vs CNR
Figure 19. Figure 20.
Copyright ©2011, Texas Instruments Incorporated 9
10µs/div
50mV/tick
50mV/tick
50mV/tick
50mA/tick
VIN = 3.8V COUT = 0µF
COUT = 1µF
COUT = 10µF
10mA
250mA
VOUT
VOUT
VOUT
IOUT
10µs/div
50mV/div
50mV/div
1V/div
VOUT
VOUT
VIN
IOUT = 250mA
5.5V
4.5V
dVIN
dt = 0.5V/µs
COUT = 0µF
COUT = 100µF
100µs/div
1V/div
1V/div
RL= 20Ω
COUT = 10µF
2V
0V
RL= 1kΩ
COUT = 0µF
RL= 20Ω
COUT = 1µF
VOUT
VEN
100µs/div
1V/div
1V/div
RL= 20Ω
COUT = 10µF
2V
0V
RL= 1kΩ
COUT = 0µF
RL= 20Ω
COUT = 1µF
VOUT
VEN
6
5
4
3
2
1
0
−1
−2
Volts
50ms/div
VIN
VOUT
10
1
0.1
0.01
IENABLE (nA)
−50 −25 0 25 50 75 100 125
Temperature (°C)
TPS73219
SBVS166 –JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted.
TPS73233 TPS73233
LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 21. Figure 22.
TPS73233 TPS73233
TURN-ON RESPONSE TURN-OFF RESPONSE
Figure 23. Figure 24.
TPS73233
POWER UP / POWER DOWN IENABLE vs TEMPERATURE
Figure 25. Figure 26.
10 Copyright ©2011, Texas Instruments Incorporated
60
55
50
45
40
35
30
25
20
VN(rms)
CFB (F)
10p 100p 1n 10n
VOUT = 2.5V
COUT = 0µF
R1= 39.2kΩ
10Hz < Frequency < 100kHz
160
140
120
100
80
60
40
20
0
IFB (nA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
5µs/div
100mV/div
100mV/div
VOUT
VOUT
VIN
4.5V
3.5V
COUT = 0µF
VOUT = 2.5V
CFB = 10nF
COUT = 10µF
10µs/div
100mV/div
100mV/div
VOUT
VOUT
IOUT
250mA
10mA
COUT = 0µF
CFB = 10nF
R1= 39.2kΩ
COUT = 10µF
TPS73219
www.ti.com
SBVS166 –JUNE 2011
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= 25°C, VIN = 2.4V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted.
TPS73201 TPS73201
RMS NOISE VOLTAGE vs CFB IFB vs TEMPERATURE
Figure 27. Figure 28.
TPS73201 TPS73201
LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION
Figure 29. Figure 30.
Copyright ©2011, Texas Instruments Incorporated 11
VN+32mVRMS (R1)R2)
R2
+32mVRMS VOUT
VREF
TPS732xx
GNDEN
ON
OFF
NR
IN OUT
VIN VOUT
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
Optionaloutputcapacitor.
Mayimproveloadtransient,
noise,orPSRR.
Optionalbypass
capacitortoreduce
outputnoise.
VN(mVRMS)+27ǒmVRMS
VǓ VOUT(V)
VN(mVRMS)+8.5ǒmVRMS
VǓ VOUT(V)
TPS73219
SBVS166 –JUNE 2011
www.ti.com
APPLICATION INFORMATION
types and values of capacitors. In applications where
The TPS73219 belongs to a family of new generation multiple low ESR capacitors are in parallel, ringing
LDO regulators that use an NMOS pass transistor to may occur when the product of COUT and total ESR
achieve ultra-low-dropout performance, reverse drops below 50nΩF. Total ESR includes all parasitic
current blockage, and freedom from output capacitor resistances, including capacitor ESR and board,
constraints. These features, combined with low noise socket, and solder joint resistance. In most
and an enable input, make the TPS73219 ideal for applications, the sum of capacitor ESR and trace
portable applications. This regulator family offers a resistance will meet this requirement.
wide selection of fixed output voltage versions and an
adjustable output version. All versions have thermal OUTPUT NOISE
and over-current protection, including foldback
current limit. A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
Figure 31 shows the basic circuit connections for the the dominant noise source within the TPS73219 and
fixed voltage models. it generates approximately 32µVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
(1)
Since the value of VREF is 1.2V, this relationship
reduces to:
(2)
for the case of no CNR.
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions An internal 27kΩresistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
For best accuracy, make the parallel combination of voltage reference when an external noise reduction
R1and R2approximately equal to 19kΩ. This 19kΩ,capacitor, CNR, is connected from NR to ground. For
in addition to the internal 8kΩresistor, presents the CNR = 10nF, the total noise in the 10Hz to 100kHz
same impedance to the error amp as the 27kΩbandwidth is reduced by a factor of ~3.2, giving the
bandgap reference output. This impedance helps approximate relationship:
compensate for leakages into the error amp
terminals.
(3)
INPUT AND OUTPUT CAPACITOR for CNR = 10nF.
REQUIREMENTS This noise reduction effect is shown as RMS Noise
Although an input capacitor is not required for Voltage vs CNR (Figure 20) in the Typical
stability, it is good analog design practice to connect Characteristics section.
a 0.1μF to 1μF low ESR capacitor across the input
supply near the regulator. This counteracts reactive The TPS73219 uses an internal charge pump to
input sources and improves transient response, noise develop an internal supply voltage sufficient to drive
rejection, and ripple rejection. A higher-value the gate of the NMOS pass element above VOUT. The
capacitor may be necessary if large, fast rise-time charge pump generates ~250μV of switching noise at
load transients are anticipated or the device is ~4MHz; however, charge-pump noise contribution is
located several inches from the power source. negligible at the output of the regulator for most
values of IOUT and COUT.
The TPS73219 does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
12 Copyright ©2011, Texas Instruments Incorporated
TPS73219
www.ti.com
SBVS166 –JUNE 2011
BOARD LAYOUT RECOMMENDATION TO time after VIN has been removed. This scenario can
IMPROVE PSRR AND NOISE PERFORMANCE result in reverse current flow (if the IN pin is low
impedance) and faster ramp times upon power-up. In
To improve ac performance such as PSRR, output addition, for VIN ramp times slower than a few
noise, and transient response, it is recommended that milliseconds, the output may overshoot upon
the PCB be designed with separate ground planes for power-up.
VIN and VOUT, with each ground plane connected only
at the GND pin of the device. In addition, the ground Note that current limit foldback can prevent device
connection for the bypass capacitor should connect start-up under some conditions. See the Internal
directly to the GND pin of the device. Current Limit section.
INTERNAL CURRENT LIMIT DROPOUT VOLTAGE
The TPS73219 internal current limit helps protect the The TPS73219 uses an NMOS pass transistor to
regulator during fault conditions. Foldback current achieve extremely low dropout. When (VIN –VOUT) is
limit helps to protect the regulator from damage less than the dropout voltage (VDO), the NMOS pass
during output short-circuit conditions by reducing device is in its linear region of operation and the
current limit when VOUT drops below 0.5V. See input-to-output resistance is the RDS-ON of the NMOS
Figure 12 in the Typical Characteristics section for a pass element.
graph of IOUT vs VOUT.For large step changes in load current, the TPS73219
Note from Figure 12 that approximately –0.2V of VOUT requires a larger voltage drop from VIN to VOUT to
results in a current limit of 0mA. Therefore, if OUT is avoid degraded transient response. The boundary of
forced below –0.2V before EN goes high, the device this transient dropout region is approximately twice
may not start up. In applications that work with both a the dc dropout. Values of VIN –VOUT above this line
positive and negative voltage supply, the TPS73219 insure normal transient response.
should be enabled first. Operating in the transient dropout region can cause
an increase in recovery time. The time required to
ENABLE PIN AND SHUTDOWN recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
The enable pin (EN) is active high and is compatible of change in load current, and the available
with standard TTL-CMOS levels. A VEN below 0.5V headroom (VIN to VOUT voltage drop). Under
(max) turns the regulator off and drops the GND pin worst-case conditions [full-scale instantaneous load
current to approximately 10nA. When EN is used to change with (VIN –VOUT) close to dc dropout levels],
shutdown the regulator, all charge is removed from the TPS73219 can take a couple of hundred
the pass transistor gate, and the output ramps back microseconds to return to the specified regulation
up to a regulated VOUT (see Figure 23). accuracy.
When shutdown capability is not required, EN can be
connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass
transistor may be left on (enhanced) for a significant
Copyright ©2011, Texas Instruments Incorporated 13
dVńdt +VOUT
COUT 80kWøRLOAD
PD+(VIN *VOUT) IOUT
TPS73219
SBVS166 –JUNE 2011
www.ti.com
TRANSIENT RESPONSE Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
The low open-loop output impedance provided by the inadequate heatsink. For reliable operation, junction
NMOS pass element in a voltage follower temperature should be limited to +125°C maximum.
configuration allows operation without an output To estimate the margin of safety in a complete design
capacitor for many applications. As with any (including heatsink), increase the ambient
regulator, the addition of a capacitor (nominal value temperature until the thermal protection is triggered;
1μF) from the OUT pin to ground will reduce use worst-case loads and signal conditions. For good
undershoot magnitude but increase its duration. In reliability, thermal protection should trigger at least
the adjustable version, the addition of a capacitor, +35°C above the maximum expected ambient
CFB, from the OUT pin to the FB pin will also improve condition of your application. This produces a
the transient response. worst-case junction temperature of +125°C at the
highest expected ambient temperature and
The TPS73219 does not have active pull-down when worst-case load.
the output is over-voltage. This allows applications
that connect higher voltage sources, such as The internal protection circuitry of the TPS73219 has
alternate power supplies, to the output. This also been designed to protect against overload conditions.
results in an output overshoot of several percent if the It was not intended to replace proper heatsinking.
load current quickly drops to zero when a capacitor is Continuously running the TPS73219 into thermal
connected to the output. The duration of overshoot shutdown will degrade device reliability.
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output POWER DISSIPATION
capacitor COUT and the internal/external load
resistance. The rate of decay is given by: The ability to remove heat from the die is different for
each package type, presenting different
(Fixed voltage version) considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
(4) Performance data for JEDEC low- and high-K boards
are shown in the Thermal Information table. Using
REVERSE CURRENT heavier copper will increase the effectiveness in
removing heat from the device. The addition of plated
The NMOS pass element of the TPS73219 provides through-holes to heat-dissipating layers will also
inherent protection against current flow from the improve the heat-sink effectiveness.
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all Power dissipation depends on input voltage and load
charge is removed from the gate of the pass element, conditions. Power dissipation (PD) is equal to the
the EN pin must be driven low before the input product of the output current times the voltage drop
voltage is removed. If this is not done, the pass across the output pass element (VIN to VOUT):
element may be left on due to stored charge on the (5)
gate. Power dissipation can be minimized by using the
After the EN pin is driven low, no bias voltage is lowest possible input voltage necessary to assure the
needed on any pin for reverse current blocking. Note required output voltage.
that reverse current is specified as the current flowing
out of the IN pin due to voltage applied on the OUT PACKAGE MOUNTING
pin. There will be additional current flowing into the
OUT pin due to the 80kΩinternal resistor divider to Solder pad footprint recommendations for the
ground (see Figure 2). TPS73219 are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
THERMAL PROTECTION Devices (SBFA015), available from the Texas
Instruments web site at www.ti.com.
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
14 Copyright ©2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 7-Apr-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS73219DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73219DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73219DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73219DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73219DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73219DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73219DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73219DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2011
Pack Materials-Page 2
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