NOV2221 PRODUCT BRIEF
NOV2221TM
SINGLE PORT ATM/POS 622 Mb/s PHYSICAL LAYER IC
1. GENERAL DESCRIPTION
The NOV2221 is an integrated circuit
that implements single-channel
ATM/Packet Over SONET/SDH
(POS) processing functions at
622.08Mb/s. The part contains both
the PMD and the TC sublayers and
has UTOPIA Level 2 interface to the
ATM layer or optionally POS interface
to the link layer. The NOV2221 is fully
compliant with the SONET/SDH, B-
ISDN ATM Forum User Network
Interface requirements and standards,
and Compliant with PPP protocol over
SONET/SDH (RFC 1619/1662 of the
IETF). The PMD sublayer is based on
Novanet Semiconductor’s Hi-PHY
technology for high-speed data and
clock recovery. The UTOPIA Level
2/POS interfaces provide variable
modes of operation when interfacing
the ATM layer or link layer in order to
facilitate the connection of the
NOV2221 to different ATM layer or
Packet Over SONET/SDH link layer
devices.
The NOV2221 is targeted for use
primarily within ATM switches,
routers and WAN switches supporting
Packet over SONET/SDH. The device
is manufactured using 0.25µ CMOS
technology and packaged in a 256 pin
PBGA package.
For additional information please contact
our customer support by e-mail:
info@novanetsemi.com or by phone
(+972-97464411) or fax (+972-9
7464422).
PRODUCT FEATURES INCLUDE
q Processes 622 Mb/s STS-
12c/STM-4 data stream
q Interfaces to Optical Fiber
Transceivers
q Provides UTOPIA Level 2 Interface
q Provide POS interface
q On-chip clock and data recovery
and clock synthesis
q 3.3 Volt, 0.25µ CMOS technology
APPLICATIONS
q Switches
q Routers
q ATM/Packet Over SONET/SDH
Interfaces
NOV2221 PRODUCT BRIEF
2. BLOCK DIAGRAM
This block diagram illustrates the functional blocks of the NOV2221 device.
Hi-PHY™ - Implements the physical interface to the optical transceiver and the
serial to parallel and parallel to serial function.
Framer - Implements the SONET/SDH frame processing.
ATM Processor - Implements cell processing functions such as cell
delineation, HEC verification and calculation etc.
POS Processor - Implements packet processing functions such as flag
detection and generation, FCS verification and calculation etc.
FIFO - The memory cells where the cells/packets data is stored before
processing (transmit path) and after processing (receive path).
UTOPIA - Implements the interface functions between the PHY and the ATM
layer (ATM mode).
POS Interface - Implements the interface functions between the PHY and the
Link layer (POS mode).
Clock
Synthesis
Data &
Clock
Recovery
Serial to
Parallel
Parallel to
Serial
Tx
SONET/
SDH
Framer
Rx
SONET/
SDH
Framer
Tx
Overhead
Processor
Rx
Overhead
Processor
Tx ATM
Cell
Processor
Rx ATM
Cell
Processor
Tx POS
Processor
Rx POS
Processor
Hi-PHY
UTOPIA
Level 2/
POS
Interface
PORT 0
RefCLK+
RxD0-
RxD0+
TxD0-
TxD0+
LDCC
Microprocessor
Interface
D[7:0]
A[5:0]
*CS
W/*R
*DSTB
*INTR
JTAG
Interface
TDO
TDI
TCK
TMS
*TRST
TSDCC 1-4
TSDCK 1-4
TLDCC 1-4
TLDCK 1-4
RSDCC 1-4
RSDCK 1-4
RLDCC 1-4
RLDCC 1-4
Sec./Line DCC i/f ASSI
ASCLK
*ASSTB
ASDO
Rx_EOP
TxData[31:0]
TxAdd[4:0]
TxSOC/P[3:0]
*TxEnb[3:0]
TxClav/PTPAx4
TxPrty
Tx_ERR
RxData[31:0]
RxAdd[4:0]
RxSOC/P[3:0]
*RxEnb[3:0]
RxClav/PRPAx4
RxPrty
RxCLK
Tx_STPA
TxCLK
Tx_EOP
Tx_MOD
Rx_RVAL
Rx_ERR
Rx_MOD
NOV2221 PRODUCT BRIEF
3. TYPICAL APPLICATION
The figure below demonstrates
connection of a NOV2221 to a
single-port ATM Layer Device
according to UTOPIA Level 2.
Connection is performed using
the Direct Status Indication
mode, in which a dedicated
RxClav and TxClav is used to
provide direct indication of the
status of the FIFOs of each
port. Cell transmission is made
to/from the PHY port. Receive
and transmit channels work
simultaneously and
independently. This mode
supports 16-bit data bus width.
TxData[15:0]
TxAdd[4:0]
TxSOC
*TxEnb
TxClav
TxPrty
TxCLK
RxData[15:0]
RxAdd[4:0]
RxSOC
*RxEnb
RxClav
RxPrty
RxCLK
NOV2221 ATM LAYER
DEVICE
RxD+/-
TxD+/-
Optical Tranceiver
