NOV2221 PRODUCT BRIEF NOV2221TM SINGLE PORT ATM/POS 622 Mb/s PHYSICAL LAYER IC 1. GENERAL DESCRIPTION The NOV2221 is an integrated circuit that implements single-channel ATM/Packet Over SONET/SDH (POS) processing functions at 622.08Mb/s. The part contains both the PMD and the TC sublayers and has UTOPIA Level 2 interface to the ATM layer or optionally POS interface to the link layer. The NOV2221 is fully compliant with the SONET/SDH, BISDN ATM Forum User Network Interface requirements and standards, and Compliant with PPP protocol over SONET/SDH (RFC 1619/1662 of the IETF). The PMD sublayer is based on Novanet Semiconductor's Hi-PHY technology for high-speed data and clock recovery. The UTOPIA Level 2/POS interfaces provide variable modes of operation when interfacing the ATM layer or link layer in order to facilitate the connection of the NOV2221 to different ATM layer or Packet Over SONET/SDH link layer devices. PRODUCT FEATURES INCLUDE APPLICATIONS q q q q q q Processes 622 Mb/s STS12c/STM-4 data stream Interfaces to Optical Fiber Transceivers Provides UTOPIA Level 2 Interface Provide POS interface On-chip clock and data recovery and clock synthesis 3.3 Volt, 0.25 CMOS technology The NOV2221 is targeted for use primarily within ATM switches, routers and WAN switches supporting Packet over SONET/SDH. The device is manufactured using 0.25 CMOS technology and packaged in a 256 pin PBGA package. For additional information please contact our customer support by e-mail: info@novanetsemi.com or by phone (+972-97464411) or fax (+972-9 7464422). q q q Switches Routers ATM/Packet Over SONET/SDH Interfaces NOV2221 PRODUCT BRIEF 2. BLOCK DIAGRAM This block diagram illustrates the functional blocks of the NOV2221 device. Hi-PHYTM - Implements the physical interface to the optical transceiver and the serial to parallel and parallel to serial function. Framer - Implements the SONET/SDH frame processing. ATM Processor - Implements cell processing functions such as cell delineation, HEC verification and calculation etc. POS Processor - Implements packet processing functions such as flag detection and generation, FCS verification and calculation etc. FIFO - The memory cells where the cells/packets data is stored before processing (transmit path) and after processing (receive path). UTOPIA - Implements the interface functions between the PHY and the ATM layer (ATM mode). POS Interface - Implements the interface functions between the PHY and the Link layer (POS mode). TxData[31:0] TxAdd[4:0] TxSOC/P[3:0] TxD0+ LDCC Serial to Parallel Tx_STPA TxPrty TxCLK Tx POS Processor Rx POS Processor Rx Overhead Processor Tx_ERR UTOPIA Level 2/ POS Interface Tx_EOP Tx_MOD RxData[31:0] RxAdd[4:0] Rx ATM Cell Processor RxSOC/P[3:0] *RxEnb[3:0] RxClav/PRPAx4 Clock Synthesis Rx_RVAL RxPrty RxCLK Rx_ERR Rx_EOP Rx_MOD TMS *TRST TDI TDO ASDO ASCLK *ASSTB TCK JTAG Interface ASSI *INTR *DSTB *CS W/*R D[7:0] RLDCC 1-4 RLDCC 1-4 RSDCK 1-4 A[5:0] Microprocessor Interface Sec./Line DCC i/f TLDCK 1-4 RefCLK+ Rx SONET/ SDH Framer RSDCC 1-4 RxD0- Data & Clock Recovery Tx Overhead Processor TxClav/PTPAx4 PORT 0 TSDCC 1-4 RxD0+ Hi-PHY TSDCK 1-4 TLDCC 1-4 TxD0- Tx SONET/ SDH Framer Parallel to Serial *TxEnb[3:0] Tx ATM Cell Processor NOV2221 PRODUCT BRIEF 3. TYPICAL APPLICATION The figure below demonstrates connection of a NOV2221 to a single-port ATM Layer Device according to UTOPIA Level 2. Connection is performed using the Direct Status Indication mode, in which a dedicated RxClav and TxClav is used to provide direct indication of the status of the FIFOs of each port. Cell transmission is made to/from the PHY port. Receive and transmit channels work simultaneously and independently. This mode supports 16-bit data bus width. TxData[15:0] TxAdd[4:0] TxSOC *TxEnb TxClav TxPrty TxCLK TxD+/- Optical Tranceiver RxD+/- NOV2221 RxData[15:0] RxAdd[4:0] RxSOC *RxEnb RxClav RxPrty RxCLK ATM LAYER DEVICE