Half-Duplex,
i
Coupler
®
Isolated RS-485 Transceiver
ADM2483
Rev. B
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
RS-485 transceiver with electrical data isolation
Complies with ANSI TIA/EIA RS-485-A and ISO 8482: 1987(E)
500 kbps data rate
Slew rate-limited driver outputs
Low power operation: 2.5 mA max
Suitable for 5 V or 3 V operations (VDD1)
High common-mode transient immunity: >25 kV/μs
True fail-safe receiver inputs
Chatter-free power-up/power-down protection
256 nodes on bus
Thermal shutdown protection
Safety and regulatory approvals
UL recognition: 2500 Vrms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN EN 60747-5-2 (VDE 0884 Rev. 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
VIORM = 560 V peak
Operating temperature range: −40°C to +85°C
APPLICATIONS
Low power RS-485/RS-422 networks
Isolated interfaces
Building control networks
Multipoint data transmission systems
FUNCTIONAL BLOCK DIAGRAM
DE
V
DD1
GND
1
GND
2
V
DD2
TxD
PV
RxD
RE
GALVANIC ISOLATION
A
B
04736-001
ADM2483
Figure 1.
GENERAL DESCRIPTION
The ADM2483 differential bus transceiver is an integrated,
galvanically isolated component designed for bidirectional data
communication on balanced, multipoint bus transmission lines.
It complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E).
Using Analog Devices’ iCoupler technology, the ADM2483
combines a 3-channel isolator, a three-state differential line
driver, and a differential input receiver into a single package.
The logic side of the device is powered with either a 5 V or 3 V
supply, and the bus side uses a 5 V supply only.
The ADM2483 is slew-limited to reduce reflections with
improperly terminated transmission lines. The controlled slew
rate limits the data rate to 500 kbps. The device’s input impedance
is 96 kΩ, allowing up to 256 transceivers on the bus. Its driver
has an active-high enable feature. The driver differential outputs
and receiver differential inputs are connected internally to form
a differential I/O port. When the driver is disabled or when
VDD1 or VDD2 = 0 V, this imposes minimal loading on the bus.
An active-high receiver disable feature, which causes the receive
output to enter a high impedance state, is provided as well.
The receiver inputs have a true fail-safe feature that ensures a
logic-high receiver output level when the inputs are open or
shorted. This guarantees that the receiver outputs are in a
known state before communication begins and at the point
when communication ends.
Current limiting and thermal shutdown features protect against
output short circuits and bus contention situations that might
cause excessive power dissipation. The part is fully specified
over the industrial temperature range and is available in a
16-lead, wide body SOIC package.
ADM2483
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Package Characteristics ............................................................... 6
Regulatory Information............................................................... 6
Insulation and Safety-Related Specifications............................ 6
VDE 0884 Insulation Characteristics ........................................ 7
Pin Configuration and Function Descriptions............................. 8
Test Circuits....................................................................................... 9
Switching Characteristics .............................................................. 10
Typical Performance Characteristics ........................................... 11
Circuit Description......................................................................... 14
Electrical Isolation...................................................................... 14
Truth Tables................................................................................. 15
Power-Up/Power-Down Characteristics................................. 15
Thermal Shutdown .................................................................... 15
True Fail-Safe Receiver Inputs.................................................. 15
Magnetic Field Immunity.......................................................... 15
Applications Information .............................................................. 17
Power_Valid Input ..................................................................... 17
Isolated Power Supply Circuit .................................................. 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
3/05—Rev. A to Rev. B
Change to Features ........................................................................... 1
Change to Package Characteristics................................................. 6
Changes to Pin Function Descriptions.......................................... 8
Changes to Figure 9 and Figure 11............................................... 10
Change to Power_Valid Input Section......................................... 17
Changes to Figure 30...................................................................... 17
Changes to Ordering Guide .......................................................... 18
1/05—Rev. 0 to Rev. A
Changes to ESD maximum rating specification........................... 5
10/04—Revision 0: Initial Version
ADM2483
Rev. B | Page 3 of 20
SPECIFICATIONS
2.7 ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage, VOD 5 V R = ∞, see Figure 3
2.0 5 V R = 50 Ω (RS-422), see Figure 3
1.5 5 V R = 27 Ω (RS-485), see Figure 3
1.5 5 V
VTST = −7 V to +12 V, VDD1 ≥ 4.75,
see Figure 4
∆ |VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 3
Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 3
∆ |VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 3
Output Short-Circuit Current, VOUT = High −250 +250 mA −7 V ≤ VOUT ≤ +12 V
Output Short-Circuit Current, VOUT = Low −250 +250 mA −7 V ≤ VOUT ≤ +12 V
Logic Inputs
Input High Voltage 0.7 VDD1 V TxD, DE, RE, PV
Input Low Voltage 0.25 VDD1 V TxD, DE, RE, PV
CMOS Logic Input Current (TxD, DE, RE, PV) −10 +0.01 +10 µA TxD, DE, RE, PV = VDD1 or 0 V
RECEIVER
Differential Inputs
Differential Input Threshold Voltage, VTH −200 −125 −30 mV −7 V ≤ VCM ≤ +12 V
Input Hysteresis 20 mV −7 V ≤ VCM ≤ +12 V
Input Resistance (A, B) 96 150 kΩ −7 V ≤ VCM ≤ +12 V
Input Current (A, B) 0.125 mA VIN = +12 V
−0.1 mA VIN = −7 V
RxD Logic Output
Output High Voltage VDD1 − 0.1 V IOUT = 20 µA, VA − VB = 0.2 V
V
DD1 − 0.4 VDD1 − 0.2 V IOUT = 4 mA, VA − VB = 0.2 V
Output Low Voltage 0.1 V IOUT = −20 µA, VA − VB = −0.2 V
0.4 V IOUT = −4 mA, VA − VB = −0.2 V
Output Short-Circuit Current 7 85 mA VOUT = GND or VCC
Three-State Output Leakage Current ±1 µA 0.4 V ≤ VOUT ≤ 2.4 V
POWER SUPPLY CURRENT
Logic Side 2.5 mA 4.5 V ≤ VDD1 ≤ 5.5 V, outputs unloaded,
RE = 0 V
1.3 mA
2.7 V ≤ VDD1 ≤ 3.3 V, outputs unloaded,
RE = 0 V
Bus Side 2.0 mA Outputs unloaded, DE = 5 V
1.7 mA Outputs unloaded, DE = 0 V
COMMON-MODE TRANSIENT IMMUNITY1 25 kV/µs
TxD = VDD1 or 0 V, VCM = 1 kV,
transient magnitude = 800 V
1 Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation.
VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The
common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ADM2483
Rev. B | Page 4 of 20
TIMING SPECIFICATIONS
2.7 ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 500 kbps
Propagation Delay, tPLH, tPHL 250 620 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9
Skew, tSKEW 40 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9
Rise/Fall Time, tR, tF 200 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9
Enable Time 1050 ns RL = 500 Ω, CL = 100 pF, see Figure 6 and Figure 11
Disable Time 1050 ns RL = 500 Ω, CL = 15 pF, see Figure 6 and Figure 11
RECEIVER
Propagation Delay, tPLH, tPHL 400 1050 ns CL = 15 pF, see Figure 7 and Figure 10
Differential Skew, tSKEW 250 ns CL = 15 pF, see Figure 7 and Figure 10
Enable Time 25 70 ns RL = 1 kΩ, CL = 15 pF, see Figure 8 and Figure 12
Disable Time 40 70 ns RL = 1 kΩ, CL = 15 pF, see Figure 8 and Figure 12
POWER VALID INPUT
Enable Time 1 2 µs
Disable Time 3 5 µs
ADM2483
Rev. B | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 3.
Parameter Rating
VDD1 −0.5 V to +7 V
VDD2 −0.5 V to +6 V
Digital Input Voltage (DE, RE, TxD) −0.5 V to VDD1 + 0.5 V
Digital Output Voltage
RxD −0.5 V to VDD1 + 0.5 V
Driver Output/Receiver Input Voltage −9 V to +14 V
ESD Rating: Contact (Human Body
Model) (A, B Pins)
±2 kV
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −55°C to +150°C
Average Output Current per Pin −35 mA to +35 mA
θJA Thermal Impedance 73°C/W
Lead Temperature
Soldering (10 sec) 260°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
ADM2483
Rev. B | Page 6 of 20
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-Output)1 R
I-O 1012 Ω
Capacitance (Input-Output)1 C
I-O 3 pF f = 1 MHz
Input Capacitance2 C
I 4 pF
Input IC Junction-to-Case Thermal Resistance θJCI 33 °C/W
Thermocouple located at center of package
underside
Output IC Junction-to-Case Thermal Resistance θJCO 28 °C/W
Thermocouple located at center of package
underside
1 Device considered a 2-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADM2483 has been approved by the following organizations:
Table 5.
UL1 CSA VDE2
Recognized under 1577 component
recognition program
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN EN 60747-5-2
(VDE 0884 Part 2): 2003-01
Complies with DIN EN 60747-5-2
(VDE 0884 Part 2): 2003-01,
DIN EN 60950 (VDE 0805): 2001-12;
EN 60950:2000
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL1577, each ADM2483 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).
2 In accordance with VDE 0884, each ADM2483 is proof tested by applying an insulation test voltage ≥1050 VPEAK for 1 sec (partial discharge detection limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.45 min mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.1 min mm Measured from input terminals to output
terminals, shortest distance along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (Table 1 in DIN VDE 0110,1/89)
ADM2483
Rev. B | Page 7 of 20
VDE 0884 INSULATION CHARACTERISTICS
This isolator is suitable for basic electrical isolation only within this safety limit data. Maintenance of this safety data shall be ensured by
means of protective circuits.
An asterisk (*) on the physical package denotes VDE 0884 approval for 560 V peak working voltage.
Table 7.
Description Symbol Characteristic Unit
Installation Classification per DIN VDE 0110 for Rated Mains Voltage
≤150 V rms I to IV
≤300 V rms I to III
≤400 V rms I to II
Climatic Classification 40/85/21
Pollution Degree (Table 1 in DIN VDE 0110) 2
Maximum Working Insulation Voltage VIORM 560 VPEAK
Input to Output test Voltage, Method b1 VPR 1050 VPEAK
VIORM × 1.875 = VPR, 100% Production Tested
tm = 1 sec, Partial Discharge <5 pC
Input-to-Output Test Voltage, Method a
(After Environmental Tests, Subgroup 1)
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge <5 pC 896 VPEAK
(After Input and/or Safety Test, Subgroup 2/3)
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge <5 pC VPR 672 VPEAK
Highest Allowable Overvoltage
(Transient Overvoltage, tTR = 10 sec) VTR 4000 VPEAK
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure. See Figure 23.)
Case Temperature TS 150 °C
Input Current IS, INPUT 265 mA
Output Current IS, OUTPUT 335 mA
Insulation Resistance at TS, VIO = 500 V RS >109 Ω
ADM2483
Rev. B | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04736-002
NC = NO CONNECT
ADM2483
TOP VIEW
(Not to Scale)
VDD1 1VDD2
16
GND112GND21
15
RxD 3NC14
RE 4B
13
DE 5A12
TxD 6NC11
PV 7NC
10
GND118GND21
9
1PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED.
EITHER OR BOTH MAY BE USED FOR GND1.
PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED.
EITHER OR BOTH MAY BE USED FOR GND2.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Power Supply (Logic Side).
2, 8 GND1 Ground (Logic Side).
3 RxD
Receiver Output Data. When enabled, if (A − B) ≥ −30 mV, then RxD = high. If (A − B) ≤ −200 mV, then
RxD = low. This is a tristate output when the receiver is disabled, that is, when RE is driven high.
4 RE Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver, and
driving it high disables the receiver.
5 DE Driver Enable Input. Driving the input high enables the driver, and driving it low disables the driver.
6 TxD Transmit Data Input. Data to be transmitted by the driver is applied to this input.
7 PV Power_Valid. Used during power-up and power-down. See the Applications Information section.
9, 15 GND2 Ground (Bus Side).
10, 11, 14 NC No Connect.
12 A Noninverting Driver Output/Receiver Input. When the driver is disabled, or when VDD1 or VDD2 is
powered down, Pin A is put into a high impedance state to avoid overloading the bus.
13 B Inverting Driver Output/Receiver Input. When the driver is disabled, or when VDD1 or VDD2 is powered
down, Pin B is put into a high impedance state to avoid overloading the bus.
16 VDD2 Power Supply (Bus Side).
ADM2483
Rev. B | Page 9 of 20
TEST CIRCUITS
04736-003
V
OD
V
OC
R
R
Figure 3. Driver Voltage Measurement
04736-004
V
OD3
375Ω
375Ω
60ΩV
TEST
Figure 4. Driver Voltage Measurement
A
B
R
LDIFF
04736-005
C
L1
C
L2
Figure 5. Driver Propagation Delay
A
S1 RL
0V OR 3V
B
04736-006
DE IN
DE S2
VCC
CL
VOUT
Figure 6. Driver Enable/Disable
A
04736-007
BV
OUT
C
L
RE
Figure 7. Receiver Propagation Delay
C
L
V
OUT
R
L
S2
V
CC
+1.5V
04736-008
S1
–1.5V
RE IN
RE
Figure 8. Receiver Enable/Disable
ADM2483
Rev. B | Page 10 of 20
SWITCHING CHARACTERISTICS
04736-009
t
PLH
V
DD1
0V
B
A
V
OH
A, B
V
OL
0.5V
DD1
0.5V
DD1
t
SKEW
= |
t
PLH
–
t
PHL
|
t
F
10% POINT 10% POINT
90% POINT
90% POINT
1/2VO
t
R
t
PHL
VO
Figure 9. Driver Propagation Delay, Rise/Fall Timing
04736-010
V
OH
0V0V
1.5V1.5V
V
OL
A
– B
RxD
t
PLH
t
PHL
t
SKEW
= |
t
PLH
–
t
PHL
|
Figure 10. Receiver Propagation Delay
04736-011
DE
2.3V
0.5V
DD1
V
OH
0V
V
OL
V
OH
– 0.5V
0.7V
DD1
0.3V
DD1
V
OL
+ 0.5V
0.5V
DD1
2.3V
A, B
A, B
t
ZL
t
ZH
t
LZ
t
HZ
Figure 11. Driver Enable/Disable Timing
04736-012
V
OH
V
OL
V
OH
– 0.5V
0.7V
DD1
0.3V
DD1
V
OL
+ 0.5V
RE
RxD
RxD
0V
O/P LOW
O/P HIGH
1.5V
0.5V
DD1
1.5V
tZL
tZH
0.5V
DD1
tLZ
tHZ
Figure 12. Receiver Enable/Disable Timing
ADM2483
Rev. B | Page 11 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
1.6
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
8525–40
04736-038
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
I
DD1
_RCVR_ENABLE @ 5.5V
I
DD2
_DE_ENABLE @ 5.5V
Figure 13. Unloaded Supply Current vs. Temperature
120
100
80
60
40
20
00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
04736-014
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 14. Output Current vs. Driver Output Low Voltage
–10
–30
–50
–70
–90
–1100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
04736-015
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 15. Output Current vs. Driver Output High Voltage
0.32
0.30
0.28
0.26
0.24
0.22
0.20
–40 80655035205–10–25
04736-031
TEMPERATURE (
°
C)
OUTPUT VOLTAGE (V)
Figure 16. Receiver Output Low Voltage vs. Temperature, I = –4mA
4.78
4.76
4.74
4.72
4.70
4.68
4.66
–40 80655035205–10–25
04736-032
TEMPERATURE (
°
C)
OUTPUT VOLTAGE (V)
Figure 17. Receiver Output High Voltage vs. Temperature, I = 4 mA
90
0
10
20
30
40
50
60
70
80
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
04736-013
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
Figure 18. Driver Output Current vs. Differential Output Voltage
ADM2483
Rev. B | Page 12 of 20
460
440
420
400
380
360
340 8525–40
04736-034
TEMPERATURE (
°
C)
TIME (ns)
t
P_ALH
@
V
DD1
= V
DD2
= 5.0V
t
P_AHL
@
V
DD1
= V
DD2
= 5.0V
t
P_BLH
@
V
DD1
= V
DD2
= 5.0V
t
P_BHL
@
V
DD1
= V
DD2
= 5.0V
Figure 19. Driver Propagation Delay vs. Temperature
800
0
100
200
300
400
500
600
700
8525–40
04736-035
TEMPERATURE (
°
C)
TIME (ns)
R
CVR
PROP
HL/V
DD1
= V
DD2
= 5.0V
R
CVR
PROP
LH/V
DD1
= V
DD2
= 5.0V
Figure 20. Receiver Propagation Delay vs. Temperature
04736-022
CH1 5.00V CH2 1.00V
CH3 1.00V CH4 5.00V M200ns A CH1 3.10V
1
2
4
T 1.33600µs
Figure 21. Driver/Receiver Propagation Delay High to Low
04736-023
CH1 5.00V CH2 1.00V
CH3 1.00V CH4 5.00V M200ns A CH1 3.10V
1
2
4
T 360.000ns
Figure 22. Driver/Receiver Propagation Delay Low to High
ADM2483
Rev. B | Page 13 of 20
350
300
250
200
150
100
50
00 50 100 150 200
04736-024
CASE TEMPERATURE (°C)
SAFETY-LIMITING CURRENT (mA)
BUS SIDE
LOGIC SIDE
Figure 23. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per VDE 0884
0
–30
–25
–20
–15
–10
–5
5.03.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8
04736-036
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 24. Output Current vs. Receiver Output High Voltage
35
0
5
10
15
20
25
30
2.252.001.751.501.251.000.750.500.250
04736-037
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 25. Output Current vs. Receiver Output Low Voltage
ADM2483
Rev. B | Page 14 of 20
CIRCUIT DESCRIPTION
ELECTRICAL ISOLATION
In the ADM2483, electrical isolation is implemented on the
logic side of the interface. Therefore, the part has two main
sections: a digital isolation section and a transceiver section (see
Figure 26). Driver input and data enable signals, applied to the
TxD and DE pins, respectively, and referenced to logic ground
(GND1), are coupled across an isolation barrier to appear at the
transceiver section referenced to isolated ground (GND2).
Similarly, the receiver output, referenced to isolated ground in
the transceiver section, is coupled across the isolation barrier to
appear at the RxD pin referenced to logic ground.
iCoupler Technology
The digital signals are transmitted across the isolation barrier
using iCoupler technology. This technique uses chip-scale
transformer windings to couple the digital signals magnetically
from one side of the barrier to the other. Digital inputs are
encoded into waveforms that are capable of exciting the
primary transformer winding. At the secondary winding, the
induced waveforms are then decoded into the binary value that
was originally transmitted.
04736-025
RE
TxD DECODEENCODE
DE DECODEENCODE
RxD DECODEENCODE
ISOLATION
BARRIER
DIGITAL ISOLATION TRANSCEIVER
D
R
A
VDD1 VDD2
GND1GND2
B
Figure 26. ADM2483 Digital Isolation and Transceiver Sections
ADM2483
Rev. B | Page 15 of 20
TRUTH TABLES
The following truth tables use these abbreviations:
Letter Description
H High level
L Low level
X Irrelevant
Z High impedance (off)
NC Disconnected
Table 9. Transmitting
Supply Status Inputs Outputs
VDD1 V
DD2 DE TxD A B
On On H H H L
On On H L L H
On On L X Z Z
On Off X X Z Z
Off On X X Z Z
Off Off X X Z Z
Table 10. Receiving
Supply Status Inputs Outputs
VDD1 V
DD2 A − B (V) RE RxD
On On >−0.03 L or NC H
On On <−0.2 L or NC L
On On
−0.2 < A − B <
−0.03 L or NC Indeterminate
On On Inputs open L or NC H
On On X H Z
On Off X L or NC H
Off On X L or NC H
Off Off X L or NC L
POWER-UP/POWER-DOWN CHARACTERISTICS
The power-up/power-down characteristics of the ADM2483 are
in accordance with the supply thresholds shown in Table 11.
Upon power-up, the ADM2483 output signals (A, B, and RxD)
reach their correct state once both supplies exceed their
thresholds. Upon power-down, the ADM2483 output signals
retain their correct state until at least one of the supplies drops
below its power-down threshold. When the VDD1 power-down
threshold is crossed, the ADM2483 output signals reach their
unpowered states within 4 µs.
Table 11. Power-Up/Power-Down Thresholds
Supply Transition Threshold (V)
VDD1 Power-up 2.0
VDD1 Power-down 1.0
VDD2 Power-up 3.3
VDD2 Power-down 2.4
THERMAL SHUTDOWN
The ADM2483 contains thermal shutdown circuitry that
protects the part from excessive power dissipation during fault
conditions. Shorting the driver outputs to a low impedance
source can result in high driver currents. The thermal sensing
circuitry detects the increase in die temperature under this
condition and disables the driver outputs. This circuitry is
designed to disable the driver outputs when a die temperature
of 150°C is reached. As the device cools, the drivers are re-enabled
at a temperature of 140°C.
TRUE FAIL-SAFE RECEIVER INPUTS
The receiver inputs have a true fail-safe feature, which ensures
that the receiver output is high when the inputs are open or
shorted. During line-idle conditions, when no driver on the bus
is enabled, the voltage across a terminating resistance at the
receiver input decays to 0 V. With traditional transceivers,
receiver input thresholds specified between −200 mV and
+200 mV mean that external bias resistors are required on the
A and B pins to ensure that the receiver outputs are in a known
state. The true fail-safe receiver input feature eliminates the
need for bias resistors by specifying the receiver input threshold
between −30 mV and −200 mV. The guaranteed negative
threshold means that when the voltage between A and B decays
to 0 V, the receiver output is guaranteed to be high.
MAGNETIC FIELD IMMUNITY
Because iCouplers use a coreless technology, no magnetic
components are present, and the problem of magnetic
saturation of the core material does not exist. Therefore,
iCouplers have essentially infinite dc field immunity. The
analysis that follows defines the conditions under which this
might occur. The ADM2483’s 3 V operating condition is
examined because it represents the most susceptible mode of
operation.
The limitation on the iCoupler’s ac magnetic field immunity is
set by the condition in which the induced error voltage in the
receiving coil (the bottom coil in this case) is made sufficiently
large, either to falsely set or reset the decoder. The voltage
induced across the bottom coil is given by
;π 2
n
r
dt
d
V∑
⎟
⎠
⎞
⎜
⎝
⎛β−
= Nn ,...,2,1
=
where if the pulses at the transformer output are greater than
1.0 V in amplitude:
β
= magnetic flux density (gauss)
N
= number of turns in receiving coil
rn = radius of nth turn in receiving coil (cm)
The decoder has a sensing threshold of about 0.5 V; therefore,
there is a 0.5 V margin in which induced voltages can be
tolerated.
ADM2483
Rev. B | Page 16 of 20
Given the geometry of the receiving coil and an imposed
requirement that the induced voltage is, at most, 50% of the
0.5 V margin at the decoder, a maximum allowable magnetic
field is calculated, as shown in Figure 27.
100.000
10.000
1.000
0.100
0.010
0.0011k 10k 100k 1M 10M 100M
04736-027
MAGNETIC FIELD FREQUENCY (Hz)
MAXIMUM ALLOWABLE MAGNETIC
FLUX DENSITY (kGAUSS)
Figure 27. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kGauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse and
is the worst-case polarity, it reduces the received pulse from
>1.0 V to 0.75 V. This is well above the 0.5 V sensing threshold
of the decoder.
These magnetic flux density values are shown in Figure 28,
using more familiar quantities such as maximum allowable
current flow, at given distances away from the ADM2483
transformers.
1000.00
100.00
0.10
1.00
10.00
0.011k 10k 100k 1M 10M 100M
04736-028
MAGNETIC FIELD FREQUENCY (Hz)
MAXIMUM ALLOWABLE CURRENT (kA)
DISTANCE = 1m
DISTANCE = 5mm
DISTANCE = 100mm
Figure 28. Maximum Allowable Current for Various
Current-to-ADM2483 Spacings
At combinations of strong magnetic field and high frequency,
any loops formed by printed circuit board traces could induce
large enough error voltages to trigger the thresholds of
succeeding circuitry. To avoid this possibility, care should be
taken in the layout of such traces.
ADM2483
Rev. B | Page 17 of 20
APPLICATIONS INFORMATION
POWER_VALID INPUT
To avoid chatter on the A and B outputs caused by slow power-
up and power-down transients on VDD1 (>100 µs/V), the
ADM2483 features a power_valid (PV) digital input. This pin
should be driven low until VDD1 exceeds 2.0 V. When VDD1 is
greater than 2.0 V, the pin should be driven high. Conversely,
upon power-down, the PV should be driven low before VDD1
reaches 2.0 V.
The power_valid input can be driven, for example, by the
output of a system reset circuit such as the ADM809Z, which
has a threshold voltage of 2.32 V.
04736-029
VDD1 2.32V
tPOR
2.0V 2.32V 2.0V
RESET
RESET
ADM809Z ADM2483
VDD1
PV
GND1
V
DD1
Figure 29. Driving PV with ADM809Z
ISOLATED POWER SUPPLY CIRCUIT
The ADM2483 requires isolated power capable of 5 V at
100 mA to be supplied between the VDD2 and GND2 pins. If no
suitable integrated power supply is available, a discrete circuit,
such as the one in Figure 30, can be used. A center-tapped
transformer provides electrical isolation. The primary winding
is excited with a pair of square waveforms that are 180° out of
phase with each other. A pair of Schottky diodes and a
smoothing capacitor are used to create a rectified signal from
the secondary winding. The ADP667 linear voltage regulator
provides a regulated power supply to the ADM2483’s bus-side
circuitry.
To create the pair of square waves, a D-type flip-flop with
complementary Q/Q outputs is used. The flip-flop can be
connected so that output Q follows the clock input signal. If no
local clock signal is available, a simple digital oscillator can be
implemented with a hex-inverting Schmitt trigger and a resistor
and capacitor. In this case, values of 3.9 kΩ and 1 nF generate a
364 kHz square wave. A pair of discrete NMOS transistors,
switched by the Q/Q flip-flop outputs, conduct current through
the center tap of the primary transformer, winding in an
alternating fashion.
04736-030
3.9kΩ
100nF
1nF 74HC14
V
CC
74HC74A
PR CLR
DQ
CLK Q
BS107A
BS107A
V
CC
ISOLATION
BARRIER
SD103C
22µF
SD103C
78253
100nF
V
CC
IN OUT 5V
SET SHDNGND
ADP667
V
DD1
V
DD2
GND
1
GND
2
ADM2483
V
CC
Figure 30. Isolated Power Supply Circuit
ADM2483
Rev. B | Page 18 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AA
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
16 9
8
1
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
10.50 (0.4134)
10.10 (0.3976)
8°
0°
0.75 (0.0295)
0.25 (0.0098) × 45°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COPLANARITY
0.10
Figure 31. 16-Lead Standard Small Outline Package [SOIC]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model Data Rate (kbps) Temperature Range Package Description Package Option
ADM2483BRW 500 −40°C to +85°C 16-Lead, Wide Body SOIC RW-16
ADM2483BRW-REEL1 500 −40°C to +85°C 16-Lead, Wide Body SOIC RW-16
ADM2483BRWZ2 500 −40°C to +85°C 16-Lead, Wide Body SOIC RW-16
ADM2483BRWZ-REEL1, 2 500 −40°C to +85°C 16-Lead, Wide Body SOIC RW-16
1 A -REEL suffix designates a 13-inch (1,000 units) tape-and-reel option.
2 Z = Pb-free part.
ADM2483
Rev. B | Page 19 of 20
NOTES
ADM2483
Rev. B | Page 20 of 20
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04736–0–3/05(B)
