Half-Duplex, iCoupler(R) Isolated RS-485 Transceiver ADM2483 VDD1 VDD2 ADM2483 DE TxD PV RxD A B 04736-001 RS-485 transceiver with electrical data isolation Complies with ANSI TIA/EIA RS-485-A and ISO 8482: 1987(E) 500 kbps data rate Slew rate-limited driver outputs Low power operation: 2.5 mA max Suitable for 5 V or 3 V operations (VDD1) High common-mode transient immunity: >25 kV/s True fail-safe receiver inputs Chatter-free power-up/power-down protection 256 nodes on bus Thermal shutdown protection Safety and regulatory approvals UL recognition: 2500 Vrms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN EN 60747-5-2 (VDE 0884 Rev. 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 VIORM = 560 V peak Operating temperature range: -40C to +85C FUNCTIONAL BLOCK DIAGRAM GALVANIC ISOLATION FEATURES RE GND1 GND2 Figure 1. APPLICATIONS Low power RS-485/RS-422 networks Isolated interfaces Building control networks Multipoint data transmission systems GENERAL DESCRIPTION The ADM2483 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on balanced, multipoint bus transmission lines. It complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E). Using Analog Devices' iCoupler technology, the ADM2483 combines a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. The logic side of the device is powered with either a 5 V or 3 V supply, and the bus side uses a 5 V supply only. The ADM2483 is slew-limited to reduce reflections with improperly terminated transmission lines. The controlled slew rate limits the data rate to 500 kbps. The device's input impedance is 96 k, allowing up to 256 transceivers on the bus. Its driver has an active-high enable feature. The driver differential outputs and receiver differential inputs are connected internally to form a differential I/O port. When the driver is disabled or when VDD1 or VDD2 = 0 V, this imposes minimal loading on the bus. An active-high receiver disable feature, which causes the receive output to enter a high impedance state, is provided as well. The receiver inputs have a true fail-safe feature that ensures a logic-high receiver output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and at the point when communication ends. Current limiting and thermal shutdown features protect against output short circuits and bus contention situations that might cause excessive power dissipation. The part is fully specified over the industrial temperature range and is available in a 16-lead, wide body SOIC package. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. ADM2483 TABLE OF CONTENTS Specifications..................................................................................... 3 Circuit Description......................................................................... 14 Timing Specifications....................................................................... 4 Electrical Isolation...................................................................... 14 Absolute Maximum Ratings............................................................ 5 Truth Tables................................................................................. 15 ESD Caution.................................................................................. 5 Power-Up/Power-Down Characteristics................................. 15 Package Characteristics ............................................................... 6 Thermal Shutdown .................................................................... 15 Regulatory Information............................................................... 6 True Fail-Safe Receiver Inputs .................................................. 15 Insulation and Safety-Related Specifications............................ 6 Magnetic Field Immunity.......................................................... 15 VDE 0884 Insulation Characteristics ........................................ 7 Applications Information .............................................................. 17 Pin Configuration and Function Descriptions............................. 8 Power_Valid Input ..................................................................... 17 Test Circuits....................................................................................... 9 Isolated Power Supply Circuit .................................................. 17 Switching Characteristics .............................................................. 10 Outline Dimensions ....................................................................... 18 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 18 REVISION HISTORY 3/05--Rev. A to Rev. B Change to Features ........................................................................... 1 Change to Package Characteristics................................................. 6 Changes to Pin Function Descriptions.......................................... 8 Changes to Figure 9 and Figure 11............................................... 10 Change to Power_Valid Input Section......................................... 17 Changes to Figure 30...................................................................... 17 Changes to Ordering Guide .......................................................... 18 1/05--Rev. 0 to Rev. A Changes to ESD maximum rating specification........................... 5 10/04--Revision 0: Initial Version Rev. B | Page 2 of 20 ADM2483 SPECIFICATIONS 2.7 VDD1 5.5 V, 4.75 V VDD2 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DRIVER Differential Outputs Differential Output Voltage, VOD |VOD| for Complementary Output States Common-Mode Output Voltage, VOC |VOC| for Complementary Output States Output Short-Circuit Current, VOUT = High Output Short-Circuit Current, VOUT = Low Logic Inputs Input High Voltage Input Low Voltage CMOS Logic Input Current (TxD, DE, RE, PV) RECEIVER Differential Inputs Differential Input Threshold Voltage, VTH Input Hysteresis Input Resistance (A, B) Input Current (A, B) RxD Logic Output Output High Voltage Min Max Unit Test Conditions/Comments 2.0 1.5 1.5 5 5 5 5 V V V V -250 -250 0.2 3 0.2 +250 +250 V V V mA mA R = , see Figure 3 R = 50 (RS-422), see Figure 3 R = 27 (RS-485), see Figure 3 VTST = -7 V to +12 V, VDD1 4.75, see Figure 4 R = 27 or 50 , see Figure 3 R = 27 or 50 , see Figure 3 R = 27 or 50 , see Figure 3 -7 V VOUT +12 V -7 V VOUT +12 V 0.7 VDD1 -10 +0.01 -200 -125 20 150 96 7 Bus Side COMMON-MODE TRANSIENT IMMUNITY1 1 V 0.25 VDD1 V +10 A TxD, DE, RE, PV TxD, DE, RE, PV TxD, DE, RE, PV = VDD1 or 0 V -30 0.125 -0.1 mV mV k mA mA -7 V VCM +12 V -7 V VCM +12 V -7 V VCM +12 V VIN = +12 V VIN = -7 V 0.1 0.4 85 1 V V V V mA A IOUT = 20 A, VA - VB = 0.2 V IOUT = 4 mA, VA - VB = 0.2 V IOUT = -20 A, VA - VB = -0.2 V IOUT = -4 mA, VA - VB = -0.2 V VOUT = GND or VCC 0.4 V VOUT 2.4 V 2.5 mA 1.3 mA 2.0 1.7 mA mA kV/s 4.5 V VDD1 5.5 V, outputs unloaded, RE = 0 V 2.7 V VDD1 3.3 V, outputs unloaded, RE = 0 V Outputs unloaded, DE = 5 V Outputs unloaded, DE = 0 V TxD = VDD1 or 0 V, VCM = 1 kV, transient magnitude = 800 V VDD1 - 0.1 VDD1 - 0.4 VDD1 - 0.2 Output Low Voltage Output Short-Circuit Current Three-State Output Leakage Current POWER SUPPLY CURRENT Logic Side Typ 25 Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. B | Page 3 of 20 ADM2483 TIMING SPECIFICATIONS 2.7 VDD1 5.5 V, 4.75 V VDD2 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DRIVER Maximum Data Rate Propagation Delay, tPLH, tPHL Skew, tSKEW Rise/Fall Time, tR, tF Enable Time Disable Time RECEIVER Propagation Delay, tPLH, tPHL Differential Skew, tSKEW Enable Time Disable Time POWER VALID INPUT Enable Time Disable Time Min Typ Max Unit Test Conditions/Comments 620 40 600 1050 1050 kbps ns ns ns ns ns RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 5 and Figure 9 RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 5 and Figure 9 RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 5 and Figure 9 RL = 500 , CL = 100 pF, see Figure 6 and Figure 11 RL = 500 , CL = 15 pF, see Figure 6 and Figure 11 25 40 1050 250 70 70 ns ns ns ns CL = 15 pF, see Figure 7 and Figure 10 CL = 15 pF, see Figure 7 and Figure 10 RL = 1 k, CL = 15 pF, see Figure 8 and Figure 12 RL = 1 k, CL = 15 pF, see Figure 8 and Figure 12 1 3 2 5 s s 500 250 200 400 Rev. B | Page 4 of 20 ADM2483 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. All voltages are relative to their respective ground. Table 3. Parameter VDD1 VDD2 Digital Input Voltage (DE, RE, TxD) Digital Output Voltage RxD Driver Output/Receiver Input Voltage ESD Rating: Contact (Human Body Model) (A, B Pins) Operating Temperature Range Storage Temperature Range Average Output Current per Pin JA Thermal Impedance Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating -0.5 V to +7 V -0.5 V to +6 V -0.5 V to VDD1 + 0.5 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -0.5 V to VDD1 + 0.5 V -9 V to +14 V 2 kV -40C to +85C -55C to +150C -35 mA to +35 mA 73C/W 260C 215C 220C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 5 of 20 ADM2483 PACKAGE CHARACTERISTICS Table 4. Parameter Resistance (Input-Output)1 Capacitance (Input-Output)1 Input Capacitance2 Input IC Junction-to-Case Thermal Resistance Symbol RI-O CI-O CI JCI Output IC Junction-to-Case Thermal Resistance JCO 1 2 Min Typ 1012 3 4 33 Max 28 Unit pF pF C/W C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside Thermocouple located at center of package underside Device considered a 2-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADM2483 has been approved by the following organizations: Table 5. UL1 Recognized under 1577 component recognition program CSA Approved under CSA Component Acceptance Notice #5A File E214100 File 205078 1 2 VDE2 Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000 File 2471900-4880-0001 In accordance with UL1577, each ADM2483 is proof tested by applying an insulation test voltage 3000 V rms for 1 sec (current leakage detection limit = 5 A). In accordance with VDE 0884, each ADM2483 is proof tested by applying an insulation test voltage 1050 VPEAK for 1 sec (partial discharge detection limit = 5 pC). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 2500 7.45 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 8.1 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >175 IIIa mm V Rev. B | Page 6 of 20 Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (Table 1 in DIN VDE 0110,1/89) ADM2483 VDE 0884 INSULATION CHARACTERISTICS This isolator is suitable for basic electrical isolation only within this safety limit data. Maintenance of this safety data shall be ensured by means of protective circuits. An asterisk (*) on the physical package denotes VDE 0884 approval for 560 V peak working voltage. Table 7. Description Installation Classification per DIN VDE 0110 for Rated Mains Voltage 150 V rms 300 V rms 400 V rms Climatic Classification Pollution Degree (Table 1 in DIN VDE 0110) Maximum Working Insulation Voltage Input to Output test Voltage, Method b1 VIORM x 1.875 = VPR, 100% Production Tested tm = 1 sec, Partial Discharge <5 pC Input-to-Output Test Voltage, Method a (After Environmental Tests, Subgroup 1) VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge <5 pC (After Input and/or Safety Test, Subgroup 2/3) VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge <5 pC Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure. See Figure 23.) Case Temperature Input Current Output Current Insulation Resistance at TS, VIO = 500 V Rev. B | Page 7 of 20 Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/85/21 2 560 1050 VPEAK VPEAK 896 VPEAK VPR 672 VPEAK VTR 4000 VPEAK TS IS, INPUT IS, OUTPUT RS 150 265 335 >109 C mA mA ADM2483 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 16 VDD2 GND11 2 15 GND21 RxD 3 14 NC RE 4 ADM2483 13 B TOP VIEW DE 5 (Not to Scale) 12 A TxD 6 11 NC PV 7 10 NC GND11 8 9 GND21 NC = NO CONNECT 2 AND PIN 8 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR GND1. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR GND2. 04736-002 1 PIN Figure 2. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2, 8 3 Mnemonic VDD1 GND1 RxD 4 RE 5 6 7 9, 15 10, 11, 14 12 DE TxD PV GND2 NC A 13 B 16 VDD2 Description Power Supply (Logic Side). Ground (Logic Side). Receiver Output Data. When enabled, if (A - B) -30 mV, then RxD = high. If (A - B) -200 mV, then RxD = low. This is a tristate output when the receiver is disabled, that is, when RE is driven high. Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver, and driving it high disables the receiver. Driver Enable Input. Driving the input high enables the driver, and driving it low disables the driver. Transmit Data Input. Data to be transmitted by the driver is applied to this input. Power_Valid. Used during power-up and power-down. See the Applications Information section. Ground (Bus Side). No Connect. Noninverting Driver Output/Receiver Input. When the driver is disabled, or when VDD1 or VDD2 is powered down, Pin A is put into a high impedance state to avoid overloading the bus. Inverting Driver Output/Receiver Input. When the driver is disabled, or when VDD1 or VDD2 is powered down, Pin B is put into a high impedance state to avoid overloading the bus. Power Supply (Bus Side). Rev. B | Page 8 of 20 ADM2483 TEST CIRCUITS VCC A R RL 0V OR 3V 04736-003 VOC R S2 S1 DE 04736-006 VOD CL VOUT B DE IN Figure 6. Driver Enable/Disable Figure 3. Driver Voltage Measurement 375 A B 375 VOUT RE CL Figure 4. Driver Voltage Measurement Figure 7. Receiver Propagation Delay VCC +1.5V S1 A CL1 S2 CL2 CL VOUT 04736-005 B RL -1.5V RE RLDIFF RE IN Figure 5. Driver Propagation Delay Figure 8. Receiver Enable/Disable Rev. B | Page 9 of 20 04736-008 60 04736-007 VTEST 04736-004 VOD3 ADM2483 SWITCHING CHARACTERISTICS VDD1 0.7VDD1 0.5VDD1 0.5VDD1 DE 0V tPLH B 0.5VDD1 0.5VDD1 tPHL 0.3VDD1 tZL 1/2VO tLZ VO 2.3V A, B A VOL + 0.5V tSKEW = |tPLH - tPHL| VOL tZH 90% POINT 90% POINT tHZ VOH A, B 10% POINT 10% POINT tR 2.3V 04736-009 VOL VOH - 0.5V A, B tF 0V Figure 9. Driver Propagation Delay, Rise/Fall Timing 04736-011 VOH Figure 11. Driver Enable/Disable Timing 0.7VDD1 RE 0.5VDD1 0.5VDD1 0.3VDD1 0V 0V tPLH tPHL tZL tLZ 1.5V RxD VOL + 0.5V O/P LOW tZH VOH VOL tHZ O/P HIGH 1.5V tSKEW = |tPLH - tPHL| 1.5V VOL 04736-010 RxD VOH - 0.5V RxD 1.5V 0V Figure 10. Receiver Propagation Delay Figure 12. Receiver Enable/Disable Timing Rev. B | Page 10 of 20 VOH 04736-012 A-B ADM2483 TYPICAL PERFORMANCE CHARACTERISTICS 0.32 1.6 IDD1_RCVR_ENABLE @ 5.5V 0.30 1.2 OUTPUT VOLTAGE (V) SUPPLY CURRENT (mA) 1.4 1.0 0.8 IDD2_DE_ENABLE @ 5.5V 0.6 0.28 0.26 0.24 0.4 04736-038 0 -40 25 TEMPERATURE (C) 0.20 -40 85 -25 -10 5 20 35 TEMPERATURE (C) 50 65 80 Figure 16. Receiver Output Low Voltage vs. Temperature, I = -4mA Figure 13. Unloaded Supply Current vs. Temperature 120 4.78 100 4.76 OUTPUT VOLTAGE (V) 80 60 40 20 4.74 4.72 4.70 04736-014 4.68 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5 4.66 -40 5.0 Figure 14. Output Current vs. Driver Output Low Voltage 04736-032 OUTPUT CURRENT (mA) 04736-031 0.22 0.2 -25 -10 5 20 35 TEMPERATURE (C) 50 65 80 Figure 17. Receiver Output High Voltage vs. Temperature, I = 4 mA 90 -30 -50 -70 -90 -110 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5 70 60 50 40 30 20 04736-013 DRIVER OUTPUT CURRENT (mA) 80 04736-015 OUTPUT CURRENT (mA) -10 10 0 0 5.0 Figure 15. Output Current vs. Driver Output High Voltage 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 DIFFERENTIAL OUTPUT VOLTAGE (V) 4.5 5.0 Figure 18. Driver Output Current vs. Differential Output Voltage Rev. B | Page 11 of 20 ADM2483 460 tP_BLH @ VDD1 = VDD2 = 5.0V 440 1 tP_AHL @ VDD1 = VDD2 = 5.0V TIME (ns) 420 400 tP_BHL @ VDD1 = VDD2 = 5.0V 380 tP_ALH @ VDD1 = VDD2 = 5.0V 04736-034 340 -40 25 TEMPERATURE (C) 4 CH1 5.00V CH3 1.00V 85 Figure 19. Driver Propagation Delay vs. Temperature 800 04736-022 2 360 CH2 1.00V CH4 5.00V M200ns A CH1 T 1.33600s 3.10V Figure 21. Driver/Receiver Propagation Delay High to Low RCVR PROP HL/VDD1 = VDD2 = 5.0V 700 1 600 RCVR PROP LH/VDD1 = VDD2 = 5.0V 400 300 200 0 -40 25 TEMPERATURE (C) 85 04736-023 2 100 04736-035 TIME (ns) 500 4 CH1 5.00V CH3 1.00V Figure 20. Receiver Propagation Delay vs. Temperature CH2 1.00V CH4 5.00V M200ns A CH1 T 360.000ns 3.10V Figure 22. Driver/Receiver Propagation Delay Low to High Rev. B | Page 12 of 20 35 300 30 OUTPUT CURRENT (mA) 350 250 BUS SIDE 200 150 LOGIC SIDE 100 0 0 50 100 150 CASE TEMPERATURE (C) -15 -20 -25 04736-036 OUTPUT CURRENT (mA) -10 3.6 3.8 4.0 4.2 4.4 OUTPUT VOLTAGE (V) 4.6 4.8 10 0 -5 3.4 15 0 200 0 3.2 20 5 Figure 23. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per VDE 0884 -30 3.0 25 04736-037 50 04736-024 SAFETY-LIMITING CURRENT (mA) ADM2483 5.0 Figure 24. Output Current vs. Receiver Output High Voltage Rev. B | Page 13 of 20 0.25 0.50 0.75 1.00 1.25 1.50 1.75 OUTPUT VOLTAGE (V) 2.00 2.25 Figure 25. Output Current vs. Receiver Output Low Voltage ADM2483 CIRCUIT DESCRIPTION ELECTRICAL ISOLATION iCoupler Technology In the ADM2483, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 26). Driver input and data enable signals, applied to the TxD and DE pins, respectively, and referenced to logic ground (GND1), are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (GND2). Similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground. The digital signals are transmitted across the isolation barrier using iCoupler technology. This technique uses chip-scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted. VDD1 VDD2 ISOLATION BARRIER A ENCODE TxD DECODE D B DE ENCODE DECODE RxD ENCODE DECODE R DIGITAL ISOLATION GND1 TRANSCEIVER GND2 Figure 26. ADM2483 Digital Isolation and Transceiver Sections Rev. B | Page 14 of 20 04736-025 RE ADM2483 TRUTH TABLES THERMAL SHUTDOWN The following truth tables use these abbreviations: The ADM2483 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150C is reached. As the device cools, the drivers are re-enabled at a temperature of 140C. Letter H L X Z NC Description High level Low level Irrelevant High impedance (off) Disconnected Table 9. Transmitting Supply Status VDD1 VDD2 On On On On On On On Off Off On Off Off TRUE FAIL-SAFE RECEIVER INPUTS DE H H L X X X Inputs TxD H L X X X X A H L Z Z Z Z Outputs B L H Z Z Z Z The receiver inputs have a true fail-safe feature, which ensures that the receiver output is high when the inputs are open or shorted. During line-idle conditions, when no driver on the bus is enabled, the voltage across a terminating resistance at the receiver input decays to 0 V. With traditional transceivers, receiver input thresholds specified between -200 mV and +200 mV mean that external bias resistors are required on the A and B pins to ensure that the receiver outputs are in a known state. The true fail-safe receiver input feature eliminates the need for bias resistors by specifying the receiver input threshold between -30 mV and -200 mV. The guaranteed negative threshold means that when the voltage between A and B decays to 0 V, the receiver output is guaranteed to be high. Table 10. Receiving Supply Status VDD1 On On VDD2 On On On On On On Off Off On On On Off On Off Inputs A - B (V) >-0.03 <-0.2 -0.2 < A - B < -0.03 Inputs open X X X X Outputs RE L or NC L or NC RxD H L L or NC L or NC H L or NC L or NC L or NC Indeterminate H Z H H L MAGNETIC FIELD IMMUNITY POWER-UP/POWER-DOWN CHARACTERISTICS The power-up/power-down characteristics of the ADM2483 are in accordance with the supply thresholds shown in Table 11. Upon power-up, the ADM2483 output signals (A, B, and RxD) reach their correct state once both supplies exceed their thresholds. Upon power-down, the ADM2483 output signals retain their correct state until at least one of the supplies drops below its power-down threshold. When the VDD1 power-down threshold is crossed, the ADM2483 output signals reach their unpowered states within 4 s. Table 11. Power-Up/Power-Down Thresholds Supply VDD1 VDD1 VDD2 VDD2 Transition Power-up Power-down Power-up Power-down Threshold (V) 2.0 1.0 3.3 2.4 Because iCouplers use a coreless technology, no magnetic components are present, and the problem of magnetic saturation of the core material does not exist. Therefore, iCouplers have essentially infinite dc field immunity. The analysis that follows defines the conditions under which this might occur. The ADM2483's 3 V operating condition is examined because it represents the most susceptible mode of operation. The limitation on the iCoupler's ac magnetic field immunity is set by the condition in which the induced error voltage in the receiving coil (the bottom coil in this case) is made sufficiently large, either to falsely set or reset the decoder. The voltage induced across the bottom coil is given by - d 2 V = rn ; n = 1, 2, ... , N dt where if the pulses at the transformer output are greater than 1.0 V in amplitude: = magnetic flux density (gauss) N= number of turns in receiving coil rn = radius of nth turn in receiving coil (cm) The decoder has a sensing threshold of about 0.5 V; therefore, there is a 0.5 V margin in which induced voltages can be tolerated. Rev. B | Page 15 of 20 ADM2483 10.000 1.000 0.100 DISTANCE = 5mm 10.00 DISTANCE = 100mm 1.00 0.10 0.01 1k 04736-027 0.010 0.001 1k DISTANCE = 1m 100.00 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 27. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kGauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V. This is well above the 0.5 V sensing threshold of the decoder. 04736-028 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGAUSS) 100.000 1000.00 MAXIMUM ALLOWABLE CURRENT (kA) Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 27. 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 28. Maximum Allowable Current for Various Current-to-ADM2483 Spacings At combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce large enough error voltages to trigger the thresholds of succeeding circuitry. To avoid this possibility, care should be taken in the layout of such traces. These magnetic flux density values are shown in Figure 28, using more familiar quantities such as maximum allowable current flow, at given distances away from the ADM2483 transformers. Rev. B | Page 16 of 20 ADM2483 APPLICATIONS INFORMATION POWER_VALID INPUT ISOLATED POWER SUPPLY CIRCUIT To avoid chatter on the A and B outputs caused by slow powerup and power-down transients on VDD1 (>100 s/V), the ADM2483 features a power_valid (PV) digital input. This pin should be driven low until VDD1 exceeds 2.0 V. When VDD1 is greater than 2.0 V, the pin should be driven high. Conversely, upon power-down, the PV should be driven low before VDD1 reaches 2.0 V. The ADM2483 requires isolated power capable of 5 V at 100 mA to be supplied between the VDD2 and GND2 pins. If no suitable integrated power supply is available, a discrete circuit, such as the one in Figure 30, can be used. A center-tapped transformer provides electrical isolation. The primary winding is excited with a pair of square waveforms that are 180 out of phase with each other. A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP667 linear voltage regulator provides a regulated power supply to the ADM2483's bus-side circuitry. The power_valid input can be driven, for example, by the output of a system reset circuit such as the ADM809Z, which has a threshold voltage of 2.32 V. VDD1 To create the pair of square waves, a D-type flip-flop with complementary Q/Q outputs is used. The flip-flop can be connected so that output Q follows the clock input signal. If no local clock signal is available, a simple digital oscillator can be implemented with a hex-inverting Schmitt trigger and a resistor and capacitor. In this case, values of 3.9 k and 1 nF generate a 364 kHz square wave. A pair of discrete NMOS transistors, switched by the Q/Q flip-flop outputs, conduct current through the center tap of the primary transformer, winding in an alternating fashion. VDD1 ADM809Z ADM2483 RESET PV GND1 VDD1 2.0V 2.0V tPOR 04736-029 Figure 29. Driving PV with ADM809Z VCC ISOLATION BARRIER 100nF 3.9k 100nF SD103C BS107A VCC PR IN CLR D VCC Q 22F OUT 5V ADP667 74HC74A CLK 74HC14 1nF Q BS107A SET GND SHDN 78253 SD103C VCC VDD1 VDD2 ADM2483 GND1 Figure 30. Isolated Power Supply Circuit Rev. B | Page 17 of 20 GND2 04736-030 RESET 2.32V 2.32V ADM2483 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1 1.27 (0.0500) BSC 0.75 (0.0295) x 45 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 8 0.33 (0.0130) 0 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 31. 16-Lead Standard Small Outline Package [SOIC] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADM2483BRW ADM2483BRW-REEL1 ADM2483BRWZ2 ADM2483BRWZ-REEL1, 2 1 2 Data Rate (kbps) 500 500 500 500 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C A -REEL suffix designates a 13-inch (1,000 units) tape-and-reel option. Z = Pb-free part. Rev. B | Page 18 of 20 Package Description 16-Lead, Wide Body SOIC 16-Lead, Wide Body SOIC 16-Lead, Wide Body SOIC 16-Lead, Wide Body SOIC Package Option RW-16 RW-16 RW-16 RW-16 ADM2483 NOTES Rev. B | Page 19 of 20 ADM2483 NOTES (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04736-0-3/05(B) Rev. B | Page 20 of 20