GAIN
200
ADC14155
ROUT
3
LATCH
RF
LO
LMH6514
VCC
RLOAD
LMH6514
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LMH6514 600 MHz, Digital Controlled, Variable Gain Amplifier
Check for Samples: LMH6514
1FEATURES DESCRIPTION
The LMH6514 is a high performance, digitally
2• Adjustable Gain with a 42 dB Range controlled variable gain amplifier (DVGA). It combines
• Precise 6.02 dB Gain Steps precision gain control with a low noise, ultra-linear,
• Parallel 3 Bit Gain Control differential amplifier. Typically, the LMH6514 drives a
high performance ADC in a broad range of mixed
• On Chip Register Gain Setting signal and digital communication applications such as
• Fully Differential Signal Path mobile radio and cellular base stations where
• Single Ended to Differential Capable automatic gain control (AGC) is required to increase
system dynamic range. When used in conjunction
• 200ΩInput Impedance with a high speed ADC, system dynamic range can
• Small Footprint (4 mm x 4 mm) WQFN Package be extended by up to 42 dB.
The LMH6514 has a differential input and output
APPLICATIONS allowing large signal swings on a single 5V supply. It
• Cellular Base Stations is designed to accept signals from RF elements and
• IF Sampling Receivers maintain a terminated impedance environment. The
input impedance is 200Ωresistive. The output
• Instrumentation impedance is either 200Ωor 400Ωand is user
• Modems selectable. A unique internal architecture allows use
• Imaging with both single ended and differential input signals.
• Differential Line Receiver Input signals to the LMH6514 are scaled by a highly
linear, digitally controlled attenuator with seven
KEY SPECIFICATIONS accurate 6 dB steps. The attenuator output provides
the input signal for a high gain, ultra linear differential
• 600 MHz bandwidth at 100Ωload transconductor. The transconductor differential output
• 39 dBm OIP3 at 75 MHz, 200Ωload current can be converted into a voltage by using the
• 26 dB to 38 dB maximum gain on-chip 200Ωor 400Ωloads. The transconductance
gain is 0.1 Amp/Volt resulting in a maximum voltage
• Selectable output impedance of 200Ωor 400Ω.gain of +32 dB when driving a 200Ωload, or 38 dB
• 8.3 dB noise figure when driving the 400Ωload.
• 5 ns gain step switching time The LMH6514 operates over the industrial
• 100 mA supply current temperature range of −40°C to +85°C. The LMH6514
is available in a 16-Pin, thermally enhanced, WQFN
package.
Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMH6514
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
ESD Tolerance (3)
Human Body Model 2 kV
Machine Model 150V
Positive Supply Voltage (Pin 3) −0.6V to 5.5V
Output Voltage (Pin 14,15) −0.6V to 6.8V
Differential Voltage between Any Two Grounds <200 mV
Analog Input Voltage Range −0.6V to VCC
Digital Input Voltage Range −0.6V to 3.6V
Output Short Circuit Duration
(one pin to ground) Infinite
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Soldering Information
Infrared or Convection (20 sec) 235°C
Wave Soldering (10 sec) 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Operating Ratings(1)
Supply Voltage (Pin 3) 4V to 5.25V
Output Voltage Range (Pin 14, 15) 1.4V to 6.4V
Differential Voltage Between Any Two Grounds <10 mV
Analog Input Voltage Range,
AC Coupled ±1.4V
Temperature Range (2) −40°C to +85°C
Package Thermal Resistance (θJA)
16-Pin WQFN 47°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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5V Electrical Characteristics(1)
The following specifications apply for single supply with VCC = 5V, Maximum Gain , RL= 100Ω(200Ωexternal || 200Ω
internal), VOUT = 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(2) (3) (2)
Dynamic Performance
SSBW −3 dB Bandwidth Average of all Gain Settings 600 MHz
Noise and Distortion
Third Order Intermodulation f = 75 MHz, V OUT = 2 VPP −70
Products f = 150 MHz, V OUT = 2 VPP −66 dBc
f = 250 MHz, V OUT = 2 VPP −60
f = 450 MHz, V OUT = 2 VPP −52
OIP3 Output Third Order Intercept Point f = 75 MHz, V OUT = 2 VPP, 35
Tone Spacing = 0.5 MHz
f = 150 MHz, V OUT = 2 VPP, 33
Tone Spacing = 2 MHz
f = 250 MHz, V OUT = 2 VPP, 31
Tone Spacing = 2 MHz dBm
f = 75 MHz, RL= 200Ω, V OUT = 2 VPP 39
Tone Spacing = 0.5 MHz
f = 150 MHz, RL= 200Ω, V OUT = 2 VPP, 37
Tone Spacing = 2 MHz
f = 250 MHz, RL= 200Ω, V OUT = 2 VPP, 34
Tone Spacing = 2 MHz
P1 dB Output Level for 1 dB Gain f = 75 MHz, R L= 200Ω16.7
Compression f = 250 MHz, R L= 200Ω14.7 dBm
f = 75 MHz 14.5
f = 450 MHz 13.2
VNI Input Noise Voltage Maximum Gain, f = 40 MHz 1.8 nV/√Hz
VNO Output Noise Voltage Maximum Gain, f = 40 MHz 36 nV/√Hz
NF Noise Figure Maximum Gain 8.3 dB
Analog I/O
Differential Input Resistance 165 188 220 Ω
158 230
Input Common Mode Resistance 825 955 1120 Ω
785 1160
Differential Output Resistance Low Gain Option 186
Ω
High Gain Option 330 370 420
325 425
Internal Load Resistors Between Pins 13, 14 and Pins 15, 16 165 187 215 Ω
158 225
Input Signal Level (AC Coupled) Max Gain, VO= 2 VPP, RL= 1 kΩ63 mVPP
Maximum Differential Input Signal AC Coupled 5.6 VPP
Input Common Mode Voltage Self Biased 1.3 1.4 1.5 V
1.1 1.7
Input Common Mode Voltage Driven Externally 0.9 to 2.0 V
Range
Minimum Input Voltage DC 0 V
Maximum Input Voltage DC 3.3 V
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No specification of parametric performance
is indicated in the electrical tables under conditions different than those tested
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
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5V Electrical Characteristics(1) (continued)
The following specifications apply for single supply with VCC = 5V, Maximum Gain , RL= 100Ω(200Ωexternal || 200Ω
internal), VOUT = 2 VPP, fin = 150 MHz. Boldface limits apply at temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(2) (3) (2)
Maximum Differential Output VCC = 5V, Output Common Mode = 5V 5.5 VPP
Voltage Swing
VOS Output Offset Voltage All Gain Settings −21 mV
CMRR Common Mode Rejection Ratio Maximum Gain 81 dB
PSRR Power Supply Rejection Ratio Maximum Gain 63 81 dB
61
Gain Parameters
Maximum Gain DC, Internal RL= 186Ω, 29.3 30 30.3 dB
External RL= 1280Ω28.7 30.9
Minimum Gain DC, Internal RL= 186Ω,−12.75 −12 −11.85 dB
External RL= 1280Ω−13.15 −11.45
Gain Step Size DC 6.02 dB
Gain Step Error DC 0.02 dB
f = 150 MHz 0.07
Cumulative Gain Step Error DC, Gain Step 7 to Gain Step 0 −0.35 0.02 0.30 dB
−0.50 0.45
Gain Step Switching Time 5 ns
Digital Inputs/Timing
Logic Compatibility CMOS Logic 3.3 V
VIL Logic Input Low Voltage 0.8 V
VIH Logic Input High Voltage 2.0 V
IIH Logic Input High Input Current(4) Digital Input Voltage = 3.3V 33 40 μA
TSU Setup Time 3 ns
THOLD Hold Time 3 ns
TPW Minimum Latch Pulse Width 10 ns
Power Requirements
ICC Total Supply Current VOUT = 0V Differential, VOUT Common 107 124 mA
Mode = 5V 134
Amplifier Supply Current Pin 3 Only 56 66 mA
74
Output Stage Bias Currents Pins 13, 14 and Pins 15, 16; 51 58 mA
VOUT Common Mode = 5 V 60
(4) Negative input current implies current flowing out of the device.
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14
15
16
13
3
2
1
4
10
11
12
9
7
6
5
8
OUT-
OUT+
GAIN_2
GAIN_1
GAIN_0
NC
NC
V+
LATCH
NC
GND
IN+
IN-
GND LOAD+
LOAD-
GND
LMH6514
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SNOSB06A –JANUARY 2008–REVISED MARCH 2013
Connection Diagram
Figure 1. 16-Pin WQFN (Top View)
Gain Control Pins
Pin Number Pin Name Gain Step Size
11 GAIN_0 6.02 dB
10 GAIN_1 12.04 dB
9 GAIN_2 24.08 dB
spacer
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PIN DESCRIPTIONS
Pin Number Symbol Description
Analog I/O
6 IN+ Non-inverting analog input. Internally biased to 1.4V. Input voltage should not exceed VCC or
go below GND by more than 0.5V.
7 IN−Inverting analog input. Internally biased to 1.4V. Input voltage should not exceed VCC or go
below GND by more than 0.5V. If using amplifier single ended this input should be capacitively
coupled to ground.
15 OUT−Open collector inverting output. This pin is an output that also requires a power source. This
pin should be connected to 5V through either an RF choke or an appropriately sized inductor
that can form part of a filter. See Application Information for details.
14 OUT+ Open collector non-inverting output. This pin is an output that also requires a power source.
This pin should be connected to 5V through either an RF choke or an appropriately sized
inductor that can form part of a filter. See Application Information for details.
16 LOAD−Internal 200Ωresistor connection to pin 15. This pin can be left floating for higher gain or
shorted to pin 13 for lower gain and lower effective output impedance. See Application
Information for details.
13 LOAD+ Internal 200Ωresistor connection to pin 14. This pin can be left floating for higher gain or
shorted to pin 16 for lower gain and lower effective output impedance. See Application
Information for details.
Power
3 VCC 5V power supply pin. Use ceramic, low ESR bypass capacitors. This pin powers everything
except the output stage.
5,8 GND Ground pins. Connect to low impedance ground plane. All pin voltages are specified with
respect to the voltage on these pins. The exposed thermal pad is also a ground connection.
Digital Inputs
11,10,9 GAIN_0 to Gain setting pins. See above table for gain step sizes for each pin. These pins are 3.3V CMOS
GAIN_2 logic compatible. 5V inputs may cause damage.
2 LATCH This pin controls the function of the gain setting pins mentioned above. With LATCH in the
logic HIGH state the gain is fixed and will not change. With the LATCH in the logic LOW state
the gain is set by the state of the gain control pins. Any changes in gain made with the LATCH
pin in the LOW state will take effect immediately. This pin is 3.3V CMOS logic compatible. 5V
inputs may cause damage.
1,4,12 NC These pins are not connected. They can be grounded or left floating.
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-40 -20 0 20 40 60 80
TEMPERATURE (°C)
20
25
30
35
40
45
OIP3 (dBm)
75 MHz
150 MHz
250 MHz
RL = 200:
0 1 2 3 4 5 6 7
20
22
24
26
28
30
32
34
36
38
40
OIP3 (dBm)
GAIN STEP (0 = MAXIMUM GAIN)
f = 75 MHz
f = 150 MHz
f = 250 MHz
VOUT = 2 VPP
RL = 100:
INPUT CLIPPING
FREQUENCY (MHz)
10 100 1000
-21
-20
-19
-18
-17
-16
GAIN (dB)
-40°C
25°C
85°C
PIN = 10 dBm
RL = 100:
0 1 2 3 4 5 6 7
20
22
24
26
28
30
32
34
36
38
40
OIP3 (dBm)
GAIN STEP (0 = MAXIMUM GAIN)
f = 75 MHz
f = 150 MHz
f = 250 MHz
VOUT = 2 VPP
RL = 200:
INPUT CLIPPING
1 10 100 1000
-22
-19
-16
-13
-10
-7
5
14
17
20
23
26
11
8
2
-1
-4
GAIN (dB)
FREQUENCY (MHz)
RL = 100:
FREQUENCY (MHz)
10 100 1000
21
22
23
24
25
26
GAIN (dB)
-40°C
25°C
85°C
PIN = -16 dBm
RL = 100:
LMH6514
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Typical Performance Characteristics
VCC = 5V
Frequency Response All Gain Settings Frequency Response over Temperature, Maximum Gain
Figure 2. Figure 3.
Frequency Response over Temperature, Minimum Gain OIP3 High Gain Mode
Figure 4. Figure 5.
OIP3 Low Gain Mode OIP3 Over Temperature
Figure 6. Figure 7.
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1 VPP
050 100 150 200 250 300
FREQUENCY (MHz)
-110
-100
-90
-80
-70
-60
-50
-40
-30
DISTORTION (dBc)
RL = 200:
2.8 VPP
2 VPP
050 100 150 200 250 300
FREQUENCY (MHz)
-90
-80
-70
-60
-50
-40
-30
DISTORTION (dBc)
RL = 200:
2.8 VPP
2 VPP
1 VPP
050 100 150 200 250 300 350 400
FREQUENCY (MHz)
-100
-90
-80
-70
-60
-50
-40
-30
DISTORTION (dBc)
RL = 100:
2.8 VPP
2 VPP
1 VPP
050 100 150 200 250 300 350 400
FREQUENCY (MHz)
-90
-80
-70
-60
-50
-40
-30
DISTORTION (dBc)
RL = 100:
2.8 VPP
1 VPP
2 VPP
01 2 3 4 5 6
GAIN STEP (0 = MAXIMUM GAIN)
-70
-65
-60
-55
-50
-45
-40
IMD3 (dBc)
7
VOUT = 2 VPP
RL = 100:
f = 250 MHz
f = 150 MHz
f = 75 MHz
INPUT CLIPPING
01 2 3 4 5 6
GAIN STEP (0 = MAXIMUM GAIN)
-85
-80
-75
-70
-65
-60
-55
IMD3 (dBc)
7
VOUT = 2 VPP
RL = 200:
f = 250 MHz
f = 150 MHz
f = 75 MHz
INPUT CLIPPING
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Typical Performance Characteristics
VCC = 5V (continued)
IMD3 Low Gain Mode IMD3 High Gain Mode
Figure 8. Figure 9.
HD2 HD3
vs. vs.
Frequency Frequency
Figure 10. Figure 11.
HD2 HD3
vs. vs.
Frequency Frequency
Figure 12. Figure 13.
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-40 -20 0 20 40 60 80
23
23.5
24
24.5
25
25.5
26
TEMPERATURE (°C)
MAXIMUM GAIN (dB)
f = 75 MHz
f = 150 MHz
f = 250 MHz
VOUT = 2 VPP
RL = 100:
10 100 1k 10k 100k
EXTERNAL DIFFERENTIAL LOAD (:)
18
22
26
30
34
38
42
MAXIMUM GAIN (dB)
400: INTERNAL WITH 400:
EXTERNAL = 32 dB NET
200: INTERNAL WITH 200:
EXTERNAL = 26 dB NET
INTERNAL LOAD =
200:
INTERNAL LOAD
= 400:
01 2 3 4 5 6
GAIN SETTING (0 = MAXIMUM GAIN)
0
10
20
30
40
50
60
7
OUTPUT NOISE (nV/
Hz)
f = 75 MHz
RL = 133:
RL = 100:
3.5 4 4.5 5 5.5
24
24.5
25
25.5
26
MAXIMUM GAIN (dB)
SUPPLY VOLTAGE (V)
RL = 100:
PIN = -25 dBm
f = 75 MHz
f = 150 MHz
f = 250 MHz
0 100 200 300 400
8
9
10
11
12
13
NOISE FIGURE (dB)
FREQUENCY (MHz)
MAXIMUM GAIN
0 1 2 3 4 5 6 7
5
10
15
20
25
30
35
40
45
50
55
NOISE FIGURE (dB)
GAIN SETTING (0 = MAXIMUM GAIN)
f = 150 MHz
f = 75 MHz
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Typical Performance Characteristics
VCC = 5V (continued)
Noise Figure for All Gain Settings Noise Figure vs. Frequency
Figure 14. Figure 15.
Differential Output Noise Maximum Gain vs. Supply Voltage
Figure 16. Figure 17.
Gain vs. External Load Maximum Gain over Temperature
Figure 18. Figure 19.
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50 100 150 200 250 300 350 400 450
FREQUENCY (MHz)
-50
0
50
100
150
200
250
300
350
INPUT IMPEDANCE (:)
|Z|
R
jX
50 100 150 200 250 300 350 400 450
FREQUENCY (MHz)
-50
0
50
100
150
200
250
300
350
INPUT IMPEDANCE (:)
|Z|
R
jX
50 100 150 200 250 300 350 400 450
FREQUENCY (MHz)
-50
0
50
100
150
200
250
300
350
INPUT IMPEDANCE (:)
|Z|
R
jX
050 100 150 200 250 300
FREQUENCY (MHz)
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
ERROR (dB)
RL = 100:
85°C
25°C
-40°C
1 2 3 4 5 6 7
5.95
6.00
6.05
6.10
6.15
6.20
6.25
6.30
6.35
6.40
6.45
STEP SIZE (dB)
GAIN STEP
IDEAL
f = 250 MHz
f = 150 MHz
f = 75 MHz
VOUT = 1 VPP
RL = 100:
HIGH
GAIN LOW
GAIN
12 3 45 6 7
GAIN STEP (0 = MAXIMUM GAIN)
5.90
5.95
6.00
6.05
6.10
6.15
6.20
6.25
GAIN STEP SIZE (dB)
85°C
25°C
-40°C
f = 150 MHz
VOUT = 2 VPP
RL = 100:
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Typical Performance Characteristics
VCC = 5V (continued)
Worst Case Gain Step Error
vs
Frequency Gain Steps over Temperature
Figure 20. Figure 21.
Worst Case Gain Step Error over Temperature Input Impedance (S11) at Maximum Gain
Figure 22. Figure 23.
Input Impedance (S11) at Minimum Gain Output Impedance (S22) at Maximum Gain Low Gain Mode
Figure 24. Figure 25.
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0 10 20 30 40
-1.5
-1
-0.5
0
0.5
1
1.5
TIME (ns)
LATCH PIN
VOUT
RL = 100:4
1
3
2
0
VOUT (V)
LATCH (V)
0 10 20 30 40
-1.5
-1
-0.5
0
0.5
1
1.5
TIME (ns)
LATCH PIN
VOUT
RL = 100:4
1
3
2
0
VOUT (V)
LATCH (V)
110 100 1000
FREQUENCY (MHz)
-90
-80
-70
-60
-50
-40
-30
CROSSTALK (dBc)
PIN = -10 dBm
LOAD = 200:
MAX GAIN
LATCH
GAIN 1
0 10 20 30 40 50 60 70 80 90 100
-40
-30
-20
-10
0
10
20
30
40
DIFFERENTIAL OUTPUT (mV)
TIME (ns)
0
3
GAIN CONTROL SIGNALS (V)
LATCH = 3.3V
PINS 9, 10, 11,12
50 100 150 200 250 300 350 400 450
FREQUENCY (MHz)
-50
0
50
100
150
200
250
300
350
INPUT IMPEDANCE (:)
|Z|
R
jX
0 10 20 30 40 50 60 70 80 90 100
-40
-30
-20
-10
0
10
20
30
40
DIFFERENTIAL OUTPUT (mV)
TIME (ns)
0
3
GAIN CONTROL SIGNALS (V)
LATCH = 0
PINS 9, 10, 11,12
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Typical Performance Characteristics
VCC = 5V (continued)
Output Impedance (S22) at
Maximum Gain High Gain Mode Digital Crosstalk
Figure 26. Figure 27.
Digital Crosstalk Digital Pin to Output Isolation
Figure 28. Figure 29.
Minimum Gain to Maximum Gain Switching Maximum Gain to Minimum Gain Switching
Using Latch Pin Using Latch Pin
Figure 30. Figure 31.
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0 10 20 30 40
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
TIME (ns)
0
1
2
3
4
GAIN BIT 0 (V)
GAIN BIT 0
VOUT
0 10 20 30 40
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
TIME (ns)
0
1
2
3
4
GAIN BIT 0 (V)
GAIN BIT 0
VOUT
0 10 20 30 40
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
TIME (ns)
0
1
2
3
4
GAIN BIT 1 (V)
GAIN BIT 1
VOUT
0 10 20 30 40
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
TIME (ns)
0
1
2
3
4
GAIN BIT 1 (V)
GAIN BIT 1
VOUT
0 10 20 30 40
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
TIME (ns)
GAIN BIT 2
VOUT
4
1
3
2
0
GAIN BIT 2 (V)
0 10 20 30 40
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
TIME (ns)
GAIN BIT 2
VOUT
4
1
3
2
0
GAIN BIT 2 (V)
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Typical Performance Characteristics
VCC = 5V (continued)
24 dB Gain Step 24 dB Gain Step
Figure 32. Figure 33.
12 dB Gain Step 12 dB Gain Step
Figure 34. Figure 35.
6 dB Gain Step 6 dB Gain Step
Figure 36. Figure 37.
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-10 -5 0 5 10 15 20 25 30
TIME (Ps)
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
VOUT (V)
f = 250 MHz
ENVELOPE DISPLAYED
VOUT
V+0
1
2
3
4
5
6
POWER SUPPLY (V)
-10 -5 0 5 10 15 20 25 30
TIME (Ps)
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
VOUT (V)
f = 250 MHz
ENVELOPE DISPLAYED
VOUT
V+
0
1
2
3
4
5
6
POWER SUPPLY (V)
-10 -5 0 5 10 15 20 25 30
TIME (Ps)
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
VOUT (V)
f = 250 MHz
ENVELOPE DISPLAYED
VOUT
V+
0
1
2
3
4
5
6
POWER SUPPLY (V)
-10 -5 0 5 10 15 20 25 30
TIME (Ps)
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
VOUT (V)
f = 250 MHz
ENVELOPE DISPLAYED
VOUT
V+
0
1
2
3
4
5
6
POWER SUPPLY (V)
LMH6514
www.ti.com
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
Typical Performance Characteristics
VCC = 5V (continued)
Power On Timing, Maximum Gain Power On Timing, Minimum Gain
Figure 38. Figure 39.
Power Off Timing, Maximum Gain Power Off Timing, Minimum Gain
Figure 40. Figure 41.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMH6514
01 2 3 4 5 6
PHASE (RADIANS)
2
3
4
5
6
7
VOUT (V)
COMMON MODE
= 5V
MAXIMUM OUTPUT VOLTAGE = 6.4V
OUT +
OUT -
1.4 VP
VOUT = 5.6 VPP DIFFERENTIAL
GAIN
200
ADC
200
3
LATCH
LMH6514
VCC
VCM = VCC
44.3 nH
10 pF
VCC
LMH6514
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
www.ti.com
APPLICATION INFORMATION
The LMH6514 is a fully differential amplifier optimized for signal path applications up to 400 MHz. The LMH6514
has a 200Ωinput. The absolute gain is load dependent, however the gain steps are always 6 dB. The LMH6514
output stage is a class A amplifier. This class A operation results in excellent distortion and linearity
characteristics. This makes the LMH6514 ideal for voltage amplification and an ideal ADC driver where high
linearity is necessary.
Figure 42. LMH6514 Typical Application
The LMH6514 output common mode should be set carefully. Using inductors to set the output common mode is
one preferred method and will give maximum output swing. AC coupling of the output is recommended. The
inductors mentioned above will shift the idling output common mode to the positive supply. Also, with the
inductors, the output voltage can exceed the supply voltage. Other options for setting the output common mode
require supply voltages above 5V. If using a supply higher than 5V care should be taken to make sure the output
common mode does not exceed the 5.25V supply rating.
It is also important to note the maximum voltage limits for the OUT+ and OUT−pins, which is 6.4V. When using
inductors these pins will experience voltage swings beyond the supply voltage. With a 5V output common mode
operating point this makes the effective maximum swing 5.6 VPP differential. System calibration and automatic
gain control algorithms should be tailored to avoid exceeding this limit. Figure 43 shows how output voltage and
output common mode add together and approach the maximum output voltage.
Figure 43. Output Voltage with Respect to the Output Common Mode
In order to help with system design Texas Instruments offers the ADC14V155KDRB High IF Receiver reference
design board. This board combines the LMH6514 DVGA with the ADC14V155 ADC and provides a ready made
solution for many IF receiver applications. Using an IF frequency of 169 MHz it achieves a small signal SNR of
72 dBFS and an SFDR of greater than 90 dBFS. Large signal measurements show an SNR of 68 dBFS and an
SFDR of 77 dBFS. The High IF Receiver board also features the LMK03000 low-jitter precision clock conditioner.
14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6514
GAIN
200
3
LATCH
LMH6514
5V
Vin
R1
RIN = R1 || 200
INTERNAL BIAS = 1.4V
C1
C2
6
7
5, 8
+IN
-IN
OUT- OUT+
6dB STEP
VARIABLE
ATTENUATOR
0 to -42 dB +38 dB
200:
200:200:
400:
13
14
16
15
+
-
LMH6514
www.ti.com
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
Figure 44. LMH6514 Block Diagram
INPUT CHARACTERISTICS
The LMH6514 input impedance is set by internal resistors to a nominal 200Ω. Process variations will result in a
range of values as shown in the Electrical Characteristics table. At higher frequencies parasitics will start to
impact the impedance. This characteristic will also depend on board layout and should be verified on the
customer’s system board.
At maximum gain the digital attenuator is set to 0 dB and the input signal will be much smaller than the output. At
minimum gain the output is 4 dB or more smaller than the input. In this configuration the input signal size may
limit the amplifier output amplitude, depending on the output configuration and the desired output signal voltage.
The input signal cannot swing more than 0.5V below the negative supply voltage (normally 0V) nor should it
exceed the positive supply voltage. The input signal will clip and cause severe distortion if it is too large. Because
the input stage self biases to approximately 1.4V the lower supply voltage will impose the limit for input voltage
swing. To drive larger input signals the input common mode can be forced higher than 1.4V to allow for more
swing. An input common mode of 2.0V will allow an 8 VPP maximum input signal. The trade off for input signal
swing is that as the input common mode is shifted away from the 1.4V internal bias point the distortion
performance will suffer slightly.
Figure 45. Single Ended Input
(Note capacitor on grounded input)
At the frequencies where the LMH6514 is the most useful the input impedance is not 200 Ωand it may not be
purely resistive. For many AC coupled applications the impedance can be easily changed using LC circuits to
transform the actual impedance to the desired impedance.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMH6514
GAIN 1-5
5
LATCH
LMH6514
5V
VIN
ZIN
C1
C2
L1 = 550 nH
C1 = 36 pF
C2 = 36 pF
L1
SOURCE IMPEDANCE = 200:
f = 100 MHz
ZAMP = (150 ± j0):
ZIN = (202 ± j0.5):
ZAMP
GAIN 1-5
5
LATCH
LMH6514
5V
VIN
ZIN
C1
C2
C3
C3 = 22 pF
L1 = 169 nH
C1 = 1 nF
C2 = 1 nF
L1
SOURCE IMPEDANCE = 50:
f = 100 MHz
ZAMP = (150 ± j0):
ZIN = (50 ± j1):
ZAMP
LMH6514
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
www.ti.com
Figure 46. Single Ended Input with LC Matching
As shown in Figure 46 a single ended 50Ωsource is matched to the LMH6514 input at 100 MHz. The loss in this
circuit is related to the parasitic resistance in the inductor and capacitor and the bandwidth is related to the
loaded Q of the circuit. Since the Q, at 1.4 is quite low, the bandwidth is very wide. (59 MHz 0.3 dB bandwidth).
The input match of this circuit is quite good. It converts the ZAMP of the amplifier, which is (150 +j0)Ωto (50+j1)Ω.
The benefit of LC matching circuits over a transformer is the ability to match ratios that are not commonly found
on transformers and also the ability to neutralize reactance to present a purely resistive load to the voltage
source.
Figure 47. Differential 200ΩLC Conversion Circuit
In Figure 47 the input source resistance is 200Ωdifferential. Here the desired input impedance is higher than the
amplifier input impedance, and is differential as well. The amplifier impedance of (150–j0)Ωis increased to
(202–j0.5)Ω. For an easy way to calculate the L and C circuit values there are several options for online tools or
down-loadable programs. The following tool might be helpful.
http://www.circuitsage.com/matching/matcher2.html
Excel can also be used for simple circuits; however, the “Analysis ToolPak” add-in must be installed to calculate
complex numbers.
16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6514
110 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
RL = 100: TOTAL
1 PH
470 nH
200 nH
LMH6514
www.ti.com
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
OUTPUT CHARACTERISTICS
The LMH6514 has the option of two different output configurations. The LMH6514 is an open collector topology.
As shown in Figure 52 each output has an on chip 200Ωpull up resistor. In addition there is an internal 400Ω
resistor between the two outputs. This results in a 200Ωor a 400Ωdifferential load in parallel with the external
load. The 400Ωoption is the high gain option and the 200Ωprovides for less gain. The 200Ωconfiguration is
recommended unless more gain is required.
The output common mode of the LMH6514 must be set by external components. Most applications will benefit
from the use of inductors on the output stage. In particular, the 400Ωoption as shown in Figure 53 will require
inductors in order to be able to develop an output voltage. The 200Ωoption as shown in Figure 54 or Figure 55
will also require inductors since the voltage drop due to the on chip 200Ωresistors will saturate the output
transistors. It is also possible to use resistors and high voltage power supplies to set the output common mode.
This operation is not recommended, unless it is necessary to DC couple the output. If DC coupling is required the
input common mode and output common mode voltages must be taken into account.
Maximum bandwidth with the LMH6514 is achieved by using the low gain, low impedance output option and
using a low load resistance. With an effective load of 67Ωa bandwidth of nearly a 1 GHz can be realized. As the
effective resistance on the output stage goes up the capacitance of the board traces and amplifier output stage
limit bandwidth in a roughly linear fashion. At an output impedance of 100Ωthe bandwidth is down to 600 MHz,
and at 200Ωthe bandwidth is 260 MHz. For this reason driving very high impedance loads is not recommended.
Although bandwidth goes down with higher values of load resistance, the distortion performance improves and
gain increases. The LMH6514 has a common emitter Class A output stage and minimizing the amount of current
swing in the output devices improves distortion substantially.
The LMH6514 output stage is powered through the collectors of the output transistors. Power for the output
stage is fed through inductors and the reactance of the inductors allows the output voltage to develop. In
Figure 42 the inductors are shown with a value of 44.4 nH. The value of the inductors used will be different for
different applications. In Figure 42 the inductors have been chosen to resonate with the ADC and the load
capacitor to provide a weak band pass filter effect. For broad band applications higher value inductors will allow
for better low frequency operation. However, large valued inductors will reduce high frequency performance,
particularly inductors of small physical sizes like 0603 or smaller. Larger inductors will tend to perform better than
smaller ones of the same value even for narrow band applications. This is because the larger inductors will have
a lower DC resistance and less inter-winding capacitance and hence a higher Q and a higher self resonance
frequency. The self resonance frequency should be higher than any desired signal content by at least a factor of
2. Another consideration is that the power inductors and the filter inductors need to be placed on the circuit board
such that their magnetic fields do not cause coupling. Mutual coupling of inductors can compromise filter
characteristics and lead to unwanted distortion products.
Figure 48. Bandwidth Changes Due to Different Inductor Values
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMH6514
-40 -20 0 20 40 60 80
23
23.5
24
24.5
25
25.5
26
TEMPERATURE (°C)
MAXIMUM GAIN (dB)
f = 75 MHz
f = 150 MHz
f = 250 MHz
VOUT = 2 VPP
RL = 100:
LMH6514
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
www.ti.com
Figure 49. Gain vs. External Load
DIGITAL CONTROL
The LMH6514 has eight gain settings covering a range of 42 dB. To avoid undesirable signal transients the
LMH6514 should be powered on at the minimum gain state (all logic input pins at 0V). The LMH6514 has a 3-bit
gain control bus as well as a Latch pin. When the Latch pin is low, data from the gain control pins is immediately
sent to the gain circuit (i.e. gain is changed immediately). When the Latch pin transitions high the current gain
state is held and subsequent changes to the gain set pins are ignored. To minimize gain change glitches multiple
gain control pins should not change while the latch pin is low. In order to achieve the very fast gain step
switching time of 5 ns the internal gain change circuit is very fast. Gain glitches could result from timing skew
between the gain set bits. This is especially the case when a small gain change requires a change in state of
three or more gain control pins. If continuous gain control is desired the Latch pin can be tied to ground. This
state is called transparent mode and the gain pins are always active. In this state the timing of the gain pin logic
transitions should be planned carefully to avoid undesirable transients.
The LMH6514 was designed to interface with 3.3V CMOS logic circuits. If operation with 5V logic is required a
simple voltage divider at each logic pin will allow for this. To properly terminate 100Ωtransmission lines a divider
with a 66.5Ωresistor to ground and a 33.2Ωseries resistor will properly terminate the line as well as give the
3.3V logic levels. Care should be taken not to exceed the 3.6V absolute maximum voltage rating of the logic
pins.
EXPOSED PAD WQFN PACKAGE
The LMH6514 is packaged in a thermally enhanced package. The exposed pad is connected to the GND pins. It
is recommended, but not necessary, that the exposed pad be connected to the supply ground plane. In any
case, the thermal dissipation of the device is largely dependent on the attachment of this pad. The exposed pad
should be attached to as much copper on the circuit board as possible, preferably external copper. However, it is
also very important to maintain good high speed layout practices when designing a system board. Please refer to
the LMH6514 evaluation board for suggested layout techniques.
Package information is available on the TI web site.
http://www.ti.com/packaging
INTERFACING TO ADC
The LMH6514 was designed to be used with high speed ADCs such as the ADC14155. As shown in the Typical
Application on page 1, AC coupling provides the best flexibility especially for IF sub-sampling applications. Any
resistive networks on the output will also cause a gain loss because the output signal is developed across the
output resistors. The chart Maximum Gain vs. External Load shows the change in gain when an external load is
added.
The inputs of the LMH6514 will self bias to the optimum voltage for normal operation. The internal bias voltage
for the inputs is approximately 1.4V. In most applications the LMH6514 input will need to be AC coupled.
18 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6514
AMP ROUT
680 nH
680 nH
5V
5V
390 nH
390 nH 3 pF
41 pF 27 nH
200
ADC CIN
200:
3 pF
LMH6514
www.ti.com
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
The output common mode voltage is not self biasing, it needs to be pulled up to the positive supply rail with
external inductors as shown in Figure 42. This gives the LMH6514 the capability for large signal swings with very
low distortion on a single 5V supply. The internal load resistors provide the LMH6514 with very consistent gain.
A unique internal architecture allows the LMH6514 to be driven by either a differential or single ended source. If
driving the LMH6514 single ended the unused input should be terminated to ground with a 0.01 µF capacitor.
Directly shorting the unused input to ground will disrupt the internal bias circuitry and will result in poor
performance.
Center Frequency is 140 MHz with a 20 MHz Bandwidth
Designed for 200ΩImpedance
Figure 50. Bandpass Filter
ADC Noise Filter
Below is a filter schematic and a table of values for some common IF frequencies. The filter shown below offers
a good compromise between bandwidth, noise rejection and cost. This filter topology is the same as is used on
the ADC14V155KDRB High IF Receiver reference design board. This filter topology works best with the 12 and
14 bit sub-sampling analog to digital converters shown in the Table 2 table.
Table 1. Filter Component Values
Filter Component Values
Fc 75 MHz 140 MHz 170 MHz 250 MHz
BW 40 MHz 20 MHz 25 MHz Narrow Band
Components L1, L2 10 µH 10 µH 10 µH 10 µH
L3, L4 390 nH 39 0nH 560 nH —
C1, C2 10 pF 3 pF 1.4 pF 47 pF
C3 22 pF 41 pF 32 pF 11 pF
L5 220 nH 27 nH 30 nH 22 nH
R1, R2 100 200 100 499
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMH6514
AMP ZOUT
L2
L1
5V
5V
L4
L3 C1
C2
C3
L5
ADC ZIN
R1
ADC VIN +
ADC VIN -
ADC VCM
AMP VOUT -
AMP VOUT +
R2
LMH6514
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
www.ti.com
Figure 51. Sample Filter
POWER SUPPLIES
As shown in Figure 52, the LMH6514 has a number of options for power supply connections on the output pins.
Pin 3 (VCC) is always connected. The output stage can be connected as shown in Figure 53,Figure 54, and
Figure 55. The supply voltage range for VCC is 4V to 5.25V. A 5V supply provides the best performance while
lower supplies will result in less power consumption. Power supply regulation of 2.5% or better is advised.
Of special note is that the digital circuits are powered from an internal supply voltage of 3.3V. The logic pins
should not be driven above the absolute maximum value of 3.6V. See the DIGITAL CONTROL section for
details.
20 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6514
14
15
16
13
3
2
1
4
10
11
12
9
7
6
5
8
OUT-
OUT+
GAIN_2
GAIN_1
GAIN_0
NC
NC
VCC
LATCH
NC
GND
IN+
IN-
GND
-
+
VOUT
5V
5V
14
15
16
13
3
2
1
4
10
11
12
9
7
6
5
8
OUT-
OUT+
GAIN_2
GAIN_1
GAIN_0
NC
NC
VCC
LATCH
NC
GND
IN+
IN-
GND
-
+
VOUT
5V
5V
14
15
16
13
3
2
1
4
10
11
12
9
7
6
5
8
OUT-
OUT+
GAIN_2
GAIN_1
GAIN_0
NC
NC
VCC
LATCH
NC
GND
IN+
IN-
GND LOAD+
LOAD-
14
15
16
13
3
2
1
4
10
11
12
9
7
6
5
8
OUT-
OUT+
GAIN_2
GAIN_1
GAIN_0
NC
NC
VCC
LATCH
NC
GND
IN+
IN-
GND NC
NC
-
+
VOUT
5V
5V
LMH6514
www.ti.com
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
Figure 52. Internal Load Resistors Figure 53. Using High Gain Mode (400ΩLoad)
Figure 54. Using Low Gain Mode (200ΩLoad) Figure 55. Alternate Connection for Low Gain
Mode (200ΩLoad)
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LMH6514
LMH6514
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
www.ti.com
Table 2. Compatible High Speed Analog to Digital Converters
Product Number Max Sampling Rate (MSPS) Resolution Channels
ADC12L063 62 12 SINGLE
ADC12DL065 65 12 DUAL
ADC12L066 66 12 SINGLE
ADC12DL066 66 12 DUAL
CLC5957 70 12 SINGLE
ADC12L080 80 12 SINGLE
ADC12DL080 80 12 DUAL
ADC12C080 80 12 SINGLE
ADC12C105 105 12 SINGLE
ADC12C170 170 12 SINGLE
ADC12V170 170 12 SINGLE
ADC14C080 80 14 SINGLE
ADC14C105 105 14 SINGLE
ADC14DS105 105 14 DUAL
ADC14155 155 14 SINGLE
ADC14V155 155 14 SINGLE
ADC08D500 500 8 DUAL
ADC08500 500 8 SINGLE
ADC08D1000 1000 8 DUAL
ADC081000 1000 8 SINGLE
ADC08D1500 1500 8 DUAL
ADC081500 1500 8 SINGLE
ADC08(B)3000 3000 8 SINGLE
ADC08L060 60 8 SINGLE
ADC08060 60 8 SINGLE
ADC10DL065 65 10 DUAL
ADC10065 65 10 SINGLE
ADC10080 80 10 SINGLE
ADC08100 100 8 SINGLE
ADCS9888 170 8 SINGLE
ADC08(B)200 200 8 SINGLE
ADC11C125 125 11 SINGLE
ADC11C170 170 11 SINGLE
22 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6514
LMH6514
www.ti.com
SNOSB06A –JANUARY 2008–REVISED MARCH 2013
REVISION HISTORY
Changes from Original (March 2013) to Revision A Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 21
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LMH6514
PACKAGE OPTION ADDENDUM
www.ti.com 24-Sep-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6514SQ/NOPB ACTIVE WQFN RGH 16 1000 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L6514SQ
LMH6514SQE/NOPB ACTIVE WQFN RGH 16 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L6514SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Sep-2015
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6514SQ/NOPB WQFN RGH 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LMH6514SQE/NOPB WQFN RGH 16 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6514SQ/NOPB WQFN RGH 16 1000 210.0 185.0 35.0
LMH6514SQE/NOPB WQFN RGH 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
SEE TERMINAL
DETAIL
16X 0.3
0.2
2.6 0.1
16X 0.5
0.3
0.8 MAX
(A) TYP
0.05
0.00
12X 0.5
4X
1.5
B4.1
3.9 A
4.1
3.9 0.3
0.2
0.5
0.3
WQFN - 0.8 mm max heightRGH0016A
PLASTIC QUAD FLATPACK - NO LEAD
4214978/B 01/2017
DIM A
OPT 1 OPT 1
(0.1) (0.2)
PIN 1 INDEX AREA
0.08
SEATING PLANE
1
49
12
58
16 13
(OPTIONAL)
PIN 1 ID
0.1 C A B
0.05
EXPOSED
THERMAL PAD
17 SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
SCALE 3.000
DETAIL
OPTIONAL TERMINAL
TYPICAL
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
16X (0.25)
16X (0.6)
( 0.2) TYP
VIA
12X (0.5)
(3.8)
(3.8)
(1)
( 2.6)
(R0.05)
TYP
(1)
WQFN - 0.8 mm max heightRGH0016A
PLASTIC QUAD FLATPACK - NO LEAD
4214978/B 01/2017
SYMM
1
4
58
9
12
13
16
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
17
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
16X (0.6)
16X (0.25)
12X (0.5)
(3.8)
(3.8)
4X ( 1.15)
(0.675)
TYP
(0.675) TYP
(R0.05)
TYP
WQFN - 0.8 mm max heightRGH0016A
PLASTIC QUAD FLATPACK - NO LEAD
4214978/B 01/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
TYP
EXPOSED METAL
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
4
58
9
12
13
16
17
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