MICROCHIP 93LC46A/B 1K 2.5V Microwire Serial EEPROM FEATURES Single supply with operation down to 2.5V Low power CMOS technology - 1 mA active current (typical) - 1A standby current (maximum) 128 x 8 bit organization (93LC46A) 64 x 16 bit organization (93LC46B) Self-timed ERASE and WRITE cycles (including auto-erase) Automatic ERAL before WRAL * Power on/off data protection circuitry * Industry standard 3-wire serial interface * Device status signal during ERASE/WRITE cycles * Sequential READ function * 1,000,000 E/W cycles guaranteed * Data retention > 200 years 8-pin PDIP/SOIC and 8-pin TSSOP packages Available for the following temperature ranges: BLOCK DIAGRAM MEMORY NADDRESS ARRAY DECODER 4 ADDRESS COUNTER} OUTPUT *| BUFFER [2 DATA REGISTER MODE DECODE cs > LOGIC CLK CLOCK Voc GENERATOR Vss DESCRIPTION DI ~ Commercial (C): OC to +70C The Microchip Technology Inc. 93LC46AX/BX are 1K- ~ Industrial (1): 40C to +85C bit, low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 (93LC46A) or x16 bits (93LC46B). Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93LC46AX/BxX is available in standard 8-pin DIP, 8-pin surface mount SOIC, and TSSOP packages. The 93LC46AX/BX are offered only in a 150-mil SOIC package. PACKAGE TYPE DIP soic soic TSSOP cs ~ ~ 10 8 8h 1 sv cs Vv q 2 Wee csc! 2 8 vec = NCL 3 BTINc clk? Q 7feNC CLK [2 7 [Inc DI cas a Fa Nc U Q Nc? $5 7c veer 2 g 7 4ves DOrH4 EB Favss b DIT}3 2 6c @ = U z H oo? 2 Sane cscls x* 8 Epo 4 5(v ow a po Y LWss por] 4 5T ives cle 4 9% 5 py Microwire is a registered trademark of National Semiconductor Incorporated. 1998 Microchip Technology Inc. DS21173E-page 193LC46A/B 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratinqgs* VCC wee cececcene ene eeeeeeeaeeeeeeeeneeeaeeaeseesaseaaeeeeeesnaesaesaeteesaeneatenees 7.0V All inputs and outputs w.rt.Vss . -0.6V to Vec +1.0V Storage temperature 65C to +150C Ambient temp. with power applied.............. -65C to +125C Soldering temperature of leads (10 seconds)............. +300C ESD protection on all pins... ccc eceee reeset eer teeeeeees 4kV *Notice: Stresses above those listed under Maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri- ods may affect device reliability. TABLE 1-1 PIN FUNCTION TABLE Name Function cs Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output Vss Ground NC No Connect Vcc Power Supply TABLE 1-2 DC AND AC ELECTRICAL CHARACTERISTICS All parameters apply over the specified | Commercial (C): Vcc = +2.5V to +6.0V Tamb = 0C to +70C operating ranges unless otherwise Industrial (1): Vcc = +2.5V to +6.0V Tamb = -40C to +85C noted Parameter Symbol Min. Max. Units Conditions J J Vint 2.0 Veco +1 Vv 2.7V < VCC < 6.0V (Note 2) High level input voltage VIH2 0.7 Vcc Vee +1 Vv Vec <2.7V : vi -0.3 08 v Vcc > 2.7V (Note 2) Low level input voltage VIL2 -0.3 0.2 Vec Vv Vec <2.7V VoL1 _ 04 Vv loL = 2.1 mA; Vee = 4.5V Low level output voltage VoL2 _ 0.2 Vv OL =100 pA; Vee = Vcc Min. | VoH1 24 _ Vv IOH = -400 pA; Vee = 4.5V High level output voltage VOH2 Vec-0.2 _ Vv IOH = -100 pA; Vee = Vec Min. Input leakage current Iu -10 10 pA VIN = Vss to Vec Output leakage current ILo -10 10 pA VOUT = Vss to Vec Pin capacitance _ VIN/VoUT = 0 V (Notes 1 & 2) (all inputs/outputs) CIN, COUT 7 pF Tamb = +25C, FeLk = 1 MHz Icc write _ 15 mA Operating current \ d 1 mA FeLk = 2 MHz; Vcc = 6.0V Ce real 500 WA FOLK = 1 MHz: Voc = 3.0V Standby current Iccs _ 1 pA CS = Vss; DI = Vss 2 MHz Veco >4.5V Clock frequency Fe_k _ 1 MHz Voc <4.5V Clock high time TCKH 250 _ ns Clock low time TCKL 250 _ ns Chip select setup time Tess 50 _ ns Relative to CLK Chip select hold time TCSH 0 _ ns Relative to CLK Chip select low time TCsL 250 _ ns Data input setup time ToIs 100 _ ns Relative to CLK Data input hold time TDIH 100 _ ns Relative to CLK Data output delay time TPD _ 400 ns CL = 100 pF Data output disable time Tez _ 100 ns CL = 100 pF (Note 2) Status valid time Tsv _ 500 ns CL = 100 pF Twe _ 6 ms ERASE/WRITE mode Program cycle time TEC _ 6 ms ERAL mode TWL _ 15 ms WRAL mode Endurance _ 1M _ cycles 25C, Vcc = 5.0V, Block Mode (Note 3) Note 1: This parameter is tested at Tamb = 25C and Felk = 1 MHz. 2: This parameter is periodically sampled and not 100% tested. 3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which may be obtained on our website. DS21173E-page 2 1998 Microchip Technology Inc.93LC46A/B 2.0 2.1 PIN DESCRIPTION Chip Select (CS A high level selects the device; a low level deselects the device and forces it into standby mode. However, a pro- gramming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the pro- gramming cycle is completed. CS must be low for 250 ns minimum (TcsL) between consecutive instructions. If CS is low, the internal con- trol logic is held in a RESET status. Serial Clock (CLK) The Serial Clock is used to synchronize the communi- cation between a master device and the 93LC46AX/ BX. Opcodes, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. 2.2 CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a Don't Care if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a START condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detection of a START condition the specified num- ber of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Table 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected. 2.3 Data In (DI Data In (Dl) is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. 2.4 Data Out (DO) Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status informa- tion during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready. TABLE 2-1 INSTRUCTION SET FOR 93LC46A Instruction | SB | Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 AB AS A4 AB A2 Al AO _ (RDY/BSY) 10 ERAL 1 00 1 oO xX X X X X _ (RDY/BSY) 10 EWDS 1 00 0 O xX X X X X _ HIGH-Z 10 EWEN 1 00 1 1 xX X xX X X _ HIGH-Z 10 READ 1 10 AB AS A4 AB A2 Al AO _ D7 - DO 18 WRITE 1 01 AB AS A4 AB A2 Al AO D7 - DO (RDY/BSY) 18 WRAL 1 00 oO 1 % X X X X D7 - DO (RDY/BSY) 18 TABLE 2-2 INSTRUCTION SET FOR 93LC46B Instruction | SB | Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 A5 A4 AS8 A2 At AO _ (RDY/BSY) 9 ERAL 1 00 1 0 Xx Xx Xx Xx _ (RDY/BSY) 9 EWDS 1 00 0 0 Xx Xx Xx Xx _ HIGH-Z 9 EWEN 1 00 1 1 Xx Xx Xx Xx _ HIGH-Z 9 READ 1 10 A5 A4 AS8 A2 At AO _ D15- DO 25 WRITE 1 01 A5 A4 AS8 A2 At AO D15- DO (RDY/BSY) 25 WRAL 1 00 0 1 Xx Xx Xx Xx D15- DO (RDY/BSY) 25 1998 Microchip Technology Inc. DS21173E-page 393LC46A/B 3.0 FUNCTIONAL DESCRIPTION Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS. 3.1 START Condition The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device oper- ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as CS is high, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new START condition is detected. FIGURE 3-1: SYNCHRONOUS DATATIMING 3.2 Data In (Dl) and Data Out (DO) It is possible to connect the Data In (Dl) and Data Out (DO) pins together. However, with this configuration, if AO is a logic-high level, it is possible for a bus conflict to occur during the dummy zero that precedes the READ operation. Under such a condition the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driv- ing AO. The higher the current sourcing capability of AO, the higher the voltage at the DO pin. 3.3 Data Protection During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 2.2V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vec has fallen below 2.2V at nominal conditions. The ERASE/WRITE Disable (EWDS) and ERASE/ WRITE Enable (EWDS) commands give additional pro- tection against accidentally programming during nor- mal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. cs VIH VIL VIH CLK VIL VIH DI VIL DO VOH (READ) Vo Do VOH (PROGRAM) ,,., Note: AC Test Conditions: VIL = 0.4V, VIH =2.4V STATUS VALID DS21173E-page 4 1998 Microchip Technology Inc.93LC46A/B 3.4 ERASE The ERASE instruction forces all data bits of the spec- ified address to the logical 1 state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical O indicates that program- ming is still in progress. DO at logical 1 indicates that the register at the specified address has been erased and the device is ready for another instruction. FIGURE 3-2: ERASE TIMING 3.5 Erase All (ERAL) The Erase All (ERAL) instruction will erase the entire memory array to the logical 1 state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire ERAL cycle is com- plete. TCSL ff N V WF CHECK STATUS 9 L z DO ff BUSY Twe FIGURE 3-3: ERALTIMING TCSL ft cs \ VY as / N_A CHECK STATUS ol L, ns HIGH-Z a LL SN DO Guaranteed at Vcc = 4.5V to +6.0V. 1998 Microchip Technology Inc. DS21173E-page 593LC46A/B 3.6 ERASE/WRITE Disable and Enable (EWDS/EWEN) The 93LC46A/B powers up in the ERASE/WRITE Dis- able (EWDS) state. All programming modes must be preceded by an ERASE/WRITE Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruc- tion is executed or Vcc is removed from the device. To protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming opera- tions. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. FIGURE 3-4: EWDSTIMING 3.7 READ The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (93LC46A) or 16-bit (93LC46B) output string. The output data bits will tog- gle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is pos- sible when CS is held high. The memory data will auto- matically cycle to the next register and output sequentially. DI 1 0 0 (0 0 L. Test, | a LL. Ss FIGURE 3-5: EWENTIMING DI L. Test, | FIGURE 3-6: READTIMING cs / fi DO HIGH-Z nm ang pen ~ DS21173E-page 6 1998 Microchip Technology Inc.93LC46A/B 3.8 WRITE The WRITE instruction is followed by 8 bits (93LC46A) or 16 bits (93LC46B) of data which are written into the specified address. After the last data bit is put on the Dl pin, the falling edge of CS initiates the self-timed auto- erase and programming cycle. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical O indicates that programming is still in progress. DO at logical 1 indicates that the register at the specified address has been written with the data specified and the device is ready for another instruc- tion. FIGURE 3-7: WRITETIMING 3.9 Write All (WRAL) The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and com- mences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). ~_ 9D a HIGH-Z ol LL - FLL TCSsL DO FIGURE 3-8: WRALTIMING TCSL, HIGH-Z DO Guaranteed at Vcc = 4.5V to +6.0V. 1998 Microchip Technology Inc. DS21173E-page 793LC46A/B NOTES: DS21173E-page 8 1998 Microchip Technology Inc.93LC46A/B NOTES: 1998 Microchip Technology Inc. DS21173E-page 993LC46A/B NOTES: DS21173E-page 10 1998 Microchip Technology Inc.93LC46A/B 93LC46A/B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 93LC46A/B /P i P SN = SM = Package: ST | Temperature 93LC46A 93LC46AT 938LC46AX 93LC46AXT Device: 93LC46B 93LC46BT 93LC46BX 93LC46BXT Blank = Range: I= Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (208 mil Body), 8-lead TSSOP, 8-lead OC to +70C -40C to +85C 1K Microwire Serial EEPROM (x8) 1K Microwire Serial EEPROM (x8) Tape and Reel 1K Microwire Serial EEPROM (x8) in alternate pinout (SN only) 1K Microwire Serial EEPROM (x8) in alternate pinout, Tape and Reel (SN only) 1K Microwire Serial EEPROM (x16) 1K Microwire Serial EEPROM (x16) Tape and Reel 1K Microwire Serial EEPROM (x16) in alternate pinout (SN only) 1K Microwire Serial EEPROM (x16) in alternate pinout, Tape and Reel (SN only) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com) 1998 Microchip Technology Inc. DS21173E-page 11MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http ://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588 Dayton Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 6/11/98 The Netherlands DNV Corngation, Inc. DNV MSC of ED on Accredited by the RvA Ai iS > ANSI-RAB Chet? PNW) REGISTERED. FIRM Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PiCmicro 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (1SO). All rights reserved. 1998, Microchip Technology Incorporated, USA. 7/98 > Printed on recycled paper. Tnfomraticn contaired in this publication regarding device applications ard the like is intercd for suogestion only and may be suparsaded by updates. Nb representation or warranty is given ard no liability is assured by Microchip Tacmollogy Thoorporated with respact to the accuracy or use of such infomation, or infrirgarent of intellectual or otherwise. Use of Microchips products as critical components in life suport systats is rot authorized exogt with express written agoroval by Microchip. Nb licenses are cxneyed, inplicitly or otherwise, under arly intellectual proparty rights. The Microdnip Jogo ard nane are registered tradstarks of Microchip Tecrology Ihe. in the U.S.A. and cther cuntries. All rights reserved All cthar traderarks menticred herein are the property of their respective camanies. patents or other proparty rights arising fron such use DS21173E-page 12 1998 Microchip Technology Inc.