Spartan -II 2.5V FPGA Family: DC a nd Switching Characteristics
Modu le 3 of 4 www.xilinx.com DS001-3 (v 2.4) August 28, 2001
10 1-800-255-7778 Preliminary Product Specification
R
Calculation of TIOOP as a Function of
Capacitance
TIOOP is the prop agation d elay from the O Input of the IOB
to the pad. The value s for T IOOP a re based on the standard
capacitive load (CSL) for each I/O standard as listed in the
table C onsta nts f or Calculat i ng TIOOP, below.
F or other capacitive l oads, use the formulas below to calcu-
late an adjusted propagation delay, TIOOP1.
TIOOP1 = TIOOP + A d j + (C LOAD – CSL) * FL
Where:
Adj is select ed from IOB Output Delay
Adjustments for Different Stand ards,
page 9, according to the I/O standard used
CLOAD is the capacitive load for th e design
FLis the c apacitanc e scaling factor
Delay Measurement Methodology
Standard VL(1) VH(1) Meas.
Point VREF
Typ(2)
LVTTL 0 3 1.4 -
LVCMOS2 0 2.5 1.125 -
PCI33_5 Per PCI Spec -
PCI33_3 Per PCI Spec -
PCI66_3 Per PCI Spec -
GTL VREF – 0.2 VREF + 0. 2 V REF 0.80
GTL+ VREF – 0.2 VREF + 0.2 VREF 1.0
HSTL Class I VREF – 0.5 VREF + 0.5 V REF 0.75
HSTL Class III VREF – 0.5 V REF + 0.5 VREF 0.90
HSTL Class IV VREF – 0.5 VREF + 0. 5 V REF 0.90
SSTL3 I and II VREF – 1.0 V REF + 1.0 VREF 1.5
SSTL2 I and II VREF – 0.75 VREF + 0.75 VREF 1.25
CTT VREF – 0.2 VREF + 0.2 V REF 1.5
AGP VREF –
(0.2xVCCO)VREF +
(0.2xVCCO)VREF Per AGP
Spec
Notes:
1. Input wavefor m swi tches between VL and V H.
2. Meas urements are made at VREF Typ, Maximum, and
Minimum. Worst-case values are reported.
3. I/O param eter mea surements are made with the capacitance
values shown in the previous table, Constants for
Calcul ating TIOOP. See Xilinx application note XAPP179 for
the appropriat e termina ti ons.
4. I/O standard measurements are reflected in the IBIS model
informati on except where th e IBIS format pre cludes it.
Constants for Calcul ating TIOOP
Standard CSL(1)
(pF) FL
(ns/pF)
LVTTL Fast Slew Rate, 2 mA drive 35 0.41
LVTTL Fast Slew Rate, 4 mA drive 35 0.20
LVTTL Fast Slew Rate, 6 mA drive 35 0.13
LVTTL Fast Slew Rate, 8 mA dr ive 35 0.079
LVTTL Fast Slew Rate, 12 mA dr ive 35 0.044
LVTTL Fast Slew Rate, 16 mA dr ive 35 0.043
LVTTL Fast Slew Rate, 24 mA dr ive 35 0.033
LVTTL Slow Slew Rate, 2 mA driv e 35 0.41
LVTTL Slow Slew Rate, 4 mA driv e 35 0.20
LVTTL Slow Slew Rate, 6 mA drive 35 0.100
LVTTL Slow Slew Rate, 8 mA drive 35 0.086
LVTTL Slow Slew Rate, 12 mA drive 35 0.058
LVTTL Slow Slew Rate, 16 mA drive 35 0.050
LVTTL Slow Slew Rate, 24 mA drive 35 0.048
LVCMOS2 35 0.041
PCI 33 MHz 5V 50 0.050
PCI 33 MHZ 3.3V 10 0.050
PCI 66 MHz 3.3V 10 0.033
GTL 0 0.014
GTL+ 0 0.017
HSTL Class I 20 0.022
HSTL Class III 20 0.016
HSTL Class IV 20 0.014
SSTL2 Class I 30 0.028
SSTL2 Class II 30 0.016
SSTL3 Class I 30 0.029
SSTL3 Class II 30 0.016
CTT 20 0.035
AGP 10 0.037
Notes:
1. I/ O par ameter measuremen ts are made with the cap acitance
valu es shown abov e. See Xilinx application note XAPP179
for the appropriat e termin ati ons.
2. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.