2N7002K - Fairchild Semiconductor

2N7002K — N-Channel Enhancement Mode Field Effect Transistor

2N7002K Rev. 1.1.0

September 2014

2N7002K

N-Channel Enhancement Mode Field Effect Transistor

Features

• Low On-Resistance

• Low Gate Threshold Voltage

• Low Input Capacitance

• Fast Switching Speed

• Low Input / Output Leakage

• Ultra-Small Surface Mount Package

• Pb Free / RoHS Compliant

• ESD HBM = 2000 V (Typical: 3000 V) as per JESD22 A114

and ESD CDM = 2000 V as per JESD22 C101

Ordering Information

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-

ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-

tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The

absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted.

Part Number Top Mark Package Packing Method

2N7002K 7K SOT-23 3L Tape and Reel

Symbol Parameter Value Unit

VDSS Drain-Source Voltage 60 V

VDGR Drain-Gate Voltage (RGS ≤ 1.0 MΩ) 60 V

VGSS Gate-Source Voltage ±20 V

IDDrain Current Continuous 300 mA

Pulsed 800

TJOperating Junction Temperature Range -55 to +150 °C

TSTG Storage Temperature Range -55 to +150 °C

SOT-23

Marking: 7K

2N7002K — N-Channel Enhancement Mode Field Effect Transistor

2N7002K Rev. 1.1.0 2

Thermal Characteristics

Values are at TA = 25°C unless otherwise noted.

Note:

1. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch. Minimum land pad size.

Electrical Characteristics

Values are at TA = 25°C unless otherwise noted.

Note:

2. Short duration test pulse used to minimize self-heating effect.

Symbol Parameter Value Unit

Total Power Dissipation 350 mW

Derate Above TA = 25°C 2.8 mW/°C

RθJA Thermal Resistance, Junction-to-Ambient(1) 350 °C/W

Symbol Parameter Conditions Min. Max. Unit

Off Characteristics(2)

BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 10 μA60 V

IDSS Zero Gate Voltage Drain Current

VDS = 60 V, VGS = 0 V 1.0

μA

VDS = 60 V, VGS = 0 V,

TJ = 125°C500

IGSS Gate-Body Leakage VGS = ±20 V, VDS = 0 V ±10 μA

On Characteristics(2)

VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 μA1.0 2.5 V

RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 0.5 A 2 Ω

VGS = 4.5 V, ID = 200 mA 4

ID(ON) On-State Drain Current VGS = 10 V, VDS = 7.5 V 1.5 A

gFS Forward Transconductance VDS = 10 V, ID = 0.2 A 200 mS

Dynamic Characteristics

Ciss Input Capacitance

VDS = 25 V, VGS= 0 V,

f = 1.0 MHz

50 pF

Coss Output Capacitance 15 pF

Crss Reverse Transfer Capacitance 6 pF

Switching Characteristics

tD(ON) Turn-On Delay Time VDD = 30 V, IDSS = 200 mA,

RG = 10 Ω, VGS = 10 V

5ns

tD(OFF) Turn-Off Delay Time 30 ns

2N7002K — N-Channel Enhancement Mode Field Effect Transistor

2N7002K Rev. 1.1.0 3

Typical Performance Characteristics

Figure 1. On-Region Characteristics Figu re 2. On-Resistance Vari ation with Ga te Voltage

and Drain Current

Figure 3. On-Resistance Variation with Temperature Figure 4. On-Resistance Variation

with Gate-Source Voltage

Figure 5. Transfer Characteristics Figure 6. Gate Threshold Variation with Temperature

0246810

0.0

0.5

1.0

1.5

2.0

VGS = 10V

ID. DRAIN-SOURCE CURRENT(A)

VDS. DRAIN-SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0

0.5

1.0

1.5

2.0

2.5

3.0

(Ω)

10V

4.5V

VGS = 3V

RDS(on),

DRANI-SOURCE ON-RESISTANCE

ID. DRAIN-SOURCE CURRENT(A)

-50 0 50 100 150

0.5

1.0

1.5

2.0

2.5

3.0

(Ω)

VDS = 10V

ID = 500 mA

RDS(on)

DRANI-SOURCE ON-RESISTANCE

TJ. JUNCTION TEMPERATURE(oC)

23456

0.0

0.2

0.4

0.6

0.8

1.0

VDS = 10V

75(oC)

125(oC)

150(oC)

25(oC)

TJ = -25(oC)

ID. DRAIN-SOURCE CURRENT(A)

VGS. GATE-SOURCE VOLTAGE (V)

-50 0 50 100 150

1.0

1.2

1.4

1.6

1.8

2.0

ID = 0.25 mA

ID = 1 mA

VDS = VGS

Vth, Gate-Source Threshold Voltage (V)

TJ. JUNCTION TEMPERATURE(oC)

2N7002K — N-Channel Enhancement Mode Field Effect Transistor

2N7002K Rev. 1.1.0 4

Typical Performance Characteristics (Continued)

Figure 7. Reverse Drain Current Variation with Diode

Forward Voltage and Temperature Figure 8. Gate Charge Characteristics

Figure 9. Maximum Safe Operating Area

0.00.20.40.60.81.0

100

-55oC

VGS = 0 V

TA=150oC

25oC

IS Reverse Drain Current, [mA]

VSD, Body Diode Forward Voltage [V]

Qg - Gate Charge

VGS, GATE-SOURCE VOLTAGE (V)

500mA

115mA

280mA

0.005

0.05

0.5

0.01 0.1 1 10 100

VDS, DRAIN-SOURCE VOLT AGE (V)

10s

100ms

RDS(ON) LIMIT

SINGLE PULSE

R JA = 350oC/W

TA= 25oC

10ms

1ms

100 s

200

ID, DRAIN CURRENT (A)

2N7002K — N-Channel Enhancement Mode Field Effect Transistor

2N7002K Rev. 1.1.0 5

Physical Dimensions

Figure 10. 3-LEAD, SOT23, JEDEC TO-236, LOW PROFILE

LAND PATTERN

RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) REFERENCE JEDEC REGISTRATION

TO-236, VARIATION AB, ISSUE H.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE INCLUSIVE OF BURRS,

MOLD FLASH AND TIE BAR EXTRUSIONS.

D) DIMENSIONING AND TOLERANCING PER

ASME Y14.5M - 1994.

E) DRAWING FILE NAME: MA03DREV10

SEE DETAIL A

SEATING

PLANE

SCALE: 2X

GAGE PLANE

(0.55)

(0.93)

1.20 MAX

0.10

0.00

0.10 C

2.40±0.30

2.92±0.20

1.30+0.20

-0.15

0.60

0.37

0.20 A B

1.90

0.95

(0.29)

0.95

1.40

2.20

1.00

1.90

0.25

0.23

0.08

0.20 MIN

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The datasheet is for reference information only.

Rev. I71

Mouser Electronics

Authorized Distributor

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