30 V, Low Noise, Rail-to-Rail I/O,
Low Power Operational Amplifiers
Data Sheet ADA4084-2/ADA4084-4
Rev. D Document Feedback
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FEATURES
Rail-to-rail input/output
Low power: 0.625 mA typical per amplifier at ±15 V
Gain bandwidth product: 15.9 MHz at AV =100 typical
Unity-gain crossover: 9.9 MHz typical
−3 dB closed-loop bandwidth: 13.9 MHz typical at ±15 V
Low offset voltage: 100 μV maximum (SOIC)
Unity-gain stable
High slew rate: 4.6 V/μs typical
Low noise: 3.9 nV/√Hz typical at 1 kHz
APPLICATIONS
Battery-powered instrumentation
High-side and low-side sensing
Power supply control and protection
Telecommunications
DAC output amplifiers
ADC input buffers
GENERAL DESCRIPTION
The ADA4084-2 (dual) and ADA4084-4 (quad) are single-supply,
10 MHz bandwidth amplifiers featuring rail-to-rail inputs and
outputs. They are guaranteed to operate from 3 V to 30 V (or
±1.5 V to ±15 V).
These amplifiers are well suited for single-supply applications
requiring both ac and precision dc performance. The combina-
tion of wide bandwidth, low noise, and precision makes the
ADA4084-2 and ADA4084-4 useful in a wide variety of
applications, including filters and instrumentation.
Other applications for these amplifiers include portable telecom-
munications equipment, power supply control and protection,
and use as amplifiers or buffers for transducers with wide output
ranges. Sensors requiring a rail-to-rail input amplifier include
Hall effect, piezoelectric, and resistive transducers.
The ability to swing rail-to-rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.
The ADA4084-2 and ADA4084-4 are specified over the
industrial temperature range of −40°C to +125°C. The dual
ADA4084-2 is available in the 8-lead SOIC, MSOP, and LFCSP
surface-mount packages, and the ADA4084-4 is offered in the
14-lead TSSOP and 16-lead LFCSP.
The ADA4084-2 and ADA4084-4 are members of a growing
series of high voltage, low noise op amps offered by Analog
Devices, Inc., (see Table 1).
PIN CONFIGURATIONS
Figure 1. 8-Lead MSOP (RM), 8-Lead SOIC (R), 8-Lead LFCSP (CP)
Figure 2. 14-Lead TSSOP (RU)
Figure 3. 16-Lead LFCSP (CP)
For a more complete selection table of low input voltage noise
amplifiers, see the AN-940 Application Note, Low Noise Amplifier
Selection Guide for Optimal Noise Performance, available at
www.analog.com.
Table 1. Low Noise Op Amps
Voltage Noise Single Dual Quad
1.1 nV/Hz AD8597 AD8599
1.8 nV/Hz ADA4004-1 ADA4004-2 ADA4004-4
2.8 nV/Hz Rail-to-Rail Output AD8675 AD8676
2.8 nV/Hz AD8671 AD8672 AD8674
3.2 nV/Hz OP27/OP37
3.9 nV/Hz Rail-to-Rail
Input/Output
ADA4084-2 ADA4084-4
1
2
3
4
8
7
6
5
OUT B
–IN B
+IN B
V+
O
UT A
–IN A
+IN A
V–
ADA4084-2
TOP VI EW
(Not to S cal e)
NOTES
1. FOR THE LF CSP PACKAGE TH
E
EXPOS ED PAD MUST BE
CONNECTED TO V–.
08237-001
OUT B 78
+IN B 510
–IN B 69
V+ 411
–IN A 213
+IN A 312
OUT A 114
OUT C
+IN C
–IN C
V–
–IN D
+IN D
OUT D
ADA4084-4
08237-102
12
11
10
1
3
4
–IN D
+IN D
V–
9+IN C
–IN A
V+
2
+IN A
+IN B
6
OUT B
5
–IN B
7
OUT C
8
–IN C
16 NIC
15 OUT A
14 OUT D
13 NIC
TOP
VIEW
ADA4084-4
NOTES
1. NIC = NOT I NTE RNALL Y CONNE CT ED.
2. FOR THE L FCSP PACKAGE THE EXPOSED PAD
MUST B E CO NN ECTED T O V–.
08237-103
IMPORTANT LINKS for the ADA4084-2_4084-4*
Last content update 12/03/2013 04:11 pm
SIMILAR PRODUCTS & PARAMETRIC SELECTION TABLES
ADA4077-2:
available as a dual channel version in two grades offering lower offset
and drift with higher linearity within the Input Voltage Range for dual
supply applications.
ADA4500-2:
offers similar speed and precision in a high linearity, zero-crossover,
5V Op Amp.
ADA4096-2
a lower power, 30V, rail-to-rail input/output Op Amp.
Find Similar Products By Operating Parameters
SAR ADC & Driver Quick-Match Guide
DOCUMENTATION
AN-940: Low Noise Amplifier Selection Guide for Optimal Noise
Performance
AN-849: Using Op Amps as Comparators
Op Amp Applications Handbook
MT-054: Precision Op Amps
MT-052: Op Amp Noise Figure: Don't Be Mislead
MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and
Equivalent Noise Bandwidth
MT-047: Op Amp Noise
MT-035: Op Amp Inputs, Outputs, Single-Supply, and Rail-to-Rail
Issues
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
OpAmp Error Budget Calculator
ADIsimOpAmp™
Analog Bridge Wizard
ADA4084 SPICE Macro Model
EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Boards and Kits page for the ADA4084-2
View the Evaluation Boards and Kits page for the ADA4084-4
Symbols and Footprints for the ADA4084-2
Symbols and Footprints for the ADA4084-4
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Quality and Reliability
Lead(Pb)-Free Data
SAMPLE & BUY
ADA4084-2
ADA4084-4
View Price & Packaging
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* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
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ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ............................................. 7
±1.5 V Characteristics .................................................................. 7
±5 V Characteristics ................................................................... 12
±15 V Characteristics ................................................................ 17
Applications Information .............................................................. 23
Functional Description .............................................................. 23
Start-Up Characteristics ............................................................ 24
Input Protection ......................................................................... 24
Output Phase Reversal ............................................................... 24
Designing Low Noise Circuits in Single-Supply
Applications ................................................................................ 25
Comparator Operation .............................................................. 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 28
REVISION HISTORY
11/13—Rev. C to Rev. D
Added 14-Lead TSSOP and 16-Lead LFCSP
Packages ............................................................................... Universal
Added ADA4804-4 ............................................................. Universal
Change to Features Section and Applications Section ................ 1
Added Figure 2 and Figure 3; Renumbered Sequentially ........... 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4 ............................................................................ 5
Changes to Table 5 and Table 6 ....................................................... 6
Changes to Typical Performance Characteristics Section ........... 7
Added Figure 101 ........................................................................... 27
Added Figure 102; Changes to Ordering Guide ......................... 28
4/13—Rev. B to Rev. C
Changes to Figure 48 Caption....................................................... 15
Updated Outline Dimensions ....................................................... 25
6/12—Rev. A to Rev. B
Added LFCSP Package ....................................................... Universal
Changes to Figure 1 .......................................................................... 1
Changes to Output Voltage High Parameter, Table 4 .................. 5
Added Figure 5 and Figure 7, Renumbered Sequentially ........... 7
Added Figure 30 and Figure 32 .................................................... 12
Added Figure 55 and Figure 57 .................................................... 17
Added Startup Characteristics Section ........................................ 23
Moved Figure 78 ............................................................................. 23
Changes to Output Phase Reversal Section and Comparator
Operation Section........................................................................... 24
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 26
2/12—Rev. 0 to Rev. A
Changes to Data Sheet Title ............................................................. 1
Changes to Voltage Range in General Description ....................... 1
Changes to Supply Current/Amplifier Parameter, Table 2 .......... 3
Changes to Common-Mode Rejection Ratio Parameter, Table 3 .. 4
Changes to Common-Mode Rejection Ratio Parameter, Table 4 .. 5
Changes to Figure 2 ........................................................................... 6
Changes to Figure 24...................................................................... 10
Changes to Figure 32...................................................................... 12
Changes to Figure 47...................................................................... 14
Changes to Figure 55...................................................................... 16
Changes to Figure 62...................................................................... 17
Changes to Figure 73...................................................................... 20
10/11—Revision 0: Initial Version
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 3 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSY = 3 V, V CM =1.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS SOIC package 20 100 μV
−40°C ≤ TA ≤ +125°C 200 μV
MSOP, TSSOP packages 50 130 μV
−40°C ≤ TA ≤ +125°C 250 μV
ADA4084-2 LFCSP package
80
200
−40°C ≤ TA ≤ +125°C 300 μV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.5 1.75 µV/°C
Offset Voltage Matching TA = 25°C 150 μV
ADA4084-4 LFCSP package 200 μV
Input Bias Current
I
B
140
250
–40°C ≤ TA ≤ +125°C 400 nA
Input Offset Current IOS 5 25 nA
–40°C ≤ T
A
≤ +125°C
50
Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 3 V 64 88 dB
−40°C ≤ TA ≤ +125°C 60 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, 0.5 V ≤ VO ≤ 2.5 V 100 104 dB
R
L
= 2 kΩ, −40°C ≤ T
A
≤ +125°C
97
Input Impedance, Differential 100||1.1 kΩ||pF
Input Impedance, Common Mode 80||2.9 MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
R
L
= 10 kΩ to V
CM
2.9
2.95
–40°C ≤ TA ≤ +125°C 2.8 V
RL = 2 kΩ to VCM 2.85 2.9 V
–40°C ≤ TA ≤ +125°C 2.7 V
Output Voltage Low VOL RL = 10 kΩ to VCM 10 20 mV
–40°C ≤ T
A
≤ +125°C
40
RL = 2 kΩ to VCM 20 30 mV
–40°C ≤ TA ≤ +125°C 50 mV
Short-Circuit Current ISC −17/+10 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, A = +1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±1.25 V to ±1.75 V 100 110 dB
–40°C ≤ TA ≤ +125°C 90 dB
Supply Current/Amplifier ISY IO = 0 mA 0.565 0.650 mA
–40°C ≤ T
A
≤ +125°C
0.950
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 2.0 2.6 V/µs
Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 15.4 MHz
Unity-Gain Crossover
UGC
V
IN
= 5 mV p-p, R
L
= 10 kΩ, A
V
= 1
8.08
Phase Margin ΦM 86 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 12.3 MHz
Settling Time tS AV = 10, VIN = 2V p-p; 0.1% 4 µs
Total Harmonic Distortion Plus Noise THD + N VIN = 300 mV rms, RL = 2 kΩ, f = 1 kHz 0.009 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.14 μV p-p
Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz
Current Noise Density in f = 1 kHz 0.55 pA/√Hz
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 4 of 28
VSY = ±5.0 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS SOIC package 30 100 μV
−40°C ≤ TA ≤ +125°C 250 μV
MSOP, TSSOP packages
60
130
μV
−40°C ≤ TA ≤ +125°C 250 μV
ADA4084-2 LFCSP package 90 200 μV
−40°C ≤ TA ≤ +125°C 300 μV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.5 1.75 μV/°C
Offset Voltage Matching
T
A
= 25°C
150
μV
ADA4084-4 LFCSP package 200 μV
Input Bias Current IB 140 250 nA
−40°C ≤ TA ≤ +125°C 400 nA
Input Offset Current IOS 5 25 nA
−40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range −5 +5 V
Common-Mode Rejection Ratio CMRR VCM = ±4 V, −40°C ≤ TA ≤ +125°C 106 124 dB
VCM = ±5 V 76 dB
VCM = ±5 V−40°C ≤ TA ≤ +125°C 70 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, −4 V ≤ VO ≤ 4 V 108 112 dB
RL = 2 kΩ, −40°C ≤ TA ≤ +125°C 103 dB
Input Impedance, Differential 100||1.1 kΩ||pF
Input Impedance, Common Mode 200||2.5 MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 4.9 4.95 V
−40°C ≤ TA ≤ +125°C 4.8 V
RL = 2 kΩ to VCM 4.8 4.85 V
−40°C ≤ TA ≤ +125°C 4.7 V
Output Voltage Low VOL RL = 10 kΩ to VCM −4.95 −4.9 V
−40°C ≤ TA ≤ +125°C −4.8 V
RL = 2 kΩ to VCM −4.95 −4.8 V
−40°C ≤ TA ≤ +125°C −4.7 V
Short-Circuit Current ISC −24/+17 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, A = +1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±2 V to ±18 V 110 120 dB
−40°C ≤ TA ≤ +125°C 105 dB
Supply Current/Amplifier
I
SY
I
O
= 0 mA
0.595
0.700
mA
−40°C ≤ TA ≤ +125°C 1.00 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ to VCM 2.4 3.7 V/µs
Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 15.9 MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 9.6 MHz
Phase Margin ΦM 85 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 13.9 MHz
Settling Time tS AV = 10, VIN = 8V p-p; 0.1% 4 µs
Total Harmonic Distortion Plus Noise
THD + N
V
IN
= 2 V rms, R
L
= 2 kΩ, f = 1 kHz
0.003
%
NOISE PERFORMANCE
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
0.14
µV p-p
Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz
Current Noise Density in 0.55 pA/√Hz
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 5 of 28
VSY = ±15.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS SOIC package 40 100 μV
−40°C ≤ TA ≤ +125°C 200 μV
MSOP, TSSOP packages
70
130
μV
−40°C ≤ TA ≤ +125°C 250 μV
ADA4084-2 LFCSP package 100 200 μV
−40°C ≤ TA ≤ +125°C 300 μV
Offset Voltage Drift ΔVOS/ΔT 0.5 1.75 μV/°C
Offset Voltage Matching
T
A
= 25°C
150
μV
ADA4084-4 LFCSP package 200 μV
Input Bias Current IB 140 250 nA
−40°C ≤ TA ≤ +125°C 400 nA
Input Offset Current IOS 5 25 nA
−40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range −15 +15 V
Common-Mode Rejection Ratio CMRR VCM = ±14 V, −40°C ≤ TA ≤ +125°C 106 124 dB
VCM = ±15 V 85 dB
VCM = ±15 V,−40°C ≤ TA ≤ +125°C 80 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, −13.5 V ≤ VO ≤ +13.5 V 110 117 dB
−40°C ≤ TA ≤ +125°C 105 dB
Input Impedance, Differential 100||1.1 kΩ||pF
Input Impedance, Common Mode 200||2.5 MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 14.85 14.9 V
−40°C ≤ TA ≤ +125°C 14.8 V
RL = 2 kΩ to VCM 14.5 14.6 V
−40°C ≤ TA ≤ +125°C 14.0 V
Output Voltage Low VOL RL = 10 kΩ to VCM −14.95 −14.9 V
−40°C ≤ TA ≤ +125°C −14.8 V
RL = 2 kΩ to VCM −14.9 −14.80 V
−40°C ≤ TA ≤ +125°C −14.7 V
Short-Circuit Current ISC ±30 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, A = +1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±2 V to ±18 V 110 120 dB
−40°C ≤ TA ≤ +125°C 105 dB
Supply Current/Amplifier
I
SY
I
O
= 0 mA
0.625
0.750
mA
−40°C ≤ TA ≤ +125°C 1.050 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 2.4 4.6 V/µs
Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 15.9 MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 9.9 MHz
Phase Margin ΦM 86 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 13.9 MHz
Settling Time tS AV = 10, VIN = 10V p-p; 0.1% 4 µs
Total Harmonic Distortion Plus Noise
THD + N
V
IN
= 5 V rms, R
L
= 2 kΩ, f = 1 kHz
0.003
%
NOISE PERFORMANCE
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
0.1
µV p-p
Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz
Current Noise Density in 0.55 pA/√Hz
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage ±18 V
Input Voltage V− ≤ VIN ≤ V+
Differential Input Voltage1 ±0.6 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
ESD
Human Body Model2 4.5 kV
Machine Model3 1.25 kV
Field-Induced Charged-Device Model
(FICDM)4
200 V
1 For input differential voltages greater than 0.6 V, limit the input current to
less than 5 mA to prevent degradation or destruction of the input devices.
2 Applicable standard: MIL-STD-883, Method 3015.7.
3 Applicable standard: JESD22-A115-A (ESD machine model standard of
JEDEC).
4 Applicable standard: JESD22-C101-C (ESD FICDM standard of JEDEC).
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the device soldered on a 4-layer JEDEC
standard printed circuit board (PCB) with zero airflow.
Table 6. Thermal Resistance
Package Type θJA θ
JC Unit
8-Lead SOIC-N (R-8) 121 43 °C/W
8-Lead MSOP (RM-8) 142 45 °C/W
8-Lead LFCSP1, 3 (CP-8-12) 84 40 °C/W
14-Lead TSSOP (RU-14) 112 43 °C/W
16-Lead LFCSP (CP-16-26)2, 3 55 30 °C/W
1 Values are based on 4-layer (2S2P) JEDEC standard PCB, with four thermal
vias. Exposed pad soldered to PCB.
2 Values are based on 4-layer (2S2P) JEDEC standard PCB, with nine thermal
vias. Exposed pad soldered to PCB.
3 θJC measured on top of package.
ESD CAUTION
Figure 4. Simplified Schematic
D2
D101
D100
D5 D4
D1
Q1
Q4 Q3
Q24
Q21
D20
Q13
Q18
Q19
Q23
Q2
FOLDED
CASCADE
V
EE
V
OUT
V
CC
V
BIAS
MIRROR
08237-002
R4
R5
R6
R7 C2
C1
R1 R2
R3
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 7 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
±1.5 V CHARACTERISTICS
Figure 5. Input Offset Voltage Distribution, SOIC
Figure 6. Input Offset Voltage Distribution, MSOP and TSSOP
Figure 7. Input Offset Voltage Distribution, ADA4084-2 LFCSP
Figure 8. TCVOS Distribution, SOIC, MSOP, and TSSOP
Figure 9. TCVOS Distribution, LFCSP
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
120
0
–100 –50 500100
NUMBER OF AM P LI FIE RS
VOS (µV)
20
40
60
80
100
VSY = ± 1.5V
TA = 25° C
RL = ∞
–25 25–75 75
08237-003
50
0
–100 –50 –25 25–75 75500100
NUMBER OF AM P LI FIE RS
VOS (µV)
VSY = ± 1.5V
TA = 25° C
RL = ∞
5
10
15
20
25
30
35
40
45
08237-004
0
50
100
150
200
–200 –150 –100 –50 050 100
NUMBER OF AMPLIFIERS
V
OS
(µV)
08237-081
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
60
002.0
NUMBER OF AM P LI FIE RS
TCV
OS
(µV/°C)
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
10
20
30
40
50
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
08237-005
0
5
10
15
20
25
30
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
NUMBER OF AMPLIFIERS
TCV
OS
(µV/°C)
08237-082
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
500
–500 00.50 0.75 1.00 1.25 1.500.25 3.002.752.502.252.001.75
INPUT OFFSET VOLTAGE (µV)
COMMON-MODE VOLT AGE (V)
–400
–300
–200
–100
0
100
200
300
400
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
08237-006
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 8 of 28
Figure 11. Input Offset Voltage vs. Temperature
Figure 12. Input Bias Current vs. Temperature
Figure 13. Input Bias Current vs. VCM and Temperature
Figure 14. Dropout Voltage vs. Source Current
Figure 15. Dropout Voltage vs. Sink Current
Figure 16. Open-Loop Gain and Phase vs. Frequency
–100
–75
–50
–25
0
25
50
75
100
–50–25 0 25 50 75 100125150
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
08237-108
V
SY
= ±1. 5V
–50
–100
–150
–200
–250
–40 125
INP UT BIAS ( nA)
TEMPERATURE (°C)
–25 –10 520 35 50 65 80 95 110
VSY = ± 1.5V
VCM = 0V
RL = ∞
IB+
IB–
08237-007
600
–600
–1.5 –1.0 1.0–0.5 0.501.5
INP UT BIAS ( nA)
V
CM
(V)
–400
–200
0
200
400
T
A
= +85°C
T
A
= +25°C
T
A
= +125°C
T
A
= –40° C
V
SY
= ±1. 5V
08237-008
1000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SO URCE CURRE NT (mA)
V
SY
= ±1. 5V
T
A
= 25° C
(V+) – V
OH
08237-009
1000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SI NK CURRE NT (mA)
V
SY
= ±1. 5V
T
A
= 25° C
V
OL
– (V–)
08237-010
120
–40
270
–90
0.1 100k
GAIN (d B)
PHASE ( Degrees)
FRE QUENCY ( kHz )
–45
0
45
90
135
180
225
–20
20
0
40
60
80
100
110 100 1k 10k
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= 10kΩ
08237-011
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 9 of 28
Figure 17. Closed-Loop Gain vs. Frequency
Figure 18. Output Impedance vs. Frequency
Figure 19. PSRR vs. Frequency
Figure 20. CMRR vs. Frequency
Figure 21. Large Signal Transient Response
Figure 22. Small Signal Transient Response
60
–2010 100M
GAIN (d B)
FRE QUENCY ( Hz )
–10
0
10
20
30
40
50
100 1k 10k 100k 10M1M
AV = +100
AV = +10
AV = +1
VSY = ± 1.5V
TA = 25° C
08237-012
1000
100
10
1
0.10
0.0110 100M
ZOUT (Ω)
FRE QUENCY ( Hz )
100 1k 10k 100k 10M1M
VSY = ± 1.5V
TA = 25° C
AV = +10
AV = +100 AV = +1
08237-013
140
–2010 100M
PSRR ( dB)
FRE QUENCY ( Hz )
0
20
40
60
80
100
120
100 1k 10k 100k 10M1M
VSY = ± 1.5V
TA = 25° C
PSRR–
PSRR+
08237-014
120
2010 100M
CMRR (dB)
FRE QUENCY ( Hz )
100 1k 10k 100k 10M1M
VSY = ± 1.5V
TA = 25° C
30
40
50
60
70
80
90
100
110
08237-015
1.5
1.0
0.5
0
–1.5
–1.0
–0.5
0246810 12 14 16 18
VOLT AGE (V)
TIME (µs)
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= 2kΩ
C
L
= 100pF
08237-016
80
60
40
20
0
–80
–60
–40
–20
018
VOLT AGE (mV)
TIME (µs)
VSY = ± 1.5V
TA = 25° C
RL = 2kΩ
CL = 100pF
08237-017
246810 12 14 16
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 10 of 28
Figure 23. Settling Time
Figure 24. Voltage Noise Density
Figure 25. Overshoot vs. Load Capacitance
Figure 26. Voltage Noise, 0.1 Hz to 10 Hz
Figure 27. Channel Separation
Figure 28. THD + N vs. Amplitude
2
–10
–8
–6
–4
–2
0
0.08
–0.04
–0.02
0
0.02
0.04
0.06
–1 0 21 43 7 865 9
VOLT AGE (V)
VOLT AGE (V)
TIME (µs)
V
SY
= ±1. 5V
T
A
= 25° C
OUTPUT
INPUT
08237-018
10
4
1110 100 1k 10k 100k
VOLTAGE NOISE DENSITY (nV/√Hz)
FRE QUENCY ( Hz )
VSY = ± 1.5V
TA = 25° C
08237-019
60
50
40
30
20
10
01100010010
OVERSHOOT (%)
CAPACI TANCE (pF )
V
SY
= ±1. 5V
V
IN
= 100mV p - p
R
L
= 2kΩ
T
A
= 25° C OS+
OS–
08237-020
80
–80 012345678910
VOLTAGE NOISE (nV)
TIME (Seconds)
–60
–40
–20
0
20
40
60
V
SY
= ±1. 5V
T
A
= 25° C
08237-021
0
–160
–140
–120
–100
–80
–60
–40
–20
100 1k 10k 100k
CHANNEL S E P ARATION (dB)
FRE QUENCY ( Hz )
V
SY
= ±1. 5V
T
A
= 25° C
V
IN
= 1V p-p
08237-022
2kΩ
–
+
10V p-p CH A
V
CC
V
EE
–
+
2kΩ
10kΩ
1kΩ
CH B,
CH C,
CH D
V
CC
V
EE
1
0.1
0.01
THD + N ( %)
0.001
0.0001
0.001 0.01
AMPLITUDE (VRMS)
0.1 1
VSY = ± 1.5V
TA = 25° C
RL = 10kΩ
VIN AT 1kHz
08237-125
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 11 of 28
Figure 29. THD + N vs. Frequency
Figure 30. No Phase Reversal
Figure 31. Positive Overload Recovery
Figure 32. Negative Overload Recovery
0.01
THD + N ( %)
0.001
0.01 0.1
FREQUENCY (kHz)
110 100
VSY = ± 1.5V
TA = 25° C
VIN = 300mVRMS
500kHz F ILTER
RL = 10kΩ
RL = 2kΩ
08237-126
2.0
–2.0 01000
VOLT AGE (V)
TIME (µs)
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
100 200 300 400 500 600 700 800 900
VSY = ± 1.5V
TA = 25° C
OUTPUT
INPUT
08237-025
CH2 500mVCH1 100mV M2µs A CH1 –84mV
1
2
T 10.2%
CH1 AMPL
200mV
08237-128
VIN
VOUT
VSY = ± 1.5 V
CH2 500mVCH1 100mV M2µs A CH1 44mV
1
2
T 10.4%
CH1 AMPL
200mV
08237-129
V
IN
V
OUT
V
SY
= ±1. 5 V
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 12 of 28
±5 V CHARACTERISTICS
Figure 33. Input Offset Voltage Distribution, SOIC
Figure 34. Input Offset Voltage Distribution, MSOP
Figure 35. Input Offset Voltage Distribution, ADA4084-2 LFCSP
Figure 36. TCVOS Distribution, SOIC and MSOP
Figure 37. TCVOS Distribution, ADA4084-2 LFCSP
Figure 38. Input Offset Voltage vs. Common-Mode Voltage
120
0
–100 –50 50–25 250–75 75 100
NUMBER OF AM P LI FIE RS
VOS (µV)
20
40
60
80
100
VSY = ± 5V
TA = 25° C
RL = ∞
08237-026
60
0
–100 100
NUMBER OF AM P LI FIE RS
VOS (µV)
10
20
30
40
50
–50 50–25 250–75 75
VSY = ± 5V
TA = 25° C
RL = ∞
08237-027
0
50
100
150
200
250
–200 –150 –100 –50 050 100
NUMBER OF AMPLIFIERS
V
OS
(µV)
08237-080
V
SY
= ±5V
T
A
= 25° C
R
L
= ∞
50
002.0
NUMBER OF AM P LI FIE RS
TCV
OS
(µV/°C)
5
10
15
20
25
30
35
40
45
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
V
SY
= ±5V
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
08237-028
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
NUMBER OF AMPLIFIERS
TCVOS (µV/°C)
0
5
10
15
20
25
30
35
08237-084
VSY = ± 5V
RL = ∞
–40°C ≤ TA ≤ +125°C
600
–600–5 5
INPUT OFFSET VOLTAGE (µV)
COMMON-MODE VOLT AGE (V)
–400
–500
–300
–200
–100
0
100
200
300
400
500 VSY = ± 5V
TA = 25° C
RL = ∞
–4 –3 –2 –1 0 1 2 3 4
08237-029
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 13 of 28
Figure 39. Input Offset Voltage vs. Temperature
Figure 40. Input Bias Current vs. Temperature
Figure 41. Input Bias Current vs. VCM and Temperature
Figure 42. Dropout Voltage vs. Source Current
Figure 43. Dropout Voltage vs. Sink Current
Figure 44. Open-Loop Gain and Phase vs. Frequency
–100
–75
–50
–25
0
25
50
75
100
–50–25 0 25 50 75 100125150
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
08237-133
V
SY
= ±5V
–50
–100
–150
–200
–250
–40 125
INP UT BIAS ( nA)
TEMPERATURE (°C)
–25 –10 520 35 50 65 80 95 110
VSY = ± 5V
VCM = 0V
RL = ∞
IB+
IB–
08237-030
800
–800–5 5
INP UT BIAS ( nA)
VCM (V)
–400
–600
–200
0
200
400
600
TA = +125°C
TA = –40° C
VSY = ± 5V
–4 –3 –2 –1 01234
TA = +25°C
TA = +85°C
08237-031
1000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SO URCE CURRE NT (mA)
V
SY
= ±5V
T
A
= 25° C
(V+) – V
OH
08237-032
1000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SI NK CURRE NT (mA)
V
SY
= ±5V
T
A
= 25° C
V
OL
– (V–)
08237-033
120
–40
270
–90
0.1 100k
GAIN (d B)
PHASE ( Degrees)
FRE QUENCY ( kHz )
–45
0
45
90
135
180
225
–20
20
0
40
60
80
100
110 100 1k 10k
V
SY
= ±5V
T
A
= 25° C
R
L
= 10kΩ
08237-034
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 14 of 28
Figure 45. Closed-Loop Gain vs. Frequency
Figure 46. Output Impedance vs. Frequency
Figure 47. PSRR vs. Frequency
Figure 48. CMRR vs. Frequency
Figure 49. Large Signal Transient Response
Figure 50. Small Signal Transient Response
60
–2010 100M
GAIN (d B)
FRE QUENCY ( Hz )
–10
0
10
20
30
40
50
100 1k 10k 100k 10M1M
VSY = ± 5V
TA = 25° C
08237-035
AV = +100
AV = +10
AV = +1
1000
100
10
1
0.10
0.0110 100M
ZOUT (Ω)
FRE QUENCY ( Hz )
100 1k 10k 100k 10M1M
VSY = ± 5V
TA = 25° C
AV = +100
AV = +1
AV = +10
08237-036
140
–2010 100M
PSRR ( dB)
FRE QUENCY ( Hz )
0
20
40
60
80
100
120
100 1k 10k 100k 10M1M
VSY = ± 5V
TA = 25° C
PSRR–
PSRR+
08237-037
120
2010 100M
CMRR (dB)
FRE QUENCY ( Hz )
100 1k 10k 100k 10M1M
VSY = ± 5V
TA = 25° C
30
40
50
60
70
80
90
100
110
08237-038
5
–5
VOLT AGE (V)
TIME (µs)
V
SY
= ±5V
T
A
= 25° C
R
L
= 2kΩ
C
L
= 100pF
–4
–3
–2
–1
0
1
2
3
4
08237-039
018246810 12 14 16
80
60
40
20
0
–80
–60
–40
–20
VOLT AGE (mV)
TIME (µs)
VSY = ± 5V
TA = 25° C
RL = 2kΩ
CL = 100pF
08237-040
0102 31 4 6 75 8 9
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 15 of 28
Figure 51. Settling Time
Figure 52. Voltage Noise Density
Figure 53. Overshoot vs. Load Capacitance
Figure 54. Voltage Noise, 0.1 Hz to 10 Hz
Figure 55. Channel Separation
Figure 56. THD + N vs. Amplitude
10
–25
–20
–5
–10
–15
0
5
0.16
–0.12
–0.08
–0.04
0
0.04
0.08
0.12
–2 02486 18161210 14
VOLT AGE (V)
VOLT AGE (V)
TIME (µs)
V
SY
= ±5V
T
A
= 25° C
OUTPUT
INPUT
08237-041
10
1110 100 1k 10k 100k
VOLTAGE NOISE DENSITY (nV/√Hz)
FRE QUENCY ( Hz )
VSY = ± 5V
TA = 25° C
08237-042
4
60
50
40
30
20
10
01100010010
OVERSHOOT (%)
CAPACI TANCE (pF )
V
SY
= ±5V
V
IN
= 100mV p - p
R
L
= 2kΩ
T
A
= 25° C OS+
OS–
08237-043
80
–80 012345678910
VOLTAGE NOISE (nV)
TIME (Seconds)
–60
–40
–20
0
20
40
60
V
SY
= ±5V
T
A
= 25° C
08237-044
0
–160
–140
–120
–100
–80
–60
–40
–20
100 1k 10k 100k
CHANNEL S E P ARATION (dB)
FRE QUENCY ( Hz )
V
SY
= ±5V
T
A
= 25° C
V
IN
= 5V p-p
08237-045
2kΩ
–
+
10V p-p CH A
V
CC
V
EE
–
+
2kΩ
10kΩ
1kΩ
CH B,
CH C,
CH D
V
CC
V
EE
1
0.1
0.01
THD + N ( %)
0.001
0.0001
0.001 0.01
AMPLITUDE (V
RMS
)
0.1 1
V
SY
= ±5V
T
A
= 25° C
R
L
= 10kΩ
V
IN
AT 1kHz
08237-150
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 16 of 28
Figure 57. THD + N vs. Frequency
Figure 58. No Phase Reversal
Figure 59. Positive Overload Recovery
Figure 60. Negative Overload Recovery
1
THD + N ( %)
0.001
0.01
0.1
0.0001
0.01 0.1
FREQUENCY (kHz)
110 100
V
SY
= ±5V
T
A
= 25° C
V
IN
= 2V
RMS
500kHz F ILTER
R
L
= 10kΩ
R
L
= 2kΩ
08237-151
6
4
2
–4
–2
–6 01000
VOLT AGE (V)
TIME (µs)
0
100 200 300 400 500 600 700 800 900
VSY = ± 5V
TA = 25° C
OUTPUT
INPUT
08237-048
CH2 2VCH1 100mV M1µs A CH1 –84mV
1
2
T 10.2%
CH1 AMPL
202mV
08237-153
V
IN
V
OUT
V
SY
= ±5V
CH2 2VCH1 100mV M2µs A CH1 44.0mV
1
2
T 10.4%
CH1 AMPL
200mV
08237-154
V
IN
V
OUT
V
SY
= ±5V
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 17 of 28
±15 V CHARACTERISTICS
Figure 61. Input Offset Voltage Distribution, SOIC
Figure 62. Input Offset Voltage Distribution, MSOP
Figure 63. Input Offset Voltage Distribution, ADA4084-2 LFCSP
Figure 64. TCVOS Distribution, SOIC and MSOP
Figure 65. TCVOS Distribution, ADA4084-2 LFCSP
Figure 66. Input Offset Voltage vs. Common-Mode Voltage
100
0
–100 –50 50–25 250–75 75 100
NUMBER OF AM P LI FIE RS
VOS (µV)
20
30
10
40
50
60
70
80
90 VSY = ± 15V
TA = 25° C
RL = ∞
08237-049
60
0
–100 100
NUMBER OF AM P LI FIE RS
VOS (µV)
10
20
30
40
50
–50 50–25 250–75 75
VSY = ± 15V
TA = 25° C
RL = ∞
08237-050
0
50
100
150
200
–200 –150 –100 –50 050 100
NUMBER OF AMPLIFIERS
VOS (µV)
08237-079
VSY = ± 15V
TA = 25° C
RL = ∞
60
002.0
NUMBER OF AM P LI FIE RS
TCV
OS
(µV/°C)
10
20
30
40
50
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
V
SY
= ±15V
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
08237-051
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
NUMBER OF AMPLIFIERS
TCV
OS
(µV/°C)
0
5
10
15
20
25
30
08237-085
V
SY
= ±15V
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
600
–600
–15 –10 –5 51510
INPUT OFFSET VOLTAGE (µV)
COMMON-MODE VOLT AGE (V)
–400
–500
–300
–200
–100
0
100
200
300
400
500 V
SY
= ±15V
T
A
= 25° C
R
L
= ∞
0
08237-052
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 18 of 28
Figure 67. Input Offset Voltage vs. Temperature
Figure 68. Input Bias Current vs. Temperature
Figure 69. Input Bias Current vs. VCM and Temperature
Figure 70. Dropout Voltage vs. Source Current
Figure 71. Dropout Voltage vs. Sink Current
Figure 72. Open-Loop Gain and Phase vs. Frequency
–100
–75
–50
–25
0
25
50
75
100
–50 –25 025 50 75 100 125 150
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE ( °C)
08237-165
V
SY
= ±15V
–50
–100
–150
–200
–250
–40 125
INP UT BIAS ( nA)
TEMPERATURE (°C)
–25 –10 520 35 50 65 80 95 110
VSY = ± 15V
VCM = 0V
RL = ∞
IB+
IB–
08237-053
1200
–1200
–15 –10 –5 510 15
INP UT BIAS ( nA)
V
CM
(V)
–400
–800
0
400
800
T
A
= +125°C
T
A
= –40° C
V
SY
= ±15V
0
T
A
= +25°C
T
A
= +85°C
08237-054
1000
10000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SO URCE CURRE NT (mA)
V
SY
= ±15V
T
A
= 25° C
(V+) – V
OH
08237-055
1000
10000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SI NK CURRE NT (mA)
V
SY
= ±15V
T
A
= 25° C
V
OL
– (V–)
08237-056
120
–40
270
–90
100 100M
GAIN (d B)
PHASE ( Degrees)
FRE QUENCY ( Hz )
–45
0
45
90
135
180
225
–20
20
0
40
60
80
100
1k 10k 100k 1M 10M
V
SY
= ±15V
T
A
= 25° C
R
L
= 10kΩ
08237-057
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 19 of 28
Figure 73. Closed-Loop Gain vs. Frequency
Figure 74. Output Impedance vs. Frequency
Figure 75. PSRR vs. Frequency
Figure 76. CMRR vs. Frequency
Figure 77. Large Signal Transient Response
Figure 78. Small Signal Transient Response
60
–2010 100M
GAIN (d B)
FRE QUENCY ( Hz )
–10
0
10
20
30
40
50
100 1k 10k 100k 10M1M
VSY = ± 15V
TA = 25° C
08237-058
AV = +100
AV = +10
AV = +1
1000
100
10
1
0.1
0.0110 100M
ZOUT (Ω)
FRE QUENCY ( Hz )
100 1k 10k 100k 10M1M
VSY = ± 15V
TA = 25° C
AV = +100
AV = +1
AV = +10
08237-059
140
–2010 100M
PSRR ( dB)
FRE QUENCY ( Hz )
0
20
40
60
80
100
120
100 1k 10k 100k 10M1M
VSY = ± 15V
TA = 25° C
PSRR–
PSRR+
08237-060
120
2010 100M
CMRR (dB)
FRE QUENCY ( Hz )
100 1k 10k 100k 10M1M
VSY = ± 15V
TA = 25° C
30
40
50
60
70
80
90
100
110
08237-061
15
10
–15
–10
–5
0
5
0 4 8 12 3628 32242016
VOLT AGE (V)
TIME (µs)
V
SY
= ±15V
T
A
= 25° C
R
L
= 2kΩ
C
L
= 100pF
08237-062
80
60
40
20
0
–80
–60
–40
–20
0 21 43 7 8 965 10
VOLT AGE (mV)
TIME (µs)
V
SY
= ±15V
T
A
= 25° C
R
L
= 2kΩ
C
L
= 100pF
08237-063
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 20 of 28
Figure 79. Settling Time
Figure 80. Voltage Noise Density
Figure 81. Overshoot vs. Load Capacitance
Figure 82. Voltage Noise 0.1 Hz to 10 Hz
Figure 83. Channel Separation
Figure 84. THD + N vs. Amplitude
10
–25
–20
–5
–10
–15
0
5
0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
–2 02486 18161210 14
VOLT AGE (V)
VOLT AGE (V)
TIME (µs)
V
SY
= ±15V
T
A
= 25° C
INPUT
OUTPUT
08237-064
10
1110 100 1k 10k 100k
VOLTAGE NOISE DENSITY (nV/√Hz)
FRE QUENCY ( Hz )
VSY = ± 15V
TA = 25° C
08237-065
4
70
50
60
40
30
20
10
01100010010
OVERSHOOT (%)
CAPACI TANCE (pF )
V
SY
= ±15V
V
IN
= 100mV p - p
R
L
= 2kΩ
T
A
= 25° C OS+
OS–
08237-066
0246810
60
–60
VOLTAGE NOISE (nV)
TIME (Seconds)
–40
–20
0
20
40
V
SY
= ±15V
T
A
= 25° C
08237-067
0
–180
–140
–160
–120
–100
–80
–60
–40
–20
100 1k 10k 100k
CHANNEL S E P ARATION (dB)
FRE QUENCY ( Hz )
V
SY
= ±15V
T
A
= 25° C
V
IN
= 10V p - p
08237-068
2kΩ
–
+
10V p-p CH A
V
CC
V
EE
–
+
2kΩ
10kΩ
1kΩ
CH B,
CH C,
CH D
V
CC
V
EE
1
0.1
0.01
THD + N ( %)
0.001
0.0001
0.001 0.01
AMPLITUDE (V
RMS
)
0.1 110
V
SY
= ±15V
R
L
= 10kΩ
V
IN
AT 1kHz
08237-175
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 21 of 28
Figure 85. THD + N vs. Frequency
Figure 86. No Phase Reversal
Figure 87. Positive Overload Recovery
Figure 88. Negative Overload Recovery
1
THD + N ( %)
0.001
0.01
0.1
0.0001
0.01 0.1
FREQUENCY (kHz)
110 100
V
SY
= ±15V
T
A
= 25° C
V
IN
= 5V
RMS
500kHz F ILTER
R
L
= 10kΩ
R
L
= 2kΩ
08237-176
20
15
10
5
–15
–10
–5
–20 01000
VOLT AGE (V)
TIME (µs)
0
100 200 300 400 500 600 700 800 900
VSY = ± 15V
TA = 25° C
OUTPUT
INPUT
08237-071
CH2 5VCH1 100mV
CH1 AMPL
202mV
M1µs A CH1 –84mV
1
2
T 10.2%
08237-178
VIN
VOUT
VSY = ± 15V
CH2 5VCH1 100mV
CH1 AMPL
200mV
M2µs A CH1 44mV
1
2
T 10.4%
08237-179
VIN
VOUT
VSY = ± 15V
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 22 of 28
Figure 89. Supply Current vs. Supply Voltage
Figure 90. CMRR vs. Temperature
Figure 91. PSRR vs. Temperature
1000
0036
I
SY
/AMPLIFIER (µA)
V
SY
(V)
100
200
300
400
500
600
700
800
900
4 8 12 16 20 24 28 32
T
A
= 25° C
R
L
= ∞
+125°C
+25°C
–40°C
+85°C
08237-072
–50 –25 025 50 75 100 125 150
CMRR (dB)
TEMPERATURE ( °C)
0
20
60
40
80
100
120
140
VCM = ± 14V
VCM = ± 1.5V
VCM = ± 4V
08237-180
–50 –25 025 50 75 100 125 150
PSRR ( dB)
TEMPERATURE ( °C)
50
60
80
70
90
100
120
150
140
130
110
VSY = ± 1.25V TO ± 1.75V VCM = 0
08237-181
VSY = ± 2V TO ±18V VCM = 0
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 23 of 28
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
The ADA4084-2/ADA4084-4 devices are precision single-supply,
rail-to-rail operational amplifiers. Intended for portable
instrumentation, the ADA4084-2/ADA4084-4 devices combine
the attributes of precision, wide bandwidth, and low noise,
making them an ideal choice in single-supply applications that
require both ac and precision dc performance. Other low supply
voltage applications for which the ADA4084-2/ADA4084-4
devices are well suited are active filters, audio microphone
preamplifiers, power supply control, and telecommunications.
To combine all of these attributes with rail-to-rail input/output
operation, novel circuit design techniques are used.
Figure 92. Equivalent Input Circuit
For example, Figure 92 illustrates a simplified equivalent circuit for
the input stage of the ADA4084-2/ADA4084-4. It comprises a PNP
differential pair, Q1 and Q2, and an NPN differential pair, Q3
and Q4, operating concurrently. Diode D100 and Diode D101
serve to clamp the applied differential input voltage to the
ADA4084-2/ADA4084-4, thereby protecting the input transistors
against Zener breakdown of the emitter-base junctions. Input
stage voltage gains are kept low for input rail-to-rail operation.
The two pairs of differential output voltages are connected to the
second stage of the ADA4084-2/ADA4084-4, which is a modified
compound folded cascade gain stage. It is also in the second gain
stage that the two pairs of differential output voltages are
combined into a single-ended output signal voltage used to
drive the output stage.
A key issue in the input stage is the behavior of the input bias
currents over the input common-mode voltage range. Input bias
currents in the ADA4084-2/ADA4084-4 are the arithmetic sum
of the base currents in Q1 and Q4 and in Q2 and Q3. As a result of
this design approach, the input bias currents in the ADA4084-2/
ADA4084-4 not only exhibit different amplitudes; they also exhibit
different polarities. This effect is best illustrated by Figure 12,
Figure 13, Figure 40, Figure 41, Figure 68, and Figure 69. It is,
therefore, important that the effective source impedances that
are connected to the ADA4084-2/ADA4084-4 inputs be
balanced for optimum dc and ac performance.
To achieve rail-to-rail output, the ADA4084-2/ADA4084-4
output stage design employs a unique topology for both sourcing
and sinking current. This circuit topology is shown in Figure 93.
The output stage is voltage-driven from the second gain stage.
The signal path through the output stage is inverting; that is, for
positive input signals, Q13 provides the base current drive to Q19
so that it conducts (sinks) current. For negative input signals,
the signal path via Q18 → mirror → Q24 provides the base
current drive for Q23 to conduct (source) current. Both
transistors provide output current until they are forced into
saturation.
Figure 93. Equivalent Output Circuit
Thus, the saturation voltage of the output transistors sets the
limit on the ADA4084-2/ADA4084-4 maximum output voltage
swing. Output short-circuit current limiting is determined by
the maximum signal current into the base of Q13 from the
second gain stage. The output stage also exhibits voltage gain. This
is accomplished by the use of common-emitter amplifiers, and,
as a result, the voltage gain of the output stage (thus, the open-
loop gain of the device) exhibits a dependence on the total load
resistance at the output of the ADA4084-2/ADA4084-4.
D2
D101
D100
D5 D4
D1
Q1
Q4 Q3
Q2
08237-073
R4
R1 R2
R3
Q24
Q21 D20
Q13
Q18
Q19
Q23
V
EE
V
OUT
V
CC
V
BIAS
MIRROR
08237-074
R5
R6
R7 C2
C1
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 24 of 28
START-UP CHARACTERISTICS
The ADA4084-2/ADA4084-4 are specified to operate from 3 V to
30 V (±1.5 V to ±15 V) under nominal power supplies. During
power-up as the supply voltage increases from 0 V to the nomi-
nal power supply voltage, the supply current (ISY) increases as well,
to the point at which it stabilizes and the amplifier is ready to
operate. The stabilization varies with temperature, as shown in
Figure 89. For example, at −40°C, it requires a higher voltage
and stabilizes at a lower supply current than at hot temperatures.
At hot temperatures, it requires a lower voltage but stabilizes at a
higher current. In all cases, the ADA4084-2/ADA4084-4 are
specified to start up and operate at a minimum of 3 V under all
temperature conditions.
INPUT PROTECTION
As with any semiconductor device, if conditions exist where the
applied input voltages to the device exceed either supply voltage,
the input overvoltage I-to-V characteristic of the device must be
considered. When an overvoltage occurs, the amplifier may be
damaged, depending on the magnitude of the applied voltage
and the magnitude of the fault current.
The D1, D2, D4, and D5 diodes conduct when the input common-
mode voltage exceeds either supply pin by a diode drop. This
diode drop voltage varies with temperature and is in the range
of 0.3 V to 0.8 V. As shown in the simplified equivalent input
circuit of Figure 92, the ADA4084-2/ADA4084-4 do not have any
internal current limiting resistors; thus, fault currents can quickly
rise to damaging levels.
This input current is not inherently damaging to the device,
provided that it is limited to 5 mA or less. If a fault condition
causes more than 5 mA to flow, add an external series resistor at
the expense of additional thermal noise. Figure 94 shows a
typical noninverting configuration for an overvoltage protected
amplifier, where the series resistance, RS, is chosen, such that
( )
mA5
SUPPLY
MAX
IN
S
VV
R−
=
For example, a 1 kΩ resistor protects the ADA4084-2/ADA4084-4
against input signals up to 5 V above and below the supplies.
Note that the thermal noise of a 1 kΩ resistor at room tempera-
ture is 4 nV/√Hz, which exceeds the voltage noise of the
ADA4084-2/ADA4084-4. For other configurations in which
both inputs are used, protect each input against abuse with a
series resistor. To ensure optimum dc and ac performance,
balance the source impedance levels.
Figure 94. Resistance in Series with Input
Limits Overvoltage Currents to Safe Values
To protect the Q1/Q2 and Q3/Q4 pairs from large differential
voltages that may result in Zener breakdown of the emitter-base
junction, D100 and D101 are connected between the two
inputs. This precludes operation as a comparator. For a more
complete description, see the MT-035 Tutorial, Op Amp Inputs,
Outputs, Single-Supply, and Rail-to-Rail Issues; the MT-083
Tutorial, Comparators; the MT-084 Tutorial, Using Op Amps As
Comparators; and the AN-849 Application Note, Using Op
Amps as Comparators, at www.analog.com.
OUTPUT PHASE REVERSAL
Some operational amplifiers designed for single-supply operation
exhibit an output voltage phase reversal when their inputs are
driven beyond their useful common-mode range. Typically, for
single-supply bipolar op amps, the negative supply determines
the lower limit of their common-mode range. With these devices,
external clamping diodes, with the anode connected to ground
and the cathode to the inputs, prevent input signal excursions
from exceeding the negative supply of the device (that is, GND),
preventing a condition that causes the output voltage to change
phase. JFET input amplifiers can also exhibit phase reversal, and, if
so, a series input resistor is usually required to prevent it.
The ADA4084-2/ADA4084-4 are free from reasonable input
voltage range restrictions, provided that input voltages no
greater than the supply voltages are applied (see Figure 30,
Figure 58, and Figure 86).
Although device output does not change phase, large currents can
flow through the input protection diodes. Therefore, apply the
technique recommended in the Input Protection section to
those applications where the likelihood of input voltages
exceeding the supply voltages is high.
R1
R2
V
IN
V
OUT
1/2
ADA4084-2/
ADA4084-4
08237-075
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 25 of 28
DESIGNING LOW NOISE CIRCUITS IN SINGLE-
SUPPLY APPLICATIONS
In single-supply applications, devices like the ADA4084-2/
ADA4084-4 extend the dynamic range of the application through
the use of rail-to-rail operation. Referring to the op amp noise
model circuit configuration illustrated in Figure 95, the
expression for the total equivalent input noise voltage of an
amplifier for a source resistance level, RS, is given by
[
]
22
2
)()()(2
nOA
SnOA
nR
nT
eee
Ri
+×+=
, units in
Hz
V
where:
RS = 2R, the effective, or equivalent, circuit source resistance.
(enR)2 is the source resistance thermal noise voltage power (4kTR).
k is the Boltzmann’s constant, 1.38 × 10–23 J/K.
T is the ambient temperature in Kelvin of the circuit, 273.15 +
TA (°C).
(inOA)2 is the op amp equivalent input noise current spectral
power (1 Hz bandwidth).
(enOA)2 is the op amp equivalent input noise voltage spectral
power (1 Hz bandwidth).
Figure 95. Op Amp Noise Circuit Model Used to Determine Total Circuit
Equivalent Input Noise Voltage and Noise Figure
As a design aid, Figure 96 shows the equivalent thermal noise of
the ADA4084-2/ADA4084-4 vs. the total source resistance. Note
that for source resistance less than 1 kΩ, the equivalent input
noise voltage of the ADA4084-2/ADA4084-4 is dominant.
Figure 96. Equivalent Thermal Noise vs. Total Source Resistance
Because circuit SNR is the critical parameter in the final analysis,
the noise behavior of a circuit is sometimes expressed in terms
of its noise figure, NF. The noise figure is defined as the ratio of
the signal-to-noise output of a circuit to its signal-to-noise
input.
Noise figure is generally used for RF and microwave circuit analysis
in a 50 Ω system. This is not very useful for op amp circuits where
the input and output impedances can vary greatly. For a more
complete description of noise figure, see the MT-052 Tutorial, Op
Amp Noise Figure: Don’t be Mislead, available at www.analog.com.
Signal levels in the application invariably increase to maximize
circuit SNR, which is not an option in low voltage, single-supply
applications.
Therefore, to achieve optimum circuit SNR in single-supply
applications, choose an operational amplifier with the lowest
equivalent input noise voltage, along with source resistance
levels that are consistent with maintaining low total circuit noise.
COMPARATOR OPERATION
Although op amps are quite different from comparators,
occasionally an unused section of a dual or a quad op amp
can be used as a comparator; however, this is not recommended
for any rail-to-rail output op amps. For rail-to-rail output op
amps, the output stage is generally a ratioed current mirror with
bipolar or MOSFET transistors. With the device operating open
loop, the second stage increases the current drive to the ratioed
mirror to close the loop. However, the loop cannot close, which
results in an increase in supply current. With the op amp
configured as a comparator, the supply current can be
significantly higher (see Figure 97). Configure an unused
section as a voltage follower with the noninverting input
connected to a voltage within the input voltage range. The
ADA4084-2/ADA4084-4 have unique second stage and output
stage designs that greatly reduce the excess supply current when
the op amp is operating open loop.
Figure 97. Supply Current vs. Supply Voltage
enR
enR
enOA
inOA
inOA
R
NOISELESS
R
NOISELESS
08237-076
IDEAL
NOISELESS
OP AMP
R
S
= 2R
TOTAL SOURCE RES ISTANCE, R
S
(Ω)
100
1
EQUIVALENT THERMAL NOISE (nV/ Hz)
10
10k
ADA4084-2/ ADA4084- 4 TOTAL
EQUIVALENT NOISE
RESIST OR T HE RM AL
NOISE ONLY
08237-077
100 1k 100k
FRE QUENCY = 1kHz
T
A
= 25° C
800
0036
SUPP LY CURRENT (µ A)
VSY (V)
08237-078
100
200
300
400
500
600
700
4 8 12 16 20 24 28 32
TA = 25° C
RL = ∞
COMPARATOR
OUTPUT LOW
COMPARATOR
OUTPUT HIGH
BUFFER
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 26 of 28
OUTLINE DIMENSIONS
Figure 98. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Figure 99. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Data Sheet ADA4084-2/ADA4084-4
Rev. D | Page 27 of 28
Figure 100. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-12)
Dimensions shown in millimeters
Figure 101. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PI N 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.70
1.60 S Q
1.50
0.203 RE F
0.05 M AX
0.02 NOM
0.50 BS C
EXPOSED
PAD
3.10
3.00 S Q
2.90
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC S TANDARDS MO-229- WEED
PI N 1
INDICATOR
(R 0. 15)
02-05-2013-B
0.20 M IN
COM P LIANT T O JEDEC S TANDARDS M O-153- AB- 1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PI N 1
5.10
5.00
4.90
0.65 BS C
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
ADA4084-2/ADA4084-4 Data Sheet
Rev. D | Page 28 of 28
Figure 102. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-26)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
ADA4084-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Q
ADA4084-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Q
ADA4084-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Q
ADA4084-2ARZ
−40°C to +125°C
8-Lead Standard Small Outline Package [SOIC_N]
R-8
ADA4084-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4084-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4084-2ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-8-12 A2Q
ADA4084-2ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-8-12 A2Q
ADA4084-4ACPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-26
ADA4084-4ACPZ-RL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-26
ADA4084-4RUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADA4084-4RUZ-RL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
1 Z = RoHS Compliant Part.
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
042709-A
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
1213
4
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.50
0.40
0.30
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
2.60
2.50 SQ
2.40
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08237-0-11/13(D)
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