SN74LVC2G125 www.ti.com SCES204N - APRIL 1999 - REVISED NOVEMBER 2013 Dual Bus Buffer Gate With 3-State Outputs Check for Samples: SN74LVC2G125 FEATURES DESCRIPTION * The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. 1 2 * * * * * * * * * * * Available in the Texas Instruments NanoFreeTM Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.3 ns at 3.3 V Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Ioff Supports Live Insertion, Partial-PowerDown Mode, and Back-Drive Protection Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the VCC Level Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) DCT PACKAGE (TOP VIEW) NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. DCU PACKAGE (TOP VIEW) 1OE 1 8 VCC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A 1OE 1A 2Y GND 1 8 2 7 3 6 4 5 YZP PACKAGE (BOTTOM VIEW) VCC 2OE 1Y 2A GND 2Y 1A 1OE 4 5 3 6 2 7 1 8 2A 1Y 2OE VCC See mechanical drawings for dimensions. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2013, Texas Instruments Incorporated SN74LVC2G125 SCES204N - APRIL 1999 - REVISED NOVEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Function Table (Each Buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z Logic Diagram (Positive Logic) 1 1OE 1A 2 6 1Y 7 2OE 5 3 2A 2Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range -0.5 6.5 V VI Input voltage range (2) -0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) -0.5 6.5 V -0.5 VCC + 0.5 (2) (3) UNIT VO Voltage range applied to any output in the high or low state IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current 50 mA 100 mA Continuous current through VCC or GND JA Tstg (1) (2) (3) (4) 2 Package thermal impedance (4) DCT package 220 DCU package 227 YZP package 102 Storage temperature range -65 150 V C/W C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G125 SN74LVC2G125 www.ti.com SCES204N - APRIL 1999 - REVISED NOVEMBER 2013 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 1.5 Low-level input voltage VI Input voltage 1.7 Output voltage 0.7 x VCC 0.35 x VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 3 V -32 4 VCC = 2.3 V t/v Input transition rise or fall rate 8 16 VCC = 3 V VCC = 4.5 V 32 VCC = 1.8 V 0.15 V, 2.5 V 0.2 V 20 VCC = 3.3 V 0.3 V 10 (1) Operating free-air temperature mA 24 VCC = 5 V 0.5 V TA mA -24 VCC = 1.65 V Low-level output current V -8 -16 VCC = 4.5 V IOL V -4 VCC = 2.3 V High-level output current V 0.3 x VCC 0 VCC = 1.65 V IOH V 2 VCC = 4.5 V to 5.5 V VO V 0.65 x VCC VCC = 1.65 V to 1.95 V VIL UNIT ns/V 5 -40 125 C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G125 3 SN74LVC2G125 SCES204N - APRIL 1999 - REVISED NOVEMBER 2013 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) -40C to 85C PARAMETER VOH TEST CONDITIONS MIN VCC - 0.1 VCC - 0.1 IOH = -4 mA 1.65 V 1.2 1.2 IOH = -8 mA 2.3 V 1.9 1.9 2.4 2.4 2.3 2.3 3.8 3.8 3V TYP (1) MA X 4.5 V IOL = 100 A 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 3V IOL = 24 mA UNIT V IOH = -32 mA IOL = 16 mA II TYP -40C to 125C MA X 1.65 V to 5.5 V IOH = -24 mA A or OE inputs MIN (1) IOH = -100 A IOH = -16 mA VOL VCC 0.4 0.4 0.55 0.55 V IOL = 32 mA 4.5 V 0.55 0.75 VI = 5.5 V or GND 0 to 5.5 V 5 5 A Ioff VI or VO = 5.5 V 0 10 10 A IOZ VO = 0 to 5.5 V 3.6 V 10 10 A ICC VI = 5.5 V or GND, 1.65 V to 5.5 V 10 10 A ICC One input at VCC - 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 500 A VI = VCC or GND 3.3 V VO = VCC or GND 3.3 V Ci Co (1) 4 Data inputs Control inputs IO = 0 3.5 4 6.5 pF pF All typical values are at VCC = 3.3 V, TA = 25C. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G125 SN74LVC2G125 www.ti.com SCES204N - APRIL 1999 - REVISED NOVEMBER 2013 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC2G125 -40C to 85C PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX tpd A Y 3.3 9.1 1.5 4.8 1.4 4.3 1 3.7 ns ten OE Y 4 9.9 1.9 5.6 1.2 4.7 1.2 3.8 ns tdis OE Y 1.5 11.6 1 5.8 1.4 4.6 1 3.4 ns VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V UNIT Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC2G125 -40C to 125C PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX tpd A Y 3.3 10.1 1.5 5.8 1.4 5.3 1 4.2 ns ten OE Y 4 10.9 1.9 6.6 1.2 5.7 1.2 4.3 ns tdis OE Y 1.5 12.6 1 6.8 1.4 5.6 1 3.9 ns VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V UNIT Operating Characteristics TA = 25 TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 19 19 20 22 2 2 2 3 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G125 UNIT pF 5 SN74LVC2G125 SCES204N - APRIL 1999 - REVISED NOVEMBER 2013 www.ti.com Parameter Measurement Information VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL tPLZ VLOAD/2 VM tPZH VM VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH - VD VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G125 SN74LVC2G125 www.ti.com SCES204N - APRIL 1999 - REVISED NOVEMBER 2013 REVISION HISTORY Changes from Revision M (January 2007) to Revision N Page * Updated document to new TI data sheet format. ................................................................................................................. 1 * Removed ordering information. ............................................................................................................................................ 1 * Updated Features. ................................................................................................................................................................ 1 * Added ESD warning. ............................................................................................................................................................ 2 * Updated operating temperature range. ................................................................................................................................. 3 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G125 7 PACKAGE OPTION ADDENDUM www.ti.com 30-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) 74LVC2G125DCTRE4 ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C25 Z 74LVC2G125DCTRE6 ACTIVE SM8 DCT 8 3000 Pb-Free (RoHS) CU SNBI Level-1-260C-UNLIM -40 to 125 C25 Z 74LVC2G125DCTRG4 ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C25 Z 74LVC2G125DCURE4 ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C25R 74LVC2G125DCURG4 ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C25R 74LVC2G125DCUTE4 ACTIVE US8 DCU 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C25Q ~ C25R) 74LVC2G125DCUTG4 ACTIVE US8 DCU 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C25Q ~ C25R) SN74LVC2G125DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C25 Z SN74LVC2G125DCUR ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (25 ~ C25Q ~ C25R) CZ SN74LVC2G125DCUT ACTIVE US8 DCU 8 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (C25Q ~ C25R) SN74LVC2G125YZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 (CM2 ~ CM7 ~ CMN) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 30-Oct-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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OTHER QUALIFIED VERSIONS OF SN74LVC2G125 : * Automotive: SN74LVC2G125-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74LVC2G125DCURG4 Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74LVC2G125DCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74LVC2G125YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74LVC2G125DCURG4 US8 DCU 8 3000 202.0 201.0 28.0 SN74LVC2G125DCUR US8 DCU 8 3000 202.0 201.0 28.0 SN74LVC2G125YZPR DSBGA YZP 8 3000 220.0 220.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MPDS049B - MAY 1999 - REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM CCCCC CCCCC CCCCC CCCCC 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0 - 8 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. 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