2011-2013 Microchip Technology Inc. DS70000657H-page 517
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
INDEX
A
Absolute Maximum Ratings .............................................. 401
AC Characteristics .................................................... 413, 471
10-Bit ADC Conversion Requirements ..................... 465
12-Bit ADC Conversion Requirements ..................... 463
ADC Module.............................................................. 459
ADC Module (10-Bit Mode)............................... 461, 473
ADC Module (12-Bit Mode)............................... 460, 473
Capacitive Loading Requirements on
Output Pins ....................................................... 413
DMA Module Requirements...................................... 465
ECANx I/O Requirements ......................................... 454
External Clock........................................................... 414
High-Speed PWMx Requirements ............................ 422
I/O Timing Requirements .......................................... 416
I2Cx Bus Data Requirements (Master Mode) ........... 451
I2Cx Bus Data Requirements (Slave Mode) ............. 453
Input Capture x Requirements .................................. 420
Internal FRC Accuracy.............................................. 415
Internal LPRC Accuracy............................................ 415
Internal RC Accuracy ................................................ 472
Load Conditions ................................................ 413, 471
OCx/PWMx Mode Requirements.............................. 421
Op Amp/Comparator Voltage Reference
Settling Time Specifications.............................. 457
Output Compare x Requirements ............................. 421
PLL Clock.......................................................... 415, 471
QEI External Clock Requirements ............................ 423
QEI Index Pulse Requirements................................. 425
Quadrature Decoder Requirements.......................... 424
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer Requirements......................... 417
SPI1 Master Mode (Full-Duplex, CKE = 0, CKP = x,
SMP = 1) Requirements ................................... 441
SPI1 Master Mode (Full-Duplex, CKE = 1, CKP = x,
SMP = 1) Requirements ................................... 440
SPI1 Master Mode (Half-Duplex, Transmit Only)
Requirements ................................................... 439
SPI1 Maximum Data/Clock Rate Summary.............. 438
SPI1 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) Requirements.................... 449
SPI1 Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) Requirements.................... 447
SPI1 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) Requirements.................... 443
SPI1 Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) Requirements.................... 445
SPI2 Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP
= 1) Requirements ............................................ 429
SPI2 Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) Requirements .................... 428
SPI2 Master Mode (Half-Duplex, Transmit Only)
Requirements ................................................... 427
SPI2 Maximum Data/Clock Rate Summary.............. 426
SPI2 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) Requirements.................... 437
SPI2 Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP
= 0) Requirements ............................................ 435
SPI2 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) Requirements.................... 431
SPI2 Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) Requirements.................... 433
Timer1 External Clock Requirements ....................... 418
Timer2/Timer4 External Clock Requirements........... 419
Timer3/Timer5 External Clock Requirements........... 419
UARTx I/O Requirements......................................... 454
ADC
Control Registers...................................................... 325
Helpful Tips............................................................... 324
Key Features ............................................................ 321
Resources ................................................................ 324
Arithmetic Logic Unit (ALU) ................................................ 44
Assembler
MPASM Assembler .................................................. 398
B
Bit-Reversed Addressing.................................................. 115
Example.................................................................... 116
Implementation ......................................................... 115
Sequence Table (16-Entry) ...................................... 116
Block Diagrams
Data Access from Program Space
Address Generation ................................. 117
16-Bit Timer1 Module ............................................... 203
ADC Conversion Clock Period ................................. 323
ADC with Connection Options for ANx Pins
and Op Amps ................................................... 322
Arbiter Architecture................................................... 110
BEMF Voltage Measurement Using ADC................... 34
Boost Converter Implementation ................................ 32
CALL Stack Frame ................................................... 111
Comparator (Module 4) ............................................ 356
Connections for On-Chip Voltage Regulator ............ 384
CPU Core ................................................................... 36
CRC Module ............................................................. 373
CRC Shift Engine ..................................................... 374
CTMU Module .......................................................... 316
Digital Filter Interconnect.......................................... 357
DMA Controller ......................................................... 141
DMA Controller Module ............................................ 139
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X ............................ 25
ECAN Module........................................................... 288
EDS Read Address Generation................................ 105
EDS Write Address Generation................................ 106
Example of MCLR Pin Connections ........................... 30
High-Speed PWMx Architectural Overview .............. 227
High-Speed PWMx Register Interconnection ........... 228
I2Cx Module ............................................................. 274
Input Capture x ......................................................... 213
Interleaved PFC.......................................................... 34
Multiphase Synchronous Buck Converter .................. 33
Multiplexing Remappable Output for RPn ................ 180
Op Amp Configuration A........................................... 358
Op Amp Configuration B........................................... 359
Op Amp/Comparator Voltage Reference Module..... 356
Op Amp/Comparator x (Modules 1, 2, 3).................. 355
Oscillator System...................................................... 153
Output Compare x Module ....................................... 219
PLL ........................................................................... 154
Programmer’s Model .................................................. 38
PTG Module ............................................................. 338
Quadrature Encoder Interface .................................. 250
Recommended Minimum Connection ........................ 30