© Semiconductor Components Industries, LLC, 2012
January, 2012 − Rev. 0
1Publication Order Number:
1N5929BRN/D
1N59xxBRNG Series
3 W DO-41 Surmetict 30
Zener Voltage Regulators
This is a 1N59xxBRNG series with limits and excellent operating
characteristics that reflect the superior capabilities of silicon−oxide
passivated junctions. All this in an axial−lead, transfer−molded plastic
package that offers protection in all common environmental
conditions.
Features
•Zener Voltage Range − 3.3 V to 200 V
•ESD Rating of Class 3 (>16 KV) per Human Body Model
•Surge Rating of 98 W @ 1 ms
•Maximum Limits Guaranteed on up to Six Electrical Parameters
•Package No Larger than the Conventional 1 W Package
•This is a Pb−Free Device
Mechanical Characteristics
CASE: Void free, transfer−molded, thermosetting plastic
FINISH: All external surfaces are corrosion resistant and leads are
readily solderable
MAXIMUM LEAD TEMPERATURE FOR SOLDERING PURPOSES:
260°C, 1/16″ from the case for 10 seconds
POLARITY: Cathode indicated by polarity band
MOUNTING POSITION: Any
MAXIMUM RATINGS
Rating Symbol Value Unit
Max. Steady State Power Dissipation
@ TL = 75°C, Lead Length = 3/8″
Derate above 75°C
PD3.0
24
W
mW/°C
Steady State Power Dissipation
@ TA = 50°C
Derate above 50°C
PD1.0
6.67
W
mW/°C
Operating and Storage
Temperature Range
TJ, Tstg −65 to
+200
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Device Package Shipping†
ORDERING INFORMATION
1N59xxBRNG Axial Lead
(Pb−Free)
AXIAL LEAD
CASE 59AB
STYLE 1
3000 Units / Box
Cathode Anode
MARKING DIAGRAM
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
http://onsemi.com
A = Assembly Location
1N59xxR = Device Number
YY = Year
WW = Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
A
1N
59xxR
YYWWG
G
Zener Voltage Regulator
IF
V
I
IR
IZT
VR
VZ
VF
1N59xxBRNG Series
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS
(TL = 30°C unless otherwise noted,
VF = 1.5 V Max @ IF = 200 mAdc for all types)
Symbol Parameter
VZReverse Zener Voltage @ IZT
IZT Reverse Current
ZZT Maximum Zener Impedance @ IZT
IZK Reverse Current
ZZK Maximum Zener Impedance @ IZK
IRReverse Leakage Current @ VR
VRBreakdown Voltage
IFForward Current
VFForward Voltage @ IF
IZM Maximum DC Zener Current
1N59xxBRNG Series
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (TL = 30°C unless otherwise noted, VF = 1.5 V Max @ IF = 200 mAdc for all types)
Device†
(Note 1)
Device
Marking
Zener Voltage (Note 2) Zener Impedance (Note 3) Leakage Current
IZM
VZ (Volts) @ IZT ZZT @ IZT ZZK @ IZK IR @ VR
Min Nom Max mA W W mA mA Max Volts mA
1N5929BRNG 1N5929R 14.25 15 15.75 25.0 9 600 0.25 1 11.4 100
1N5932BRNG 1N5932R 19.00 20 21.00 18.7 14 650 0.25 1 15.2 75
1N5934BRNG 1N5934R 22.80 24 25.20 15.6 19 700 0.25 1 18.2 62
†The “G’’ suffix indicates Pb−Free package available.
1. TOLERANCE AND TYPE NUMBER DESIGNATION
Tolerance designation − device tolerance of ±5% are indicated by a “B” suffix.
2. ZENER VOLTAGE (VZ) MEASUREMENT
ON Semiconductor guarantees the zener voltage when measured at 90 seconds while maintaining the lead temperature (TL) at 30°C ±1°C,
3/8″ from the diode body.
3. ZENER IMPEDANCE (ZZ) DERIVATION
The zener impedance is derived from 60 seconds AC voltage, which results when an AC current having an rms value equal to 10% of the
DC zener current (IZT or IZK) is superimposed on IZT or IZK.
Figure 1. Power Temperature Derating Curve
TL, LEAD TEMPERATURE (°C)
0 20 40 60 20080 100 120 140 160 180
0
1
2
3
4
5
L = 3/8″
PD, STEADY STATE DISSIPATION (WATTS)
L = LEAD LENGTH
TO HEAT SINK
1N59xxBRNG Series
http://onsemi.com
4
10
20
30
50
100
200
300
500
1K
0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100
PW, PULSE WIDTH (ms)
P , PEAK SURGE POWER (WATTS)
PK
1 2 5 10 20 50 100 200 400 1000
0.0003
0.0005
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
3
TA = 125°C
TA = 125°C
NOMINAL VZ (VOLTS)
AS SPECIFIED IN ELEC. CHAR. TABLE
Figure 2. Typical Thermal Response L, Lead Length = 3/8 Inch
Figure 3. Maximum Surge Power Figure 4. Typical Reverse Leakage
IR, REVERSE LEAKAGE (μAdc) @ VR
RECTANGULAR
NONREPETITIVE
WAVEFORM
TJ=25°C PRIOR
TO INITIAL PULSE
0.5
θJL (t, D), TRANSIENT THERMAL RESISTANCE
JUNCTION‐TO‐LEAD (°C/W)
0.01
0.0000001
DUTY CYCLE, D = t1/t2
SINGLE PULSE D TJL = qJL(t)PPK
REPETITIVE PULSES D TJL = qJL(t,D)PPK
qJL(t,D) = D * qJL (∞)+(1−D) * qJL(t)
[where qJL(t) is D = 0 curve]
PPK t1
t2
t, TIME (SECONDS)
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100
0.1
1
10
100
D = 0
0.2
0.1
0.05
0.02
0.01
1N59xxBRNG Series
http://onsemi.com
5
APPLICATION NOTE
Since the actual voltage available from a given zener
diode is temperature dependent, it is necessary to determine
junction temperature under any set of operating conditions
in order to calculate its value. The following procedure is
recommended:
Lead Temperature, TL, should be determined from:
TL = qLA PD + TA
qLA is the lead-to-ambient thermal resistance (°C/W) and
PD is the power dissipation. The value for qLA will vary and
depends on the device mounting method. qLA is generally
30−40°C/W for the various clips and tie points in common
use and for printed circuit board wiring.
The temperature of the lead can also be measured using a
thermocouple placed on the lead as close as possible to the
tie point. The thermal mass connected to the tie point is
normally large enough so that it will not significantly
respond to heat surges generated in the diode as a result of
pulsed operation once steady-state conditions are achieved.
Using the measured value of TL, the junction temperature
may be determined by:
TJ = TL + DTJL
DTJL is the increase in junction temperature above the lead
temperature and may be found from Figure 2 for a train of
power pulses (L = 3/8 inch) or from Figure 10 for dc power.
DTJL = qJL PD
For worst-case design, using expected limits of IZ, limits
of PD and the extremes of TJ (DTJ) may be estimated.
Changes in voltage, VZ, can then be found from:
DV = qVZ DTJ
qVZ, the zener voltage temperature coefficient, is found
from Figures 5 and 6.
Under high power-pulse operation, the zener voltage will
vary with time and may also be affected significantly by the
zener resistance. For best regulation, keep current
excursions as low as possible.
Data of Figure 2 should not be used to compute surge
capability. Surge limitations are given in Figure 3. They are
lower than would be expected by considering only junction
temperature, as current crowding effects cause temperatures
to be extremely high in small spots resulting in device
degradation should the limits of Figure 3 be exceeded.
1N59xxBRNG Series
http://onsemi.com
6
Figure 5. Units To 12 Volts Figure 6. Units 10 To 400 Volts
Figure 7. VZ = 3.3 thru 10 Volts Figure 8. VZ = 12 thru 82 Volts
Figure 9. VZ = 100 thru 400 Volts Figure 10. Typical Thermal Resistance
ZENER VOLTAGE versus ZENER CURRENT
(Figures 7, 8 and 9)
TEMPERATURE COEFFICIENT RANGES
(90% of the Units are in the Ranges Indicated)
VZ, ZENER VOLTAGE @ IZT (VOLTS)
34 5 6 789101112
10
8
6
4
2
0
-2
-4
RANGE
, TEMPERATURE COEFFICIENT (mV/ C) @ I ZTVZ °
θ
1000
500
200
100
50
20
10 10 20 50 100 200 400 1000
VZ, ZENER VOLTAGE @ IZT (VOLTS)
, TEMPERATURE COEFFICIENT (mV/ C) @ IZTVZ °θ
01 234 56 7 8910
100
50
30
20
10
1
0.5
0.3
0.2
0.1
VZ, ZENER VOLTAGE (VOLTS)
I , ZENER CURRENT (mA)
Z
2
5
3
0102030405060708090100
VZ, ZENER VOLTAGE (VOLTS)
I , ZENER CURRENT (mA)
Z
100
50
30
20
10
1
0.5
0.3
0.2
0.1
2
5
3
100 200 300 400250 350150
10
1
0.5
0.2
0.1
VZ, ZENER VOLTAGE (VOLTS)
2
5
I , ZENER CURRENT (mA)
Z
0
10
20
30
40
50
60
70
80
L, LEAD LENGTH TO HEAT SINK (INCH)
EQUAL CONDUCTION
THROUGH EACH LEAD
0 1/8 1/4 3/8 1/2 5/8 3/4 7/8 1
TL
JL, JUNCTION‐TO‐LEAD THERMAL RESISTANCE
θ
LL
( C/W)°
1N59xxBRNG Series
http://onsemi.com
7
PACKAGE DIMENSIONS
AXIAL LEAD
CASE 59AB
ISSUE O
B
D
K
K
F
F
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A4.10 5.200.161 0.205
B2.00 2.700.079 0.106
D0.71 0.860.028 0.034
F−−− 1.27−−− 0.050
K13.70 −−−0.540 −−−
NOTES:
1. CONTROLLING DIMENSION: INCHES.
2. PACKAGE CONTOUR IS OPTIONAL WITHIN DIMENSIONS A
AND B. HEAT SLUGS, IF ANY, SHALL BE WITHIN DIMENSION
B BUT NOT SUBJECT TO ITS MINIMUM VALUE.
3. DIMENSION A DEFINES THE ENTIRE BODY INCLUDING
HEAT SLUGS.
4. DIMENSION B IS MEASURED AT THE MAXIMUM DIAMETER
OF THE BODY.
5. POLARITY SHALL BE DENOTED BY A CATHODE BAND.
6. LEAD DIAMETER, D, IS NOT CONTROLLED IN ZONE F.
7. ALL RULES AND NOTES ASSOCIATED WITH JEDEC DO−41
OUTLINE SHALL APPLY
STYLE 1:
PIN 1. CATHODE (POLARITY BAND)
2. ANODE
POLARITY INDICATOR
OPTIONAL AS NEEDED
(SEE STYLES)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
1N5929BRN/D
SURMETIC is a trademark of Semiconductor Components Industries, LLC (SCILLC).
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
