TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 2010, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all
parameters.
•High-Performance Operation:
fmax (no feedback)
TIBPAL20R’ -7C Series . . . 100 MHz
TIBPAL20R’ -10M Series . . . 62.5 MHz
fmax (internal feedback)
TIBPAL20R’ -7C Series . . . 100 MHz
TIBPAL20R’ -10M Series . . . 62.5 MHz
fmax (external feedback)
TIBPAL20R’ -7C Series . . . 74 MHz
TIBPAL20R’ -10M Series . . . 50 MHz
Propagation Delay
TIBPAL20L8-7C Series . . . 7 ns Max
TIBPAL20L8-10M Series . . . 10 ns Max
•Functionally Equivalent, but Faster Than
Existing 24-Pin PLD Circuits
•Preload Capability on Output Registers
Simplifies Testing
•Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•Security Fuse Prevents Duplication
•Dependable Texas Instruments Quality and
Reliability
DEVICE I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORT
S
PAL20L8 14 2 0 6
PAL20R4 12 0 4 (3-state buffers) 4
PAL20R6 12 0 6 (3-state buffers) 2
PAL20R8 12 0 8 (3-state buffers) 0
description
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X™ circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board
space.
All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow loading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.
The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for
operation over the full military temperature range of −55°C to 125°C.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
I
I
I
I
I
I
I
I
I
I
I
GND
VCC
I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
TIBPAL20L8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O
I/O
I/O
NC
I/O
I/O
I/O
I
I
I
NC
I
I
I
426
14 15 16 17 18
I
I
GND
NC
I
I
O
I
I
I
NC
I
O
TIBPAL20L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
NC −No internal connection
Pin assignments in operating mode
V
CC
OBSOLETE - No Longer Available
TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
CLK
I
I
I
I
I
I
I
I
I
I
GND
I
I/O
I/O
Q
Q
Q
Q
I/O
I/O
I
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
OE
TIBPAL20R4’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
I
I
GND
NC
I
I/O
I
I
CLK
NC
I
I/O
(TOP VIEW)
VCC
11 19
12 13 14 15 16 17 18
4
10
9
8
7
6
5 I/O
20
21
22
23
24
25
3 2 1 282726
I
I
I
NC
I
I
I
Q
Q
NC
Q
Q
I/O
TIBPAL20R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
NC −No internal connection
OE
CLK
I
I
I
I
I
I
I
I
I
I
GND
I
I/O
Q
Q
Q
Q
Q
Q
I/O
I
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13 OE
I
I
GND
NC
I
I/O
I
I
CLK
NC
I
I/O
VCC
11 19
12 13 14 15 16 17 18
4
10
9
8
7
6
5Q
20
21
22
23
24
25
3 2 1 282726
I
I
I
NC
I
I
I
Q
Q
NC
Q
Q
Q
OE
VCC
(TOP VIEW)
TIBPAL20R6’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
TIBPAL20R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
CLK
I
I
I
I
I
I
I
I
I
I
GND
I
Q
Q
Q
Q
Q
Q
Q
Q
I
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13 OE
I
I
GND
NC
I
Q
I
I
CLK
NC
I
Q
VCC
11 19
12 13 14 15 16 17 18
4
10
9
8
7
6
5Q
20
21
22
23
24
25
3 2 1 282726
I
I
I
NC
I
I
I
Q
Q
NC
Q
Q
Q
OE
VCC
(TOP VIEW)
TIBPAL20R8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
TIBPAL20R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
Pin assignments in operating mode
OBSOLETE - No Longer Available
TIBPAL20L8-7C, TIBPAL20R4-7C
TIBPAL20L8-10M, TIBPAL20R4-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
functional block diagrams (positive logic)
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I
EN ≥1
&
40 X 64
14 20
206
7
7
7
7
7
7
7
7
6
20 x
denotes fused inputs
Q
I/O
I/O
I/O
I/O
I
EN
12 20
204
7
7
7
8
8
8
7
4
20 x
≥1
&
40 X 64
≥1
8
Q
Q
Q
4
1D
I = 0 2
CLK C1
EN 2
OE
4
TIBPAL20L8’
TIBPAL20R4’
OBSOLETE - No Longer Available
TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
functional block diagrams (positive logic)
denotes fused inputs
TIBPAL20R6’
TIBPAL20R8’
Q
I/O
I/O
I
EN
12 20
202
7
8
8
8
7
2
20 x
≥1
&
40 X 64
≥1
8
Q
Q
Q
6
1D
I = 0 2
CLK C1
EN 2
OE
6
8Q
8Q
Q
I12 20
208
8
8
8
8
20 x
8
Q
Q
Q
1D
I = 0 2
CLK C1
EN 2
8Q
8Q
&
40 X 64
≥1
OE
8Q
8Q
OBSOLETE - No Longer Available
4 8 12 16 20 24 28 32
I3
I4
I5
I6
I7
I8
I9
I10
O
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
O
15
I
14
Increment
I1
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
2520
First Fuse
Numbers
36 390
I2I
23
I11 I
13
TIBPAL20L8-7C
TIBPAL20L8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
logic diagram (positive logic)
OBSOLETE - No Longer Available
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
4 8 12 16 20 24 28 32
I3
I4
I5
I6
I7
I8
I9
I10
I/O
22
I/O
21
I/O
16
I/O
15
Increment
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
2520
First Fuse
Numbers
36 390
I2I
23
I11 I
14
Q
20
Q
19
Q
18
Q
17
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
13 OE
CLK 1
TIBPAL20R4-7C
TIBPAL20R4-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
logic diagram (positive logic)
OBSOLETE - No Longer Available
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
4 8 12 16 20 24 28 32
I3
I4
I5
I6
I7
I8
I9
I10
I/O
22
I/O
15
Increment
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
2520
First Fuse
Numbers
36 390
I2I
23
I11 I
14
Q
20
Q
19
Q
18
Q
17
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
13 OE
CLK 1
Q
21
C1
1D
I = 0
Q
16
C1
1D
I = 0
TIBPAL20R6-7C
TIBPAL20R6-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
logic diagram (positive logic)
OBSOLETE - No Longer Available
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
4 8 12 16 20 24 28 32
I3
I4
I5
I6
I7
I8
I9
I10
Increment
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
2520
First Fuse
Numbers
36 390
I2I
23
I11 I
14
Q
20
Q
19
Q
18
Q
17
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
13 OE
CLK 1
Q
21
C1
1D
I = 0
Q
16
C1
1D
I = 0
Q
22
C1
1D
I = 0
Q
15
C1
1D
I = 0
TIBPAL20R8-7C
TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
logic diagram (positive logic)
OBSOLETE - No Longer Available
TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage (see Note 2) 2 5.5 V
VIL Low-level input voltage (see Note 2) 0.8 V
IOH High-level output current −3.2 mA
IOL Low-level output current 24 mA
fclock†Clock frequency 0 100 MHz
High 5
Low 5
tsu†Setup time, input or feedback before clock↑7 ns
th†Hold time, input or feedback after clock↑0 ns
TAOperating free-air temperature 0 25 75 °C
†fclock, tw, tsu, and th do not apply for TIBPAL20L8’.
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
ns
Pulse duration, clock (see Note 2)tw†
OBSOLETE - No Longer Available
I, I/O O, I/Otpd ns
TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.75 V, II = −18 mA −0.8 −1.5 V
VOH VCC = 4.75 V, IOH = −3.2 mA 2.4 3.2 V
VOL VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V
IOZH‡VCC = 5.25 V, VO = 2.7 V 100 μA
IOZL‡VCC = 5.25 V, VO = 0.4 V −100 μA
IIVCC = 5.25 V, VI = 5.5 V 100 μA
IIH‡VCC = 5.25 V, VI = 2.7 V 25 μA
IIL‡VCC = 5.25 V, VI = 0.4 V −80 −250 μA
IOS§VCC = 5.25 V, VO = 0.5 V −30 −70 −130 mA
ICC VCC = 5.25 V, VI = 0, Outputs open 150 210 mA
Cif = 1 MHz, VI = 2 V 5 pF
Cof = 1 MHz, VO = 2 V 6 pF
Cclk f = 1 MHz, VCLK = 2 V 6 pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITION MIN TYP†MAX UNIT
without feedback 100
fmaxwith internal feedback
(counter configuration) 100 MHz
with external feedback 74
1 or 2 outputs switching 3 5.5 7
8 outputs switching R1 = 200 Ω, 3 6 7.5
tpd CLK↑QR2 = 390 Ω, 2 4 6.5 ns
tpd#CLK↑Feedback input See Figure 6 3 ns
ten OE↓Q 4 7.5 ns
tdis OE↑Q 4 7.5 ns
ten I, I/O O, I/O 6 9 ns
tdis I, I/O O, I/O 6 9 ns
tsk(o)|| Skew between registered outputs 0.5 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
See section for fmax specifications.
#This parameter applies to TIBPAL20R4’ and TIBPAL20R6’ only (see Figure 4 for illustration) and is calculated from the measured fmax with internal
feedback in the counter configuration.
|| This parameter is the measurement of the difference between the fastest and slowest tpd (CLK-to-Q) observed when multiple registered outputs
are switching in the same direction.
OBSOLETE - No Longer Available
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −2 mA
IOL Low-level output current 12 mA
fclock†Clock frequency 0 62.5 MHz
High 8
Low 8
tsu†Setup time, input or feedback before clock↑10 ns
th†Hold time, input or feedback after clock↑0 ns
TAOperating free-air temperature −55 25 125 °C
†fclock, tw, tsu, and th do not apply for TIBPAL20L8’.
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
ns
Pulse duration, clock (see Note 2)tw†
OBSOLETE - No Longer Available
μAVI = 2.7 V
VCC = 5.5 V,
IIH‡
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = −18 mA −0.8 −1.5 V
VOH VCC = 4.5 V, IOH = −2 mA 2.4 3.2 V
VOL VCC = 4.5 V, IOL = 12 mA 0.3 0.5 V
IOZH‡VCC = 5.5 V, VO = 2.7 V 20 μA
IOZL‡VCC = 5.5 V, VO = 0.4 V −0.1 mA
IIVCC = 5.5 V, VI = 5.5 V 1 mA
I/O ports 100
All others 25
IIL‡VCC = 5.5 V, VI = 0.4 V −0.08 −0.25 mA
IOS§VCC = 5.5 V, VO = 0.5 V −30 −70 −130 mA
ICC VCC = 5.5 V,
VI = 0,
Outputs open
OE = VIH 140 220 mA
Cif = 1 MHz, VI = 2 V 5 pF
Cof = 1 MHz, VO = 2 V 6 pF
Cclk f = 1 MHz, VCLK = 2 V 6 pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITION MIN TYP†MAX UNIT
without feedback 62.5
fmaxwith internal feedback
(counter configuration) 62.5 MHz
with external feedback 50
tpd I, I/O O, I/O R1 = 390 Ω, 1 6 10 ns
tpd CLK↑QR2 = 750 Ω, 1 4 10 ns
tpd#CLK↑Feedback input See Figure 6 5 ns
ten OE↓Q 1 4 10 ns
tdis OE↑Q 1 4 10 ns
ten I, I/O O, I/O 1 6 12 ns
tdis I, I/O O, I/O 1 6 10 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
See section for fmax specifications. fmax with external feedback is not production tested but is calculated from the equation found in the fmax
specification section.
#This parameter applies to TIBPAL20R4’ and TIBPAL20R6’ only (see Figure 4 for illustration) and is calculated from the measured fmax with internal
feedback in the counter configuration.
OBSOLETE - No Longer Available
TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1. With VCC at 5 volts and Pin 1 at VIL, raise Pin 13 to VIHH.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse Pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower Pin 13 to VIL. Preload can be verified by observing the
voltage level at the output pin.
td
tsu
tw
td
VIHH
VIL
VIL
VOL
VOH
VIH
Pin 13
Pin 1
Registered I/O Input Output
VIH
VIL
Figure 1. Preload Waveforms
NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 v
OBSOLETE - No Longer Available
TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
14
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
1.5 V
tsu‡
tpd†
tw
VIL
VIH
5 V
VCC
Active Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
(600 ns TYP, 1000 ns MAX)
1.5 V
†This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
OBSOLETE - No Longer Available
TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15
fmax SPECIFICATIONS
fmax without feedback, see Figure 3
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (tsu + th).
However, the minimum fmax is determined by the minimum clock period (tw high + tw low).
Thus, fmax without feedback +1
(twhigh )twlow) or 1
(tsu )th).
CLK
LOGIC
ARRAY
tsu + th
or
tw high + tw low
C1
1D
Figure 3. fmax Without Feedback
fmax with internal feedback, see Figure 4
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
Thus, fmax with internal feedback +1
(tsu )tpd CLK *to *FB).
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
LOGIC
ARRAY
tsu tpd CLK - to- FB
C1
1D
Figure 4. fmax With Internal Feedback
OBSOLETE - No Longer Available
TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16
fmax SPECIFICATIONS
fmax with external feedback, see Figure 5
This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals
(tsu + tpd CLK-to-Q).
Thus, fmax with external feedback +1
(tsu )tpd CLK *to *Q).
tpd CLK - to- Q tsu
CLK
LOGIC
ARRAY
NEXT DEVICE
tsu
C1
1D
Figure 5. fmax With External Feedback
OBSOLETE - No Longer Available
TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17
PARAMETER MEASUREMENT INFORMATION
tsu
S1
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V
1.5 V
th
1.5 V
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
1.5 V 1.5 V
1.5 V 1.5 V
tw
1.5 V 1.5 V
≈ 3.3 V
VOL
VOH
VOH −0.5 V
≈ 0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
R1
VOL +0.5 V
5 V
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
From Output
Under Test
Test
Point
Input
Out-of-Phase
Output
(see Note D)
Timing
Input
Data
Input
In-Phase
Output
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty cycle = 50%. For C suffix, use the voltage levels
indicated inparentheses ( ). For M suffix, use the voltage levels indicated in brackets [ ].
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 6. Load Circuit and Voltage Waveforms
OBSOLETE - No Longer Available
TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
18
TYPICAL CHARACTERISTICS
160
140
120
100
−75 −50 −25 0 25 50
Figure 7
180
200
SUPPLY CURRENT
vs
FREE- AIR TEMPERATURE
220
75 100 125
TA − Free - Air Temperature −°C
ICC − Supply Current − mA
4
2
1
0
4.5 4.75 5
Figure 8
Propagation Delay Time − ns
6
7
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
8
5.25 5.5
5
3
VCC − Supply Voltage − V
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
1 Output Switching
CL − Load Capacitance − pF
4
2
1
0
−75 −50 −25 0 25 50
Figure 9
Propagation Delay Time − ns
6
7
8
75 100 125
5
3
PROPAGATION DELAY TIME
vs
FREE- AIR TEMPERATURE
VCC = 5 V
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
TA − Free - Air Temperature −°C
8
4
2
0
100 200 300 400
Figure 10
Propagation Delay Time − ns
12
14
16
500
10
6
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
VCC = 5 V
TA = 25 °C
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
0 600
OBSOLETE - No Longer Available
TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS005E − D3307, OCTOBER 1989 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19
TYPICAL CHARACTERISTICS
Number of Outputs Switching
0.4
0.2
0.1
0
23 4 5 6
Figure 12
0.6
0.7
0.8
78
0.5
0.3
PROPAGATION DELAY TIME†
vs
NUMBER OF OUTPUTS SWITCHING
VCC = 5 V
TA = 25 °C
R1 = 200 Ω
R2 = 390 Ω
CL = 50 pF
8-Bit Counter
4
2
1
0
012345
Figure 13
Propagation Delay Time − ns
6
7
8
678
5
3
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
tskew − Skew Between Outputs Switching − ns
VCC = 5 V
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
Number of Outputs Switching
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
1 4 10 40 100
Figure 11
F − Frequency − MHz
POWER DISSIPATION
vs
FREQUENCY
8- BIT COUNTER MODE
800
600
1000
700
900
VCC = 5 V
PD − Power Dissipation − mW
TA = 0 °C
TA = 25 °C
TA = 80 °C
†Outputs switching in the same direction (tPLH compared to tPLH/tPHL to tPHL)
OBSOLETE - No Longer Available
PACKAGE OPTION ADDENDUM
www.ti.com 21-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-87671153A OBSOLETE LCCC FK 28 TBD Call TI Call TI
5962-8767115KA OBSOLETE CFP W 24 TBD Call TI Call TI
5962-8767115LA OBSOLETE CDIP JT 24 TBD Call TI Call TI
5962-87671163A OBSOLETE LCCC FK 28 TBD Call TI Call TI
5962-8767116KA OBSOLETE CFP W 24 TBD Call TI Call TI
5962-8767116LA OBSOLETE CDIP JT 24 TBD Call TI Call TI
5962-87671173A OBSOLETE LCCC FK 28 TBD Call TI Call TI
5962-8767117KA OBSOLETE CFP W 24 TBD Call TI Call TI
5962-8767117LA OBSOLETE CDIP JT 24 TBD Call TI Call TI
5962-87671183A OBSOLETE LCCC FK 28 TBD Call TI Call TI
5962-8767118KA OBSOLETE CFP W 24 TBD Call TI Call TI
5962-8767118LA OBSOLETE CDIP JT 24 TBD Call TI Call TI
TIBPAL20L8-10MFKB OBSOLETE LCCC FK 28 TBD Call TI Call TI
TIBPAL20L8-10MJTB OBSOLETE CDIP JT 24 TBD Call TI Call TI
TIBPAL20L8-10MWB OBSOLETE CFP W 24 TBD Call TI Call TI
TIBPAL20L8-7CFN OBSOLETE PLCC FN 28 TBD Call TI Call TI
TIBPAL20L8-7CNT OBSOLETE PDIP NT 24 TBD Call TI Call TI
TIBPAL20R4-10MFKB OBSOLETE LCCC FK 28 TBD Call TI Call TI
TIBPAL20R4-10MJTB OBSOLETE CDIP JT 24 TBD Call TI Call TI
TIBPAL20R4-10MWB OBSOLETE CFP W 24 TBD Call TI Call TI
TIBPAL20R4-7CFN OBSOLETE PLCC FN 28 TBD Call TI Call TI
TIBPAL20R4-7CNT OBSOLETE PDIP NT 24 TBD Call TI Call TI
TIBPAL20R6-10MFKB OBSOLETE LCCC FK 28 TBD Call TI Call TI
TIBPAL20R6-10MJTB OBSOLETE CDIP JT 24 TBD Call TI Call TI
TIBPAL20R6-10MWB OBSOLETE CFP W 24 TBD Call TI Call TI
TIBPAL20R6-7CFN OBSOLETE PLCC FN 28 TBD Call TI Call TI
TIBPAL20R6-7CNT OBSOLETE PDIP NT 24 TBD Call TI Call TI
TIBPAL20R8-10MFKB OBSOLETE LCCC FK 28 TBD Call TI Call TI
TIBPAL20R8-10MJTB OBSOLETE CDIP JT 24 TBD Call TI Call TI
TIBPAL20R8-10MWB OBSOLETE CFP W 24 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 21-Mar-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TIBPAL20R8-7CFN NRND PLCC FN 28 37 TBD CU Level-1-220C-UNLIM
TIBPAL20R8-7CNT NRND PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0°–15°
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN (6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MECHANICAL DATA
MCFP007 – OCTOBER 1994
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W (R-GDFP-F24) CERAMIC DUAL FLATPACK
4040180-5/B 03/95
1.115 (28,32)
0.090 (2,29)
0.375 (9,53)
0.019 (0,48)
0.030 (0,76)
0.045 (1,14)
0.006 (0,15)
0.045 (1,14)
0.015 (0,38)
0.015 (0,38)
0.026 (0,66)
0.004 (0,10)
0.340 (8,64)
0.840 (21,34)
124
0.360 (9,14)
0.240 (6,10)
1312
Base and Seating Plane
30° TYP
0.360 (9,14)
0.240 (6,10)
0.395 (10,03)
0.360 (9,14)
0.640 (16,26)
0.490 (12,45)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
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