93LC46A/ST - Microchip Technology

 2002-2011 Microchip Technology Inc. DS21749J-page 1

93AA46A/B/C, 93LC46A/B/C,

93C46A/B/C

Device Selection Table

Features:

• Low-Power CMOS Technology

• ORG Pin to Select Word Size for ‘46C’ Version

• 128 x 8-bit Organization ‘A’ Devices (no ORG)

• 64 x 16-bit Organization ‘B’ Devices (no ORG)

• Self-Timed Erase/Write Cycles (including

Auto-Erase)

• Automatic Erase All (ERAL) Before Write All

(WRAL)

• Power-On/Off Data Protection Circuitry

• Industry Standard 3-Wire Serial I/O

• Device Status Signal (Ready/Busy)

• Sequential Read Function

• 1,000,000 Erase/Write Cycles

• Data Retention > 200 Years

• Pb-free and RoHS Compliant

• Temperature Ranges Supported:

Pin Function Table

Description:

The Microchip Technology Inc. 93XX46A/B/C devices

are 1Kbit low-voltage serial Electrically Erasable

PROMs (EEPROM). Word-selectable devices such as

the 93AA46C, 93LC46C or 93C46C are dependent

upon external logic levels driving the ORG pin to set

word size. For dedicated 8-bit communication, the

93AA46A, 93LC46A or 93C46A devices are available,

while the 93AA46B, 93LC46B and 93C46B devices

provide dedicated 16-bit communication. Advanced

CMOS technology makes these devices ideal for low-

power, nonvolatile memory applications. The entire

93XX Series is available in standard packages includ-

ing 8-lead PDIP and SOIC, and advanced packaging

including 8-lead MSOP, 6-lead SOT-23, 8-lead

2x3 DFN/TDFN and 8-lead TSSOP. All packages are

Pb-free (Matte Tin) finish.

Part Number VCC Range ORG Pin Word Size Temp Ranges Packages

93AA46A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT, MC, MN

93AA46B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT, MC, MN

93LC46A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC, MN

93LC46B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC, MN

93C46A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC, MN

93C46B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC, MN

93AA46C 1.8-5.5 Yes 8- or 16-bit I P, SN, ST, MS, MC, MN

93LC46C 2.5-5.5 Yes 8- or 16-bit I, E P, SN, ST, MS, MC, MN

93C46C 4.5-5.5 Yes 8- or 16-bit I, E P, SN, ST, MS, MC, MN

- Industrial (I) -40°C to +85°C

- Automotive (E) -40°C to +125°C

Name Function

CS Chip Select

CLK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

VSS Ground

NC No internal connection

ORG Memory Configuration

VCC Power Supply

1K Microwire Compatible Serial EEPROM

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

DS21749J-page 2  2002-2011 Microchip Technology Inc.

Package Types (not to scale)

CLK

ORG

PDIP/SOIC

(P, SN)

CLK DI

NC ORG*

ROTATED SOIC

(ex: 93LC46BX)

TSSOP/MSOP

CLK

ORG*

(ST, MS) SOT-23

CLK

(OT)

*ORG pin is NC on A/B devices

DFN/TDFN

CLK

ORG*

VSS

VCC

(MC, MN)

 2002-2011 Microchip Technology Inc. DS21749J-page 3

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins  4kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

All parameters apply over the specified

ranges unless otherwise noted.

Industrial (I): TA = -40°C to +85°C, VCC = +1.8V TO +5.5V

Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V

Param.

No. Symbol Parameter Min. Typ Max. Units Conditions

D1 VIH1

VIH2

High-level input voltage 2.0

0.7 VCC

—

VCC +1

VCC 2.7V

VCC 2.7V

D2 VIL1

VIL2

Low-level input voltage -0.3

-0.3

—

0.8

0.2 VCC

VCC 2.7V

VCC 2.7V

D3 VOL1

VOL2

Low-level output voltage —

—

0.4

0.2

IOL = 2.1 mA, VCC = 4.5V

IOL = 100 A, VCC = 2.5V

D4 VOH1

VOH2

High-level output voltage 2.4

VCC - 0.2

—

IOH = -400 A, VCC = 4.5V

IOH = -100 A, VCC = 2.5V

D5 ILI Input leakage current — — ±1 AVIN = VSS or VCC

D6 ILO Output leakage current — — ±1 AVOUT = VSS or VCC

D7 CIN,

COUT

Pin capacitance

(all inputs/outputs)

——7pFVIN/VOUT = 0V (Note 1)

A = 25°C, FCLK = 1 MHz

D8 ICC

write

Write current —

—

500

—

A

FCLK = 3 MHz, VCC = 5.5V

FCLK = 2 MHz, VCC = 2.5V

D9 ICC read Read current —

—

100

500

—

A

FCLK = 3 MHz, VCC = 5.5V

FCLK = 2 MHz, VCC = 3.0V

FCLK = 2 MHz, VCC = 2.5V

D10 ICCS Standby current —

—

A

I-Temp

E-Temp

CLK = CS = 0V

ORG = DI = VSS or VCC

(Note 2) (Note 3)

D11 VPOR VCC voltage detect

—

1.5

3.8

—

(Note 1)

93AA46A/B/C, 93LC46A/B/C

93C46A/B/C

Note 1: This parameter is periodically sampled and not 100% tested.

2: ORG pin not available on ‘A’ or ‘B’ versions.

3: Ready/Busy status must be cleared from DO; see Section 3.4 “Data Out (DO)”.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

DS21749J-page 4  2002-2011 Microchip Technology Inc.

TABLE 1-2: AC CHARACTERISTICS

All parameters apply over the specified

ranges unless otherwise noted.

Industrial (I): T

A = -40°C to +85°C, VCC = +1.8V TO +5.5V

Automotive (E): T

A = -40°C to +125°C, VCC = +2.5V TO +5.5V

Param.

No. Symbol Parameter Min. Max. Units Conditions

A1 FCLK Clock frequency — 3

MHz

4.5VVCC  5.5V, 93XX46C only

2.5V VCC  5.5V

1.8V VCC 2.5V

A2 TCKH Clock high time 200

250

450

—ns

4.5VVCC  5.5V, 93XX46C only

2.5V VCC  5.5V

1.8V VCC 2.5V

A3 TCKL Clock low time 100

200

450

—ns

4.5VVCC  5.5V, 93XX46C only

2.5V VCC  5.5V

1.8V VCC 2.5V

A4 TCSS Chip Select setup time 50

100

250

—ns

4.5VVCC  5.5V

2.5V VCC  4.5V

1.8V VCC 2.5V

A5 TCSH Chip Select hold time 0 — ns 1.8V VCC 5.5V

A6 TCSL Chip Select low time 250 — ns 1.8V VCC 5.5V

A7 TDIS Data input setup time 50

100

250

—ns4.5VVCC  5.5V, 93XX46C only

2.5V VCC  5.5V

1.8V VCC 2.5V

A8 TDIH Data input hold time 50

100

250

—ns4.5VVCC  5.5V, 93XX46C only

2.5V VCC  5.5V

1.8V VCC 2.5V

A9 TPD Data output delay time —

—

200

250

400

ns 4.5VVCC  5.5V, CL = 100 pF

2.5V VCC  4.5V, CL = 100 pF

1.8V VCC 2.5V, CL = 100 pF

A10 TCZ Data output disable time —

—

100

200

ns 4.5VVCC 5.5V, (Note 1)

1.8VVCC  4.5V, (Note 1)

A11 TSV Status valid time — 200

300

500

ns 4.5VVCC  5.5V, CL = 100 pF

2.5V VCC  4.5V, CL = 100 pF

1.8V VCC 2.5V, CL = 100 pF

A12 TWC Program cycle time — 6 ms Erase/Write mode (AA and LC

versions)

A13 TWC — 2 ms Erase/Write mode (93C versions)

A14 TEC — 6 ms ERAL mode, 4.5V  VCC  5.5V

A15 TWL — 15 ms WRAL mode, 4.5V  VCC  5.5V

A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This application is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which may be obtained from Microchip’s web

site at www.microchip.com.

 2002-2011 Microchip Technology Inc. DS21749J-page 5

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

FIGURE 1-1: SYNCHRONOUS DATA TIMING

TABLE 1-3: INSTRUCTION SET FOR X16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)

TABLE 1-4: INSTRUCTION SET FOR X8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE 1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY)9

ERAL 1 00 10XXXX — (RDY/BSY)9

EWDS 1 00 00XXXX — High-Z 9

EWEN 1 00 11XXXX — High-Z 9

READ 1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25

WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)25

WRAL 1 00 01XXXXD15 - D0 (RDY/BSY)25

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE 1 11 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)10

ERAL 1 00 10XXXXX — (RDY/BSY)10

EWDS 1 00 00XXXXX —High-Z 10

EWEN 1 00 11XXXXX —High-Z 10

READ 1 10 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 18

WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)18

WRAL 1 00 01XXXXX D7 - D0 (RDY/BSY)18

CS VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

CLK

(Read)

(Program)

TCSS

TDIS

TCKH TCKL

TDIH

TPD

TCSH

TPD

TCZ

Status Valid

TSV

TCZ

Note: TSV is relative to CS.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

DS21749J-page 6  2002-2011 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

When the ORG pin (93XX46C) is connected to VCC,

the (x16) organization is selected. When it is connected

to ground, the (x8) organization is selected. Instruc-

tions, addresses and write data are clocked into the DI

pin on the rising edge of the clock (CLK). The DO pin is

normally held in a High-Z state except when reading

data from the device, or when checking the Ready/

Busy status during a programming operation. The

Ready/Busy status can be verified during an erase/

write operation by polling the DO pin; DO low indicates

that programming is still in progress, while DO high

indicates the device is ready. DO will enter the High-Z

state on the falling edge of CS.

2.1 Start Condition

The Start bit is detected by the device if CS and DI are

both high with respect to the positive edge of CLK for

the first time.

Before a Start condition is detected, CS, CLK and DI

may change in any combination (except to that of a

Start condition), without resulting in any device

operation (Read, Write, Erase, EWEN, EWDS, ERAL

or WRAL). As soon as CS is high, the device is no

longer in Standby mode.

An instruction following a Start condition will only be

executed if the required opcode, address and data bits

for any particular instruction are clocked in.

2.2 Data In/Data Out (DI/DO)

It is possible to connect the Data In and Data Out pins

together. However, with this configuration it is possible

for a “bus conflict” to occur during the “dummy zero”

that precedes the read operation if A0 is a logic high

level. Under such a condition the voltage level seen at

Data Out is undefined and will depend upon the relative

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0,

the higher the voltage at the Data Out pin. In order to

limit this current, a resistor should be connected

between DI and DO.

2.3 Data Protection

All modes of operation are inhibited when VCC is below

a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices

or 3.8V for ‘93C’ devices.

The EWEN and EWDS commands give additional

protection against accidentally programming during

normal operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before the initial ERASE or WRITE instruction

can be executed.

Block Diagram

Note: When preparing to transmit an instruction,

either the CLK or DI signal levels must be

at a logic low as CS is toggled active high.

Note: For added protection, an EWDS command

should be performed after every write

operation and an external 10 k pull-

down protection resistor should be added

to the CS pin.

Memory

Array

Data Register

Mode

Decode

Logic

Clock

Address

Decoder

Address

Counter

Output

Buffer

ORG*

CLK

VCC VSS

*ORG input is not available on A/B devices

 2002-2011 Microchip Technology Inc. DS21749J-page 7

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.4 Erase

The ERASE instruction forces all data bits of the

specified address to the logical ‘1’ state. CS is brought

low following the loading of the last address bit. This

falling edge of the CS pin initiates the self-timed

programming cycle, except on ‘93C’ devices where the

rising edge of CLK before the last address bit initiates

the write cycle.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the device is ready for another instruction.

FIGURE 2-1: ERASE TIMING FOR 93AA AND 93LC DEVICES

FIGURE 2-2: ERASE TIMING FOR 93C DEVICES

Note: After the Erase cycle is complete, issuing

a Start bit and then taking CS low will clear

the Ready/Busy status from DO.

CLK

TCSL

Check Status

111ANAN-1 AN-2 ••• A0

TSV TCZ

Busy Ready

High-Z

TWC

High-Z

CLK

TCSL

Check Status

111ANAN-1 AN-2 ••• A0

TSV TCZ

Busy Ready

High-Z

TWC

High-Z

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

DS21749J-page 8  2002-2011 Microchip Technology Inc.

2.5 Erase All (ERAL)

The Erase All (ERAL) instruction will erase the entire

memory array to the logical ‘1’ state. The ERAL cycle

is identical to the erase cycle, except for the different

opcode. The ERAL cycle is completely self-timed and

commences at the falling edge of the CS, except on

‘93C’ devices where the rising edge of CLK before the

last data bit initiates the write cycle. Clocking of the

CLK pin is not necessary after the device has entered

the ERAL cycle.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL).

VCC must be 4.5V for proper operation of ERAL.

FIGURE 2-3: ERAL TIMING FOR 93AA AND 93LC DEVICES

FIGURE 2-4: ERAL TIMING FOR 93C DEVICES

Note: After the ERAL command is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

CLK

TCSL

Check Status

100 10x

••• x

TSV TCZ

Busy Ready

High-Z

TEC

High-Z

VCC must be 4.5V for proper operation of ERAL.

CLK

TCSL

Check Status

100 10x

••• x

TSV TCZ

Busy Ready

High-Z

TEC

High-Z

 2002-2011 Microchip Technology Inc. DS21749J-page 9

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.6 Erase/Write Disable and Enable

(EWDS/EWEN)

The 93XX46A/B/C powers up in the Erase/Write Disable

(EWDS) state. All programming modes must be preceded

by an Erase/Write Enable (EWEN) instruction. Once the

EWEN instruction is executed, programming remains

enabled until an EWDS instruction is executed or Vcc is

removed from the device.

To protect against accidental data disturbance, the EWDS

instruction can be used to disable all erase/write functions

and should follow all programming operations. Execution

of a READ instruction is independent of both the EWEN and

EWDS instructions.

FIGURE 2-5: EWDS TIMING

FIGURE 2-6: EWEN TIMING

2.7 Read

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit precedes the 8-bit (if ORG pin is low or A-version

devices) or 16-bit (if ORG pin is high or B-version

devices) output string.

The output data bits will toggle on the rising edge of the

CLK and are stable after the specified time delay (TPD).

Sequential read is possible when CS is held high. The

memory data will automatically cycle to the next register

and output sequentially.

FIGURE 2-7: READ TIMING

CLK

DI 10

000x ••• x

TCSL

CLK

DI 00 1 1x

TCSL

•••

CLK

110

AN••• A0

High-Z 0Dx ••• D0 Dx ••• D0 •••

Dx D0

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

DS21749J-page 10  2002-2011 Microchip Technology Inc.

2.8 Write

The WRITE instruction is followed by 8 bits (if ORG is

low or A-version devices) or 16 bits (if ORG pin is high

or B-version devices) of data, which are written into the

specified address. For 93AA46A/B/C and 93LC46A/B/C

devices, after the last data bit is clocked into DI, the

falling edge of CS initiates the self-timed auto-erase and

programming cycle. For 93C46A/B/C devices, the self-

timed auto-erase and programming cycle is initiated by

the rising edge of CLK on the last data bit.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the data specified and the device is ready for another

instruction.

FIGURE 2-8: WRITE TIMING FOR 93AA AND 93LC DEVICES

FIGURE 2-9: WRITE TIMING FOR 93C DEVICES

Note: After the Write cycle is complete, issuing a

Start bit and then taking CS low will clear

the Ready/Busy status from DO.

CLK

101AN••• A0 Dx ••• D0

Busy Ready High-Z

High-Z

TWC

TCSL

TCZ

TSV

CLK

101AN••• A0 Dx ••• D0

Busy Ready High-Z

High-Z

TWC

TCSL

TCZ

TSV

 2002-2011 Microchip Technology Inc. DS21749J-page 11

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.9 Write All (WRAL)

The Write All (WRAL) instruction will write the entire

memory array with the data specified in the command.

For 93AA46A/B/C and 93LC46A/B/C devices, after the

last data bit is clocked into DI, the falling edge of CS

initiates the self-timed auto-erase and programming

cycle. For 93C46A/B/C devices, the self-timed auto-

erase and programming cycle is initiated by the rising

edge of CLK on the last data bit. Clocking of the CLK

pin is not necessary after the device has entered the

WRAL cycle. The WRAL command does include an

automatic ERAL cycle for the device. Therefore, the

WRAL instruction does not require an ERAL instruction,

but the chip must be in the EWEN status.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL).

VCC must be 4.5V for proper operation of WRAL.

FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES

FIGURE 2-11: WRAL TIMING FOR 93C DEVICES

Note: After the Write All cycle is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

CLK

HIGH-Z

10001 x

••• xDx ••• D0

High-Z Busy Ready

TWL

VCC must be 4.5V for proper operation of WRAL.

TCSL

TSV TCZ

CLK

HIGH-Z

10001 x

••• xDx ••• D0

High-Z Busy Ready

TWL

TCSL

TSV TCZ

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

DS21749J-page 12  2002-2011 Microchip Technology Inc.

3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN DESCRIPTIONS

3.1 Chip Select (CS)

A high level selects the device; a low level deselects

the device and forces it into Standby mode. However, a

programming cycle that is already in progress will be

completed, regardless of the Chip Select (CS) input

signal. If CS is brought low during a program cycle, the

device will go into Standby mode as soon as the

programming cycle is completed.

CS must be low for 250 ns minimum (T

CSL) between

consecutive instructions. If CS is low, the internal

control logic is held in a Reset status.

3.2 Serial Clock (CLK)

The Serial Clock is used to synchronize the communi-

cation between a master device and the 93XX series

device. Opcodes, address and data bits are clocked in

on the positive edge of CLK. Data bits are also clocked

out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission

sequence (at high or low level) and can be continued

anytime with respect to clock high time (TCKH) and

clock low time (TCKL). This gives the controlling master

freedom in preparing opcode, address and data.

CLK is a “don't care” if CS is low (device deselected). If

CS is high, but the Start condition has not been

detected (DI = 0), any number of clock cycles can be

received by the device without changing its status (i.e.,

waiting for a Start condition).

CLK cycles are not required during the self-timed write

(i.e., auto erase/write) cycle.

After detection of a Start condition the specified number

of clock cycles (respectively low-to-high transitions of

CLK) must be provided. These clock cycles are

required to clock in all required opcode, address and

data bits before an instruction is executed. CLK and DI

then become “don't care” inputs waiting for a new Start

condition to be detected.

3.3 Data In (DI)

Data In (DI) is used to clock in a Start bit, opcode,

address and data synchronously with the CLK input.

3.4 Data Out (DO)

Data Out (DO) is used in the Read mode to output data

synchronously with the CLK input (TPD after the

positive edge of CLK).

This pin also provides Ready/Busy status information

during erase and write cycles. Ready/Busy status infor-

mation is available on the DO pin if CS is brought high

after being low for minimum Chip Select low time (TCSL)

and an erase or write operation has been initiated.

The Status signal is not available on DO if CS is held

low during the entire erase or write cycle. In this case,

DO is in the High-Z mode. If status is checked after the

erase/write cycle, the data line will be high to indicate

the device is ready.

3.5 Organization (ORG)

When the ORG pin is connected to VCC or Logic HI, the

(x16) memory organization is selected. When the ORG

pin is tied to VSS or Logic LO, the (x8) memory

organization is selected. For proper operation, ORG

must be tied to a valid logic level.

93XX46A devices are always (x8) organization and

93XX46B devices are always (x16) organization.

Name PDIP SOIC TSSOP MSOP DFN(1) TDFN(1) SOT-23 Rotated

SOIC Function

CS 1 1 1 1 1 1 5 3 Chip Select

CLK 2 2 2 2 2 2 4 4 Serial Clock

DI 3 3 3 3 3 3 3 5 Data In

DO 4 4 4 4 4 4 1 6 Data Out

Vss 5 5 5 5 5 5 2 7 Ground

ORG/NC 6 6 6 6 6 6 — 8 Organization/93XX46C

No Internal Connection/

93XX46A/B

NC 7 7 7 7 7 7 — 1 No Internal Connection

VCC 8 8 8 8 8 8 6 2 Power Supply

Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.

Note: After a programming cycle is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

 2002-2011 Microchip Technology Inc. DS21749J-page 13

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Example:

6-Lead SOT-23

8-Lead MSOP (150 mil) Example:

XXXXXXT

YWWNNN

3L46BI

5281L7

XXNN 1EL7

T/XXXNNN

XXXXXXXX

YYWW

8-Lead PDIP

8-Lead SOIC

XXXXYYWW

XXXXXXXT

NNN

XXXX

TYWW

8-Lead TSSOP

NNN

I/P 1L7

93LC46B

0528

Example:

SN 0528

93LC46BI

1L7

L46B

I528

Example:

8-Lead Rotated SOIC

XXXXYYWW

XXXXXXXT

NNN

Example:

SN 0528

93L46BXI

1L7

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

DS21749J-page 14  2002-2011 Microchip Technology Inc.

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Part Number

1st Line Marking Codes

TSSOP MSOP

SOT-23 DFN TDFN

I Temp. E Temp. I Temp. E Temp. I Temp. E Temp.

93AA46A A46A 3A46AT 1BNN — 301 — E01 —

93AA46B A46B 3A46BT 1LNN — 311 — E11 —

93AA46C A46C 3A46CT — — 321 — E21 —

93LC46A L46A 3L46AT 1ENN 1FNN 304 — E04 E05

93LC46B L46B 3L46BT 1PNN 1RNN 314 — E14 E15

93LC46C L46C 3L46CT — — 324 — E24 —

93C46A C46A 3C46AT 1HNN 1JNN 307 — E07 E08

93C46B C46B 3C46BT 1TNN 1UNN 317 — E17 E18

93C46C C46C 3C46CT — — 327 — E27 —

Note: T = Temperature grade (I, E)

NN = Alphanumeric traceability code

8-Lead 2x3 DFN Example:

314

528

XXX

YWW

8-Lead 2x3 TDFN Example:

E14

528

XXX

YWW

 2002-2011 Microchip Technology Inc. DS21749J-page 15

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C





 

 

 

 

 

 



 

   

  

  

    

    

    

  

  

  

    

  

   

    

    

NOTE 1

A2 c

L1 L

   

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

DS21749J-page 16  2002-2011 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2002-2011 Microchip Technology Inc. DS21749J-page 17

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

   !"



 

 



 

   

  

  

  

    

    

    

    

    

    

    

    

   

    

    

PIN1IDBY

LASER MARK

123

A2 c

   

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

DS21749J-page 18  2002-2011 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2002-2011 Microchip Technology Inc. DS21749J-page 19

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

#$%"&&'(#$



 

 

 

 





 

   

  

  

    

    

    

    

    

    

    

    

    

    

    

NOTE 1

123

   